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Tim Harveye3946fe2014-02-07 15:24:56 +08001/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Tim Harvey326cdb12014-09-08 23:07:28 -070012#include <dt-bindings/gpio/gpio.h>
13
Tim Harveye3946fe2014-02-07 15:24:56 +080014/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
Tim Harveye3946fe2014-02-07 15:24:56 +080017 ethernet1 = &eth1;
18 led0 = &led0;
19 led1 = &led1;
20 led2 = &led2;
21 nand = &gpmi;
Tim Harveye3946fe2014-02-07 15:24:56 +080022 ssi0 = &ssi1;
23 usb0 = &usbh1;
24 usb1 = &usbotg;
Tim Harveye3946fe2014-02-07 15:24:56 +080025 };
26
27 chosen {
28 bootargs = "console=ttymxc1,115200";
29 };
30
Tim Harveyb3253242014-04-30 23:32:30 -070031 backlight {
32 compatible = "pwm-backlight";
33 pwms = <&pwm4 0 5000000>;
34 brightness-levels = <0 4 8 16 32 64 128 255>;
35 default-brightness-level = <7>;
36 };
37
Tim Harveye3946fe2014-02-07 15:24:56 +080038 leds {
39 compatible = "gpio-leds";
Tim Harveyb5f37b72014-09-08 23:07:30 -070040 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_gpio_leds>;
Tim Harveye3946fe2014-02-07 15:24:56 +080042
43 led0: user1 {
44 label = "user1";
Tim Harvey326cdb12014-09-08 23:07:28 -070045 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
Tim Harveye3946fe2014-02-07 15:24:56 +080046 default-state = "on";
47 linux,default-trigger = "heartbeat";
48 };
49
50 led1: user2 {
51 label = "user2";
Tim Harvey326cdb12014-09-08 23:07:28 -070052 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
Tim Harveye3946fe2014-02-07 15:24:56 +080053 default-state = "off";
54 };
55
56 led2: user3 {
57 label = "user3";
Tim Harvey326cdb12014-09-08 23:07:28 -070058 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
Tim Harveye3946fe2014-02-07 15:24:56 +080059 default-state = "off";
60 };
61 };
62
63 memory {
64 reg = <0x10000000 0x40000000>;
65 };
66
67 pps {
68 compatible = "pps-gpio";
Tim Harveyb5f37b72014-09-08 23:07:30 -070069 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_pps>;
Tim Harvey326cdb12014-09-08 23:07:28 -070071 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
Tim Harveye3946fe2014-02-07 15:24:56 +080072 status = "okay";
73 };
74
75 regulators {
76 compatible = "simple-bus";
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 reg_1p0v: regulator@0 {
81 compatible = "regulator-fixed";
82 reg = <0>;
83 regulator-name = "1P0V";
84 regulator-min-microvolt = <1000000>;
85 regulator-max-microvolt = <1000000>;
86 regulator-always-on;
87 };
88
89 /* remove when pmic 1p8 regulator available */
90 reg_1p8v: regulator@1 {
91 compatible = "regulator-fixed";
92 reg = <1>;
93 regulator-name = "1P8V";
94 regulator-min-microvolt = <1800000>;
95 regulator-max-microvolt = <1800000>;
96 regulator-always-on;
97 };
98
99 reg_3p3v: regulator@2 {
100 compatible = "regulator-fixed";
101 reg = <2>;
102 regulator-name = "3P3V";
103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>;
105 regulator-always-on;
106 };
107
108 reg_usb_h1_vbus: regulator@3 {
109 compatible = "regulator-fixed";
110 reg = <3>;
111 regulator-name = "usb_h1_vbus";
112 regulator-min-microvolt = <5000000>;
113 regulator-max-microvolt = <5000000>;
114 regulator-always-on;
115 };
116
117 reg_usb_otg_vbus: regulator@4 {
118 compatible = "regulator-fixed";
119 reg = <4>;
120 regulator-name = "usb_otg_vbus";
121 regulator-min-microvolt = <5000000>;
122 regulator-max-microvolt = <5000000>;
Tim Harvey326cdb12014-09-08 23:07:28 -0700123 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
Tim Harveye3946fe2014-02-07 15:24:56 +0800124 enable-active-high;
125 };
126 };
127
128 sound {
Tim Harveyb12d1e92014-05-21 23:04:54 -0700129 compatible = "fsl,imx6q-ventana-sgtl5000",
Tim Harveye3946fe2014-02-07 15:24:56 +0800130 "fsl,imx-audio-sgtl5000";
Tim Harveyb12d1e92014-05-21 23:04:54 -0700131 model = "sgtl5000-audio";
Tim Harveye3946fe2014-02-07 15:24:56 +0800132 ssi-controller = <&ssi1>;
133 audio-codec = <&codec>;
134 audio-routing =
135 "MIC_IN", "Mic Jack",
136 "Mic Jack", "Mic Bias",
137 "Headphone Jack", "HP_OUT";
138 mux-int-port = <1>;
139 mux-ext-port = <4>;
140 };
141};
142
143&audmux {
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_audmux>;
146 status = "okay";
147};
148
149&can1 {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_flexcan1>;
152 status = "okay";
153};
154
155&fec {
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_enet>;
158 phy-mode = "rgmii";
Tim Harvey326cdb12014-09-08 23:07:28 -0700159 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
Tim Harveye3946fe2014-02-07 15:24:56 +0800160 status = "okay";
161};
162
163&gpmi {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_gpmi_nand>;
166 status = "okay";
167};
168
Tim Harveyaef15db2014-04-23 00:47:51 -0700169&hdmi {
170 ddc-i2c-bus = <&i2c3>;
171 status = "okay";
172};
173
Tim Harveye3946fe2014-02-07 15:24:56 +0800174&i2c1 {
175 clock-frequency = <100000>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pinctrl_i2c1>;
178 status = "okay";
179
180 eeprom1: eeprom@50 {
181 compatible = "atmel,24c02";
182 reg = <0x50>;
183 pagesize = <16>;
184 };
185
186 eeprom2: eeprom@51 {
187 compatible = "atmel,24c02";
188 reg = <0x51>;
189 pagesize = <16>;
190 };
191
192 eeprom3: eeprom@52 {
193 compatible = "atmel,24c02";
194 reg = <0x52>;
195 pagesize = <16>;
196 };
197
198 eeprom4: eeprom@53 {
199 compatible = "atmel,24c02";
200 reg = <0x53>;
201 pagesize = <16>;
202 };
203
204 gpio: pca9555@23 {
205 compatible = "nxp,pca9555";
206 reg = <0x23>;
207 gpio-controller;
208 #gpio-cells = <2>;
209 };
210
Tim Harveye3946fe2014-02-07 15:24:56 +0800211 rtc: ds1672@68 {
212 compatible = "dallas,ds1672";
213 reg = <0x68>;
214 };
215};
216
217&i2c2 {
218 clock-frequency = <100000>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_i2c2>;
221 status = "okay";
Tim Harveye3946fe2014-02-07 15:24:56 +0800222};
223
224&i2c3 {
225 clock-frequency = <100000>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_i2c3>;
228 status = "okay";
229
Tim Harveye3946fe2014-02-07 15:24:56 +0800230 codec: sgtl5000@0a {
231 compatible = "fsl,sgtl5000";
232 reg = <0x0a>;
233 clocks = <&clks 201>;
234 VDDA-supply = <&reg_1p8v>;
235 VDDIO-supply = <&reg_3p3v>;
236 };
237
Tim Harveye3946fe2014-02-07 15:24:56 +0800238 touchscreen: egalax_ts@04 {
239 compatible = "eeti,egalax_ts";
240 reg = <0x04>;
241 interrupt-parent = <&gpio1>;
Tim Harvey326cdb12014-09-08 23:07:28 -0700242 interrupts = <11 2>;
243 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
Tim Harveye3946fe2014-02-07 15:24:56 +0800244 };
Tim Harveye3946fe2014-02-07 15:24:56 +0800245};
246
Tim Harveyb5f37b72014-09-08 23:07:30 -0700247&ldb {
248 status = "okay";
Tim Harveye3946fe2014-02-07 15:24:56 +0800249
Tim Harveyb5f37b72014-09-08 23:07:30 -0700250 lvds-channel@1 {
251 fsl,data-mapping = "spwg";
252 fsl,data-width = <18>;
253 status = "okay";
254
255 display-timings {
256 native-mode = <&timing0>;
257 timing0: hsd100pxn1 {
258 clock-frequency = <65000000>;
259 hactive = <1024>;
260 vactive = <768>;
261 hback-porch = <220>;
262 hfront-porch = <40>;
263 vback-porch = <21>;
264 vfront-porch = <7>;
265 hsync-len = <60>;
266 vsync-len = <10>;
267 };
Tim Harveye3946fe2014-02-07 15:24:56 +0800268 };
Tim Harveyb5f37b72014-09-08 23:07:30 -0700269 };
270};
Tim Harveye3946fe2014-02-07 15:24:56 +0800271
Tim Harveyb5f37b72014-09-08 23:07:30 -0700272&pcie {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_pcie>;
275 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
276 status = "okay";
277
278 eth1: sky2@8 { /* MAC/PHY on bus 8 */
279 compatible = "marvell,sky2";
280 };
281};
282
283&pwm4 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_pwm4>;
286 status = "okay";
287};
288
289&ssi1 {
Tim Harveyb5f37b72014-09-08 23:07:30 -0700290 status = "okay";
291};
292
293&uart1 {
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_uart1>;
296 status = "okay";
297};
298
299&uart2 {
300 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_uart2>;
302 status = "okay";
303};
304
305&uart5 {
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_uart5>;
308 status = "okay";
309};
310
311&usbotg {
312 vbus-supply = <&reg_usb_otg_vbus>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_usbotg>;
315 disable-over-current;
316 status = "okay";
317};
318
319&usbh1 {
320 vbus-supply = <&reg_usb_h1_vbus>;
321 status = "okay";
322};
323
324&usdhc3 {
325 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_usdhc3>;
327 cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
328 vmmc-supply = <&reg_3p3v>;
329 status = "okay";
330};
331
332&iomuxc {
333 imx6qdl-gw53xx {
Tim Harveye3946fe2014-02-07 15:24:56 +0800334 pinctrl_audmux: audmuxgrp {
335 fsl,pins = <
336 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
337 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
338 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
339 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
Tim Harveyb5f37b72014-09-08 23:07:30 -0700340 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
Tim Harveye3946fe2014-02-07 15:24:56 +0800341 >;
342 };
343
344 pinctrl_enet: enetgrp {
345 fsl,pins = <
346 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
347 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
348 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
349 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
350 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
351 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
352 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
353 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
354 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
355 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
356 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
357 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
358 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
359 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
360 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
361 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
362 >;
363 };
364
365 pinctrl_flexcan1: flexcan1grp {
366 fsl,pins = <
Tim Harvey73e005c2014-09-08 23:07:29 -0700367 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
368 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
Tim Harveyb5f37b72014-09-08 23:07:30 -0700369 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
370 >;
371 };
372
373 pinctrl_gpio_leds: gpioledsgrp {
374 fsl,pins = <
375 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
376 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
377 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
Tim Harveye3946fe2014-02-07 15:24:56 +0800378 >;
379 };
380
381 pinctrl_gpmi_nand: gpminandgrp {
382 fsl,pins = <
383 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
384 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
385 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
386 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
387 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
388 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
389 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
390 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
391 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
392 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
393 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
394 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
395 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
396 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
397 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
398 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
399 >;
400 };
401
402 pinctrl_i2c1: i2c1grp {
403 fsl,pins = <
404 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
405 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
406 >;
407 };
408
409 pinctrl_i2c2: i2c2grp {
410 fsl,pins = <
411 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
412 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
413 >;
414 };
415
416 pinctrl_i2c3: i2c3grp {
417 fsl,pins = <
418 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
419 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
420 >;
421 };
422
Tim Harveyb5f37b72014-09-08 23:07:30 -0700423 pinctrl_pcie: pciegrp {
424 fsl,pins = <
425 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
426 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
427 >;
428 };
429
430 pinctrl_pps: ppsgrp {
431 fsl,pins = <
432 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
433 >;
434 };
435
Tim Harveyb3253242014-04-30 23:32:30 -0700436 pinctrl_pwm4: pwm4grp {
437 fsl,pins = <
438 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
439 >;
440 };
441
Tim Harveye3946fe2014-02-07 15:24:56 +0800442 pinctrl_uart1: uart1grp {
443 fsl,pins = <
444 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
445 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
446 >;
447 };
448
449 pinctrl_uart2: uart2grp {
450 fsl,pins = <
451 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
452 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
453 >;
454 };
455
456 pinctrl_uart5: uart5grp {
457 fsl,pins = <
458 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
459 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
460 >;
461 };
462
463 pinctrl_usbotg: usbotggrp {
464 fsl,pins = <
465 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
Tim Harveyb5f37b72014-09-08 23:07:30 -0700466 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
467 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
Tim Harveye3946fe2014-02-07 15:24:56 +0800468 >;
469 };
470
471 pinctrl_usdhc3: usdhc3grp {
472 fsl,pins = <
473 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
474 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
475 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
476 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
477 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
478 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
Tim Harveyb5f37b72014-09-08 23:07:30 -0700479 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
Tim Harveye3946fe2014-02-07 15:24:56 +0800480 >;
481 };
482 };
483};