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gerrit-public.fairphone.software / kernel / msm-4.19 / 8e8ec596e6c0144e2dd500a57ee23dde9684df46 / . / arch / powerpc / boot / dts / p4080ds.dts
blob: c78e8015501979d64cbb24d91313432def100ee4 [file] [log] [blame]
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]1/*
2 * P4080DS Device Tree Source
3 *
Kim Phillips8e8ec592011-03-13 16:54:26 +0800[diff] [blame^]4 * Copyright 2009-2011 Freescale Semiconductor Inc.
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15 model = "fsl,P4080DS";
16 compatible = "fsl,P4080DS";
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 ccsr = &soc;
22
23 serial0 = &serial0;
24 serial1 = &serial1;
25 serial2 = &serial2;
26 serial3 = &serial3;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 pci2 = &pci2;
30 usb0 = &usb0;
31 usb1 = &usb1;
32 dma0 = &dma0;
33 dma1 = &dma1;
34 sdhc = &sdhc;
35
Kim Phillips8e8ec592011-03-13 16:54:26 +0800[diff] [blame^]36 crypto = &crypto;
37 sec_jr0 = &sec_jr0;
38 sec_jr1 = &sec_jr1;
39 sec_jr2 = &sec_jr2;
40 sec_jr3 = &sec_jr3;
41 rtic_a = &rtic_a;
42 rtic_b = &rtic_b;
43 rtic_c = &rtic_c;
44 rtic_d = &rtic_d;
45 sec_mon = &sec_mon;
46
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]47 rio0 = &rapidio0;
48 };
49
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 cpu0: PowerPC,4080@0 {
55 device_type = "cpu";
56 reg = <0>;
57 next-level-cache = <&L2_0>;
58 L2_0: l2-cache {
59 };
60 };
61 cpu1: PowerPC,4080@1 {
62 device_type = "cpu";
63 reg = <1>;
64 next-level-cache = <&L2_1>;
65 L2_1: l2-cache {
66 };
67 };
68 cpu2: PowerPC,4080@2 {
69 device_type = "cpu";
70 reg = <2>;
71 next-level-cache = <&L2_2>;
72 L2_2: l2-cache {
73 };
74 };
75 cpu3: PowerPC,4080@3 {
76 device_type = "cpu";
77 reg = <3>;
78 next-level-cache = <&L2_3>;
79 L2_3: l2-cache {
80 };
81 };
82 cpu4: PowerPC,4080@4 {
83 device_type = "cpu";
84 reg = <4>;
85 next-level-cache = <&L2_4>;
86 L2_4: l2-cache {
87 };
88 };
89 cpu5: PowerPC,4080@5 {
90 device_type = "cpu";
91 reg = <5>;
92 next-level-cache = <&L2_5>;
93 L2_5: l2-cache {
94 };
95 };
96 cpu6: PowerPC,4080@6 {
97 device_type = "cpu";
98 reg = <6>;
99 next-level-cache = <&L2_6>;
100 L2_6: l2-cache {
101 };
102 };
103 cpu7: PowerPC,4080@7 {
104 device_type = "cpu";
105 reg = <7>;
106 next-level-cache = <&L2_7>;
107 L2_7: l2-cache {
108 };
109 };
110 };
111
112 memory {
113 device_type = "memory";
114 };
115
116 soc: soc@ffe000000 {
117 #address-cells = <1>;
118 #size-cells = <1>;
119 device_type = "soc";
120 compatible = "simple-bus";
121 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
122 reg = <0xf 0xfe000000 0 0x00001000>;
123
124 corenet-law@0 {
125 compatible = "fsl,corenet-law";
126 reg = <0x0 0x1000>;
127 fsl,num-laws = <32>;
128 };
129
130 memory-controller@8000 {
131 compatible = "fsl,p4080-memory-controller";
132 reg = <0x8000 0x1000>;
133 interrupt-parent = <&mpic>;
134 interrupts = <0x12 2>;
135 };
136
137 memory-controller@9000 {
138 compatible = "fsl,p4080-memory-controller";
139 reg = <0x9000 0x1000>;
140 interrupt-parent = <&mpic>;
141 interrupts = <0x12 2>;
142 };
143
144 corenet-cf@18000 {
145 compatible = "fsl,corenet-cf";
146 reg = <0x18000 0x1000>;
147 fsl,ccf-num-csdids = <32>;
148 fsl,ccf-num-snoopids = <32>;
149 };
150
151 iommu@20000 {
152 compatible = "fsl,p4080-pamu";
153 reg = <0x20000 0x10000>;
154 interrupts = <24 2>;
155 interrupt-parent = <&mpic>;
156 };
157
158 mpic: pic@40000 {
159 interrupt-controller;
160 #address-cells = <0>;
161 #interrupt-cells = <2>;
162 reg = <0x40000 0x40000>;
163 compatible = "chrp,open-pic";
164 device_type = "open-pic";
165 };
166
167 dma0: dma@100300 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
171 reg = <0x100300 0x4>;
172 ranges = <0x0 0x100100 0x200>;
173 cell-index = <0>;
174 dma-channel@0 {
175 compatible = "fsl,p4080-dma-channel",
176 "fsl,eloplus-dma-channel";
177 reg = <0x0 0x80>;
178 cell-index = <0>;
179 interrupt-parent = <&mpic>;
180 interrupts = <28 2>;
181 };
182 dma-channel@80 {
183 compatible = "fsl,p4080-dma-channel",
184 "fsl,eloplus-dma-channel";
185 reg = <0x80 0x80>;
186 cell-index = <1>;
187 interrupt-parent = <&mpic>;
188 interrupts = <29 2>;
189 };
190 dma-channel@100 {
191 compatible = "fsl,p4080-dma-channel",
192 "fsl,eloplus-dma-channel";
193 reg = <0x100 0x80>;
194 cell-index = <2>;
195 interrupt-parent = <&mpic>;
196 interrupts = <30 2>;
197 };
198 dma-channel@180 {
199 compatible = "fsl,p4080-dma-channel",
200 "fsl,eloplus-dma-channel";
201 reg = <0x180 0x80>;
202 cell-index = <3>;
203 interrupt-parent = <&mpic>;
204 interrupts = <31 2>;
205 };
206 };
207
208 dma1: dma@101300 {
209 #address-cells = <1>;
210 #size-cells = <1>;
211 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
212 reg = <0x101300 0x4>;
213 ranges = <0x0 0x101100 0x200>;
214 cell-index = <1>;
215 dma-channel@0 {
216 compatible = "fsl,p4080-dma-channel",
217 "fsl,eloplus-dma-channel";
218 reg = <0x0 0x80>;
219 cell-index = <0>;
220 interrupt-parent = <&mpic>;
221 interrupts = <32 2>;
222 };
223 dma-channel@80 {
224 compatible = "fsl,p4080-dma-channel",
225 "fsl,eloplus-dma-channel";
226 reg = <0x80 0x80>;
227 cell-index = <1>;
228 interrupt-parent = <&mpic>;
229 interrupts = <33 2>;
230 };
231 dma-channel@100 {
232 compatible = "fsl,p4080-dma-channel",
233 "fsl,eloplus-dma-channel";
234 reg = <0x100 0x80>;
235 cell-index = <2>;
236 interrupt-parent = <&mpic>;
237 interrupts = <34 2>;
238 };
239 dma-channel@180 {
240 compatible = "fsl,p4080-dma-channel",
241 "fsl,eloplus-dma-channel";
242 reg = <0x180 0x80>;
243 cell-index = <3>;
244 interrupt-parent = <&mpic>;
245 interrupts = <35 2>;
246 };
247 };
248
249 spi@110000 {
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]250 #address-cells = <1>;
251 #size-cells = <0>;
Mingkai Huf3016fa2010-10-12 18:18:33 +0800[diff] [blame]252 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]253 reg = <0x110000 0x1000>;
254 interrupts = <53 0x2>;
255 interrupt-parent = <&mpic>;
Mingkai Huf3016fa2010-10-12 18:18:33 +0800[diff] [blame]256 fsl,espi-num-chipselects = <4>;
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]257
Mingkai Huf3016fa2010-10-12 18:18:33 +0800[diff] [blame]258 flash@0 {
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]259 #address-cells = <1>;
260 #size-cells = <1>;
Mingkai Huf3016fa2010-10-12 18:18:33 +0800[diff] [blame]261 compatible = "spansion,s25sl12801";
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]262 reg = <0>;
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]263 spi-max-frequency = <40000000>; /* input clock */
264 partition@u-boot {
265 label = "u-boot";
266 reg = <0x00000000 0x00100000>;
267 read-only;
268 };
269 partition@kernel {
270 label = "kernel";
271 reg = <0x00100000 0x00500000>;
272 read-only;
273 };
274 partition@dtb {
275 label = "dtb";
276 reg = <0x00600000 0x00100000>;
277 read-only;
278 };
279 partition@fs {
280 label = "file system";
281 reg = <0x00700000 0x00900000>;
282 };
283 };
284 };
285
286 sdhc: sdhc@114000 {
287 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
288 reg = <0x114000 0x1000>;
289 interrupts = <48 2>;
290 interrupt-parent = <&mpic>;
Roy Zang447bd472010-08-10 18:02:01 -0700[diff] [blame]291 voltage-ranges = <3300 3300>;
Roy Zang05e57ee2010-08-10 18:02:00 -0700[diff] [blame]292 sdhci,auto-cmd12;
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]293 };
294
295 i2c@118000 {
296 #address-cells = <1>;
297 #size-cells = <0>;
298 cell-index = <0>;
299 compatible = "fsl-i2c";
300 reg = <0x118000 0x100>;
301 interrupts = <38 2>;
302 interrupt-parent = <&mpic>;
303 dfsrr;
304 };
305
306 i2c@118100 {
307 #address-cells = <1>;
308 #size-cells = <0>;
309 cell-index = <1>;
310 compatible = "fsl-i2c";
311 reg = <0x118100 0x100>;
312 interrupts = <38 2>;
313 interrupt-parent = <&mpic>;
314 dfsrr;
315 eeprom@51 {
316 compatible = "at24,24c256";
317 reg = <0x51>;
318 };
319 eeprom@52 {
320 compatible = "at24,24c256";
321 reg = <0x52>;
322 };
323 rtc@68 {
324 compatible = "dallas,ds3232";
325 reg = <0x68>;
326 interrupts = <0 0x1>;
327 interrupt-parent = <&mpic>;
328 };
329 };
330
331 i2c@119000 {
332 #address-cells = <1>;
333 #size-cells = <0>;
334 cell-index = <2>;
335 compatible = "fsl-i2c";
336 reg = <0x119000 0x100>;
337 interrupts = <39 2>;
338 interrupt-parent = <&mpic>;
339 dfsrr;
340 };
341
342 i2c@119100 {
343 #address-cells = <1>;
344 #size-cells = <0>;
345 cell-index = <3>;
346 compatible = "fsl-i2c";
347 reg = <0x119100 0x100>;
348 interrupts = <39 2>;
349 interrupt-parent = <&mpic>;
350 dfsrr;
351 };
352
353 serial0: serial@11c500 {
354 cell-index = <0>;
355 device_type = "serial";
356 compatible = "ns16550";
357 reg = <0x11c500 0x100>;
358 clock-frequency = <0>;
359 interrupts = <36 2>;
360 interrupt-parent = <&mpic>;
361 };
362
363 serial1: serial@11c600 {
364 cell-index = <1>;
365 device_type = "serial";
366 compatible = "ns16550";
367 reg = <0x11c600 0x100>;
368 clock-frequency = <0>;
369 interrupts = <36 2>;
370 interrupt-parent = <&mpic>;
371 };
372
373 serial2: serial@11d500 {
374 cell-index = <2>;
375 device_type = "serial";
376 compatible = "ns16550";
377 reg = <0x11d500 0x100>;
378 clock-frequency = <0>;
379 interrupts = <37 2>;
380 interrupt-parent = <&mpic>;
381 };
382
383 serial3: serial@11d600 {
384 cell-index = <3>;
385 device_type = "serial";
386 compatible = "ns16550";
387 reg = <0x11d600 0x100>;
388 clock-frequency = <0>;
389 interrupts = <37 2>;
390 interrupt-parent = <&mpic>;
391 };
392
393 gpio0: gpio@130000 {
394 compatible = "fsl,p4080-gpio";
395 reg = <0x130000 0x1000>;
396 interrupts = <55 2>;
397 interrupt-parent = <&mpic>;
398 #gpio-cells = <2>;
399 gpio-controller;
400 };
401
402 usb0: usb@210000 {
403 compatible = "fsl,p4080-usb2-mph",
404 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
405 reg = <0x210000 0x1000>;
406 #address-cells = <1>;
407 #size-cells = <0>;
408 interrupt-parent = <&mpic>;
409 interrupts = <44 0x2>;
410 phy_type = "ulpi";
411 };
412
413 usb1: usb@211000 {
414 compatible = "fsl,p4080-usb2-dr",
415 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
416 reg = <0x211000 0x1000>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 interrupt-parent = <&mpic>;
420 interrupts = <45 0x2>;
421 dr_mode = "host";
422 phy_type = "ulpi";
423 };
Kim Phillips8e8ec592011-03-13 16:54:26 +0800[diff] [blame^]424
425 crypto: crypto@300000 {
426 compatible = "fsl,p4080-sec4.0", "fsl,sec4.0";
427 #address-cells = <1>;
428 #size-cells = <1>;
429 reg = <0x300000 0x10000>;
430 ranges = <0 0x300000 0x10000>;
431 interrupt-parent = <&mpic>;
432 interrupts = <92 2>;
433
434 sec_jr0: jr@1000 {
435 compatible = "fsl,p4080-sec4.0-job-ring",
436 "fsl,sec4.0-job-ring";
437 reg = <0x1000 0x1000>;
438 interrupt-parent = <&mpic>;
439 interrupts = <88 2>;
440 };
441
442 sec_jr1: jr@2000 {
443 compatible = "fsl,p4080-sec4.0-job-ring",
444 "fsl,sec4.0-job-ring";
445 reg = <0x2000 0x1000>;
446 interrupt-parent = <&mpic>;
447 interrupts = <89 2>;
448 };
449
450 sec_jr2: jr@3000 {
451 compatible = "fsl,p4080-sec4.0-job-ring",
452 "fsl,sec4.0-job-ring";
453 reg = <0x3000 0x1000>;
454 interrupt-parent = <&mpic>;
455 interrupts = <90 2>;
456 };
457
458 sec_jr3: jr@4000 {
459 compatible = "fsl,p4080-sec4.0-job-ring",
460 "fsl,sec4.0-job-ring";
461 reg = <0x4000 0x1000>;
462 interrupt-parent = <&mpic>;
463 interrupts = <91 2>;
464 };
465
466 rtic@6000 {
467 compatible = "fsl,p4080-sec4.0-rtic",
468 "fsl,sec4.0-rtic";
469 #address-cells = <1>;
470 #size-cells = <1>;
471 reg = <0x6000 0x100>;
472 ranges = <0x0 0x6100 0xe00>;
473
474 rtic_a: rtic-a@0 {
475 compatible = "fsl,p4080-sec4.0-rtic-memory",
476 "fsl,sec4.0-rtic-memory";
477 reg = <0x00 0x20 0x100 0x80>;
478 };
479
480 rtic_b: rtic-b@20 {
481 compatible = "fsl,p4080-sec4.0-rtic-memory",
482 "fsl,sec4.0-rtic-memory";
483 reg = <0x20 0x20 0x200 0x80>;
484 };
485
486 rtic_c: rtic-c@40 {
487 compatible = "fsl,p4080-sec4.0-rtic-memory",
488 "fsl,sec4.0-rtic-memory";
489 reg = <0x40 0x20 0x300 0x80>;
490 };
491
492 rtic_d: rtic-d@60 {
493 compatible = "fsl,p4080-sec4.0-rtic-memory",
494 "fsl,sec4.0-rtic-memory";
495 reg = <0x60 0x20 0x500 0x80>;
496 };
497 };
498 };
499
500 sec_mon: sec_mon@314000 {
501 compatible = "fsl,p4080-sec4.0-mon", "fsl,sec4.0-mon";
502 reg = <0x314000 0x1000>;
503 interrupt-parent = <&mpic>;
504 interrupts = <93 2>;
505 };
Kumar Galaab2f4892009-10-22 16:35:07 -0500[diff] [blame]506 };
507
508 rapidio0: rapidio@ffe0c0000 {
509 #address-cells = <2>;
510 #size-cells = <2>;
511 compatible = "fsl,rapidio-delta";
512 reg = <0xf 0xfe0c0000 0 0x20000>;
513 ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
514 interrupt-parent = <&mpic>;
515 /* err_irq bell_outb_irq bell_inb_irq
516 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
517 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
518 };
519
520 localbus@ffe124000 {
521 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
522 reg = <0xf 0xfe124000 0 0x1000>;
523 interrupts = <25 2>;
524 #address-cells = <2>;
525 #size-cells = <1>;
526
527 ranges = <0 0 0xf 0xe8000000 0x08000000>;
528
529 flash@0,0 {
530 compatible = "cfi-flash";
531 reg = <0 0 0x08000000>;
532 bank-width = <2>;
533 device-width = <2>;
534 };
535 };
536
537 pci0: pcie@ffe200000 {
538 compatible = "fsl,p4080-pcie";
539 device_type = "pci";
540 #interrupt-cells = <1>;
541 #size-cells = <2>;
542 #address-cells = <3>;
543 reg = <0xf 0xfe200000 0 0x1000>;
544 bus-range = <0x0 0xff>;
545 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
546 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
547 clock-frequency = <0x1fca055>;
548 interrupt-parent = <&mpic>;
549 interrupts = <16 2>;
550
551 interrupt-map-mask = <0xf800 0 0 7>;
552 interrupt-map = <
553 /* IDSEL 0x0 */
554 0000 0 0 1 &mpic 40 1
555 0000 0 0 2 &mpic 1 1
556 0000 0 0 3 &mpic 2 1
557 0000 0 0 4 &mpic 3 1
558 >;
559 pcie@0 {
560 reg = <0 0 0 0 0>;
561 #size-cells = <2>;
562 #address-cells = <3>;
563 device_type = "pci";
564 ranges = <0x02000000 0 0xe0000000
565 0x02000000 0 0xe0000000
566 0 0x20000000
567
568 0x01000000 0 0x00000000
569 0x01000000 0 0x00000000
570 0 0x00010000>;
571 };
572 };
573
574 pci1: pcie@ffe201000 {
575 compatible = "fsl,p4080-pcie";
576 device_type = "pci";
577 #interrupt-cells = <1>;
578 #size-cells = <2>;
579 #address-cells = <3>;
580 reg = <0xf 0xfe201000 0 0x1000>;
581 bus-range = <0 0xff>;
582 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
583 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
584 clock-frequency = <0x1fca055>;
585 interrupt-parent = <&mpic>;
586 interrupts = <16 2>;
587 interrupt-map-mask = <0xf800 0 0 7>;
588 interrupt-map = <
589 /* IDSEL 0x0 */
590 0000 0 0 1 &mpic 41 1
591 0000 0 0 2 &mpic 5 1
592 0000 0 0 3 &mpic 6 1
593 0000 0 0 4 &mpic 7 1
594 >;
595 pcie@0 {
596 reg = <0 0 0 0 0>;
597 #size-cells = <2>;
598 #address-cells = <3>;
599 device_type = "pci";
600 ranges = <0x02000000 0 0xe0000000
601 0x02000000 0 0xe0000000
602 0 0x20000000
603
604 0x01000000 0 0x00000000
605 0x01000000 0 0x00000000
606 0 0x00010000>;
607 };
608 };
609
610 pci2: pcie@ffe202000 {
611 compatible = "fsl,p4080-pcie";
612 device_type = "pci";
613 #interrupt-cells = <1>;
614 #size-cells = <2>;
615 #address-cells = <3>;
616 reg = <0xf 0xfe202000 0 0x1000>;
617 bus-range = <0x0 0xff>;
618 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
619 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
620 clock-frequency = <0x1fca055>;
621 interrupt-parent = <&mpic>;
622 interrupts = <16 2>;
623 interrupt-map-mask = <0xf800 0 0 7>;
624 interrupt-map = <
625 /* IDSEL 0x0 */
626 0000 0 0 1 &mpic 42 1
627 0000 0 0 2 &mpic 9 1
628 0000 0 0 3 &mpic 10 1
629 0000 0 0 4 &mpic 11 1
630 >;
631 pcie@0 {
632 reg = <0 0 0 0 0>;
633 #size-cells = <2>;
634 #address-cells = <3>;
635 device_type = "pci";
636 ranges = <0x02000000 0 0xe0000000
637 0x02000000 0 0xe0000000
638 0 0x20000000
639
640 0x01000000 0 0x00000000
641 0x01000000 0 0x00000000
642 0 0x00010000>;
643 };
644 };
645
646};