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gerrit-public.fairphone.software / kernel / msm-4.19 / 8fe627ec5b7c47b1654dff50536d9709863295a3 / . / include / asm-avr32 / arch-at32ap / smc.h
blob: c98eea44a70a08eba09b2d24b7f522dd6ea5b255 [file] [log] [blame]
Haavard Skinnemoenbc157b72006-09-25 23:32:16 -0700[diff] [blame]1/*
2 * Static Memory Controller for AT32 chips
3 *
4 * Copyright (C) 2006 Atmel Corporation
5 *
6 * Inspired by the OMAP2 General-Purpose Memory Controller interface
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#ifndef __ARCH_AT32AP_SMC_H
13#define __ARCH_AT32AP_SMC_H
14
15/*
16 * All timing parameters are in nanoseconds.
17 */
Kristoffer Nyborg Gregertsenaf8184712007-08-17 16:59:57 +0200[diff] [blame]18struct smc_timing {
Haavard Skinnemoenbc157b72006-09-25 23:32:16 -0700[diff] [blame]19 /* Delay from address valid to assertion of given strobe */
Kristoffer Nyborg Gregertsenaf8184712007-08-17 16:59:57 +0200[diff] [blame]20 int ncs_read_setup;
21 int nrd_setup;
22 int ncs_write_setup;
23 int nwe_setup;
Haavard Skinnemoenbc157b72006-09-25 23:32:16 -0700[diff] [blame]24
25 /* Pulse length of given strobe */
Kristoffer Nyborg Gregertsenaf8184712007-08-17 16:59:57 +0200[diff] [blame]26 int ncs_read_pulse;
27 int nrd_pulse;
28 int ncs_write_pulse;
29 int nwe_pulse;
Haavard Skinnemoenbc157b72006-09-25 23:32:16 -0700[diff] [blame]30
31 /* Total cycle length of given operation */
Kristoffer Nyborg Gregertsenaf8184712007-08-17 16:59:57 +0200[diff] [blame]32 int read_cycle;
33 int write_cycle;
34
35 /* Minimal recovery times, will extend cycle if needed */
36 int ncs_read_recover;
37 int nrd_recover;
38 int ncs_write_recover;
39 int nwe_recover;
40};
41
42/*
43 * All timing parameters are in clock cycles.
44 */
45struct smc_config {
46
47 /* Delay from address valid to assertion of given strobe */
48 u8 ncs_read_setup;
49 u8 nrd_setup;
50 u8 ncs_write_setup;
51 u8 nwe_setup;
52
53 /* Pulse length of given strobe */
54 u8 ncs_read_pulse;
55 u8 nrd_pulse;
56 u8 ncs_write_pulse;
57 u8 nwe_pulse;
58
59 /* Total cycle length of given operation */
60 u8 read_cycle;
61 u8 write_cycle;
Haavard Skinnemoenbc157b72006-09-25 23:32:16 -0700[diff] [blame]62
63 /* Bus width in bytes */
64 u8 bus_width;
65
66 /*
67 * 0: Data is sampled on rising edge of NCS
68 * 1: Data is sampled on rising edge of NRD
69 */
70 unsigned int nrd_controlled:1;
71
72 /*
73 * 0: Data is driven on falling edge of NCS
74 * 1: Data is driven on falling edge of NWR
75 */
76 unsigned int nwe_controlled:1;
77
78 /*
Hans-Christian Egtvedt068d9f62007-01-31 18:01:45 +0100[diff] [blame]79 * 0: NWAIT is disabled
80 * 1: Reserved
81 * 2: NWAIT is frozen mode
82 * 3: NWAIT in ready mode
83 */
84 unsigned int nwait_mode:2;
85
86 /*
Haavard Skinnemoenbc157b72006-09-25 23:32:16 -0700[diff] [blame]87 * 0: Byte select access type
88 * 1: Byte write access type
89 */
90 unsigned int byte_write:1;
Hans-Christian Egtvedt068d9f62007-01-31 18:01:45 +0100[diff] [blame]91
92 /*
93 * Number of clock cycles before data is released after
94 * the rising edge of the read controlling signal
95 *
96 * Total cycles from SMC is tdf_cycles + 1
97 */
98 unsigned int tdf_cycles:4;
99
100 /*
101 * 0: TDF optimization disabled
102 * 1: TDF optimization enabled
103 */
104 unsigned int tdf_mode:1;
Haavard Skinnemoenbc157b72006-09-25 23:32:16 -0700[diff] [blame]105};
106
Kristoffer Nyborg Gregertsenaf8184712007-08-17 16:59:57 +0200[diff] [blame]107extern void smc_set_timing(struct smc_config *config,
108 const struct smc_timing *timing);
109
Haavard Skinnemoenbc157b72006-09-25 23:32:16 -0700[diff] [blame]110extern int smc_set_configuration(int cs, const struct smc_config *config);
111extern struct smc_config *smc_get_configuration(int cs);
112
113#endif /* __ARCH_AT32AP_SMC_H */