blob: 51998a4b11af000aae3eca1389bba07743d2c045 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
David Howells760285e2012-10-02 18:01:07 +010028#include <drm/drmP.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020029#include "radeon.h"
David Howells760285e2012-10-02 18:01:07 +010030#include <drm/radeon_drm.h>
Marek Olšák6759a0a2012-08-09 16:34:17 +020031#include "radeon_asic.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020032
Dave Airlie6a9ee8a2010-02-01 15:38:10 +100033#include <linux/vga_switcheroo.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090034#include <linux/slab.h>
Dave Airlie10ebc0b2012-09-17 14:40:31 +100035#include <linux/pm_runtime.h>
Alex Deucher78488652014-03-11 15:02:30 -040036
Oded Gabbaye28740e2014-07-15 13:53:32 +030037#include "radeon_kfd.h"
38
Alex Deucher78488652014-03-11 15:02:30 -040039#if defined(CONFIG_VGA_SWITCHEROO)
Alex Deucher90c4cde2014-04-10 22:29:01 -040040bool radeon_has_atpx(void);
Alex Deucher78488652014-03-11 15:02:30 -040041#else
Alex Deucher90c4cde2014-04-10 22:29:01 -040042static inline bool radeon_has_atpx(void) { return false; }
Alex Deucher78488652014-03-11 15:02:30 -040043#endif
44
Alex Deucherf482a142012-07-17 14:02:34 -040045/**
46 * radeon_driver_unload_kms - Main unload function for KMS.
47 *
48 * @dev: drm dev pointer
49 *
50 * This is the main unload function for KMS (all asics).
51 * It calls radeon_modeset_fini() to tear down the
52 * displays, and radeon_device_fini() to tear down
53 * the rest of the device (CP, writeback, etc.).
54 * Returns 0 on success.
55 */
Jerome Glissecf0fe452009-12-09 18:21:55 +010056int radeon_driver_unload_kms(struct drm_device *dev)
57{
58 struct radeon_device *rdev = dev->dev_private;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020059
Jerome Glissecf0fe452009-12-09 18:21:55 +010060 if (rdev == NULL)
61 return 0;
Dave Airlie10ebc0b2012-09-17 14:40:31 +100062
Alex Deucher0cd9cb72013-04-12 19:15:52 -040063 if (rdev->rmmio == NULL)
64 goto done_free;
Dave Airlie10ebc0b2012-09-17 14:40:31 +100065
Lukas Wunner19de6592016-06-08 18:47:27 +020066 if (radeon_is_px(dev)) {
67 pm_runtime_get_sync(dev->dev);
68 }
Dave Airlie10ebc0b2012-09-17 14:40:31 +100069
Oded Gabbaye28740e2014-07-15 13:53:32 +030070 radeon_kfd_device_fini(rdev);
71
Alex Deucherc4917072012-07-31 17:14:35 -040072 radeon_acpi_fini(rdev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +100073
Jerome Glissecf0fe452009-12-09 18:21:55 +010074 radeon_modeset_fini(rdev);
75 radeon_device_fini(rdev);
Alex Deucher0cd9cb72013-04-12 19:15:52 -040076
77done_free:
Jerome Glissecf0fe452009-12-09 18:21:55 +010078 kfree(rdev);
79 dev->dev_private = NULL;
80 return 0;
81}
82
Alex Deucherf482a142012-07-17 14:02:34 -040083/**
84 * radeon_driver_load_kms - Main load function for KMS.
85 *
86 * @dev: drm dev pointer
87 * @flags: device flags
88 *
89 * This is the main load function for KMS (all asics).
90 * It calls radeon_device_init() to set up the non-display
91 * parts of the chip (asic init, CP, writeback, etc.), and
92 * radeon_modeset_init() to set up the display parts
93 * (crtcs, encoders, hotplug detect, etc.).
94 * Returns 0 on success, error on failure.
95 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +020096int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
97{
98 struct radeon_device *rdev;
Alberto Miloned7a29522010-07-06 11:40:24 -040099 int r, acpi_status;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200100
101 rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
102 if (rdev == NULL) {
103 return -ENOMEM;
104 }
105 dev->dev_private = (void *)rdev;
106
107 /* update BUS flag */
Dave Airlie8410ea32010-12-15 03:16:38 +1000108 if (drm_pci_device_is_agp(dev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200109 flags |= RADEON_IS_AGP;
Jon Mason58b65422011-06-27 16:07:50 +0000110 } else if (pci_is_pcie(dev->pdev)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200111 flags |= RADEON_IS_PCIE;
112 } else {
113 flags |= RADEON_IS_PCI;
114 }
115
Alex Deucher73acacc2014-04-15 12:44:35 -0400116 if ((radeon_runtime_pm != 0) &&
117 radeon_has_atpx() &&
118 ((flags & RADEON_IS_IGP) == 0))
Alex Deucher90c4cde2014-04-10 22:29:01 -0400119 flags |= RADEON_IS_PX;
120
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200121 /* radeon_device_init should report only fatal error
122 * like memory allocation failure or iomapping failure,
123 * or memory manager initialization failure, it must
124 * properly initialize the GPU MC controller and permit
125 * VRAM allocation
126 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200127 r = radeon_device_init(rdev, dev, dev->pdev, flags);
128 if (r) {
Jerome Glissecf0fe452009-12-09 18:21:55 +0100129 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
130 goto out;
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200131 }
Alberto Miloned7a29522010-07-06 11:40:24 -0400132
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +0200133 /* Again modeset_init should fail only on fatal error
134 * otherwise it should provide enough functionalities
135 * for shadowfb to run
136 */
137 r = radeon_modeset_init(rdev);
Jerome Glissecf0fe452009-12-09 18:21:55 +0100138 if (r)
139 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
Luca Tettamantifda4b252012-07-30 21:20:35 +0200140
141 /* Call ACPI methods: require modeset init
142 * but failure is not fatal
143 */
144 if (!r) {
145 acpi_status = radeon_acpi_init(rdev);
146 if (acpi_status)
147 dev_dbg(&dev->pdev->dev,
148 "Error during ACPI methods call\n");
149 }
150
Oded Gabbaye28740e2014-07-15 13:53:32 +0300151 radeon_kfd_device_probe(rdev);
152 radeon_kfd_device_init(rdev);
153
Alex Deucher90c4cde2014-04-10 22:29:01 -0400154 if (radeon_is_px(dev)) {
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000155 pm_runtime_use_autosuspend(dev->dev);
156 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
157 pm_runtime_set_active(dev->dev);
158 pm_runtime_allow(dev->dev);
159 pm_runtime_mark_last_busy(dev->dev);
160 pm_runtime_put_autosuspend(dev->dev);
161 }
162
Jerome Glissecf0fe452009-12-09 18:21:55 +0100163out:
164 if (r)
165 radeon_driver_unload_kms(dev);
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000166
167
Jerome Glissecf0fe452009-12-09 18:21:55 +0100168 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200169}
170
Alex Deucherf482a142012-07-17 14:02:34 -0400171/**
172 * radeon_set_filp_rights - Set filp right.
173 *
174 * @dev: drm dev pointer
175 * @owner: drm file
176 * @applier: drm file
177 * @value: value
178 *
179 * Sets the filp rights for the device (all asics).
180 */
Marek Olšák9eba4a92011-01-05 05:46:48 +0100181static void radeon_set_filp_rights(struct drm_device *dev,
182 struct drm_file **owner,
183 struct drm_file *applier,
184 uint32_t *value)
185{
Daniel Vetter45c1da52015-10-15 09:36:34 +0200186 struct radeon_device *rdev = dev->dev_private;
187
188 mutex_lock(&rdev->gem.mutex);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100189 if (*value == 1) {
190 /* wants rights */
191 if (!*owner)
192 *owner = applier;
193 } else if (*value == 0) {
194 /* revokes rights */
195 if (*owner == applier)
196 *owner = NULL;
197 }
198 *value = *owner == applier ? 1 : 0;
Daniel Vetter45c1da52015-10-15 09:36:34 +0200199 mutex_unlock(&rdev->gem.mutex);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100200}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200201
202/*
Marek Olšák9eba4a92011-01-05 05:46:48 +0100203 * Userspace get information ioctl
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200204 */
Alex Deucherf482a142012-07-17 14:02:34 -0400205/**
206 * radeon_info_ioctl - answer a device specific request.
207 *
208 * @rdev: radeon device pointer
209 * @data: request object
210 * @filp: drm filp
211 *
212 * This function is used to pass device specific parameters to the userspace
213 * drivers. Examples include: pci device id, pipeline parms, tiling params,
214 * etc. (all asics).
215 * Returns 0 on success, -EINVAL on failure.
216 */
Rashika Kheria55203452014-01-06 20:53:07 +0530217static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200218{
219 struct radeon_device *rdev = dev->dev_private;
Marek Olšák6759a0a2012-08-09 16:34:17 +0200220 struct drm_radeon_info *info = data;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200221 struct radeon_mode_info *minfo = &rdev->mode_info;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400222 uint32_t *value, value_tmp, *value_ptr, value_size;
223 uint64_t value64;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200224 struct drm_crtc *crtc;
225 int i, found;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200226
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200227 value_ptr = (uint32_t *)((unsigned long)info->value);
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400228 value = &value_tmp;
229 value_size = sizeof(uint32_t);
Dr. David Alan Gilbertd8ab3552010-08-02 09:43:52 +1000230
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200231 switch (info->request) {
232 case RADEON_INFO_DEVICE_ID:
Ville Syrjäläffbab09b2013-10-04 14:53:40 +0300233 *value = dev->pdev->device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200234 break;
235 case RADEON_INFO_NUM_GB_PIPES:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400236 *value = rdev->num_gb_pipes;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200237 break;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400238 case RADEON_INFO_NUM_Z_PIPES:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400239 *value = rdev->num_z_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -0400240 break;
Jerome Glisse733289c2009-09-16 15:24:21 +0200241 case RADEON_INFO_ACCEL_WORKING:
Alex Deucher148a03b2010-06-03 19:00:03 -0400242 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
243 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400244 *value = false;
Alex Deucher148a03b2010-06-03 19:00:03 -0400245 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400246 *value = rdev->accel_working;
Jerome Glisse733289c2009-09-16 15:24:21 +0200247 break;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200248 case RADEON_INFO_CRTC_FROM_ID:
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100249 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400250 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
251 return -EFAULT;
252 }
Jerome Glissebc35afd2010-05-12 18:01:13 +0200253 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
254 crtc = (struct drm_crtc *)minfo->crtcs[i];
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400255 if (crtc && crtc->base.id == *value) {
Alex Deucher0baf2d82010-07-21 14:05:35 -0400256 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400257 *value = radeon_crtc->crtc_id;
Jerome Glissebc35afd2010-05-12 18:01:13 +0200258 found = 1;
259 break;
260 }
261 }
262 if (!found) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400263 DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
Jerome Glissebc35afd2010-05-12 18:01:13 +0200264 return -EINVAL;
265 }
266 break;
Alex Deucher148a03b2010-06-03 19:00:03 -0400267 case RADEON_INFO_ACCEL_WORKING2:
Alex Deucher3c64bd22014-08-01 20:05:30 +0200268 if (rdev->family == CHIP_HAWAII) {
Andreas Boll9eb401a2014-08-01 20:05:32 +0200269 if (rdev->accel_working) {
270 if (rdev->new_fw)
271 *value = 3;
272 else
273 *value = 2;
274 } else {
Alex Deucher3c64bd22014-08-01 20:05:30 +0200275 *value = 0;
Andreas Boll9eb401a2014-08-01 20:05:32 +0200276 }
Alex Deucher3c64bd22014-08-01 20:05:30 +0200277 } else {
278 *value = rdev->accel_working;
279 }
Alex Deucher148a03b2010-06-03 19:00:03 -0400280 break;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400281 case RADEON_INFO_TILING_CONFIG:
Alex Deucher64f759c2012-07-06 17:40:32 -0400282 if (rdev->family >= CHIP_BONAIRE)
283 *value = rdev->config.cik.tile_config;
284 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400285 *value = rdev->config.si.tile_config;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400286 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400287 *value = rdev->config.cayman.tile_config;
Alex Deucherfecf1d02011-03-02 20:07:29 -0500288 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400289 *value = rdev->config.evergreen.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400290 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400291 *value = rdev->config.rv770.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400292 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400293 *value = rdev->config.r600.tile_config;
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400294 else {
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000295 DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400296 return -EINVAL;
297 }
Alex Deucherb824b362010-08-12 08:25:47 -0400298 break;
Dave Airlieab9e1f52010-07-13 11:11:11 +1000299 case RADEON_INFO_WANT_HYPERZ:
Marek Olšák43861f72010-08-07 03:36:34 +0200300 /* The "value" here is both an input and output parameter.
301 * If the input value is 1, filp requests hyper-z access.
302 * If the input value is 0, filp revokes its hyper-z access.
303 *
304 * When returning, the value is 1 if filp owns hyper-z access,
305 * 0 otherwise. */
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100306 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400307 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
308 return -EFAULT;
309 }
310 if (*value >= 2) {
311 DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
Marek Olšák43861f72010-08-07 03:36:34 +0200312 return -EINVAL;
Dave Airlieab9e1f52010-07-13 11:11:11 +1000313 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400314 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100315 break;
316 case RADEON_INFO_WANT_CMASK:
317 /* The same logic as Hyper-Z. */
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100318 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400319 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
320 return -EFAULT;
321 }
322 if (*value >= 2) {
323 DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
Marek Olšák9eba4a92011-01-05 05:46:48 +0100324 return -EINVAL;
Marek Olšák43861f72010-08-07 03:36:34 +0200325 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400326 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
Alex Deuchere7aeeba2010-06-04 13:10:12 -0400327 break;
Alex Deucher58bbf012011-01-24 17:14:26 -0500328 case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
329 /* return clock value in KHz */
Alex Deucher454d2e22013-02-14 10:04:02 -0500330 if (rdev->asic->get_xclk)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400331 *value = radeon_get_xclk(rdev) * 10;
Alex Deucher454d2e22013-02-14 10:04:02 -0500332 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400333 *value = rdev->clock.spll.reference_freq * 10;
Alex Deucher58bbf012011-01-24 17:14:26 -0500334 break;
Dave Airlie486af182011-03-01 14:32:27 +1000335 case RADEON_INFO_NUM_BACKENDS:
Alex Deucher64f759c2012-07-06 17:40:32 -0400336 if (rdev->family >= CHIP_BONAIRE)
337 *value = rdev->config.cik.max_backends_per_se *
338 rdev->config.cik.max_shader_engines;
339 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400340 *value = rdev->config.si.max_backends_per_se *
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400341 rdev->config.si.max_shader_engines;
342 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400343 *value = rdev->config.cayman.max_backends_per_se *
Alex Deucherfecf1d02011-03-02 20:07:29 -0500344 rdev->config.cayman.max_shader_engines;
345 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400346 *value = rdev->config.evergreen.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000347 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400348 *value = rdev->config.rv770.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000349 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400350 *value = rdev->config.r600.max_backends;
Dave Airlie486af182011-03-01 14:32:27 +1000351 else {
352 return -EINVAL;
353 }
354 break;
Alex Deucher65659452011-04-26 13:27:43 -0400355 case RADEON_INFO_NUM_TILE_PIPES:
Alex Deucher64f759c2012-07-06 17:40:32 -0400356 if (rdev->family >= CHIP_BONAIRE)
357 *value = rdev->config.cik.max_tile_pipes;
358 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400359 *value = rdev->config.si.max_tile_pipes;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400360 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400361 *value = rdev->config.cayman.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400362 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400363 *value = rdev->config.evergreen.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400364 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400365 *value = rdev->config.rv770.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400366 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400367 *value = rdev->config.r600.max_tile_pipes;
Alex Deucher65659452011-04-26 13:27:43 -0400368 else {
369 return -EINVAL;
370 }
371 break;
Alex Deucher8aeb96f2011-05-03 19:28:02 -0400372 case RADEON_INFO_FUSION_GART_WORKING:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400373 *value = 1;
Alex Deucher8aeb96f2011-05-03 19:28:02 -0400374 break;
Alex Deuchere55b9422011-07-15 19:53:52 +0000375 case RADEON_INFO_BACKEND_MAP:
Alex Deucher64f759c2012-07-06 17:40:32 -0400376 if (rdev->family >= CHIP_BONAIRE)
Michel Dänzer1ddce272013-11-18 18:25:59 +0900377 *value = rdev->config.cik.backend_map;
Alex Deucher64f759c2012-07-06 17:40:32 -0400378 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400379 *value = rdev->config.si.backend_map;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400380 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400381 *value = rdev->config.cayman.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000382 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400383 *value = rdev->config.evergreen.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000384 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400385 *value = rdev->config.rv770.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000386 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400387 *value = rdev->config.r600.backend_map;
Alex Deuchere55b9422011-07-15 19:53:52 +0000388 else {
389 return -EINVAL;
390 }
391 break;
Jerome Glisse721604a2012-01-05 22:11:05 -0500392 case RADEON_INFO_VA_START:
393 /* this is where we report if vm is supported or not */
394 if (rdev->family < CHIP_CAYMAN)
395 return -EINVAL;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400396 *value = RADEON_VA_RESERVED_SIZE;
Jerome Glisse721604a2012-01-05 22:11:05 -0500397 break;
398 case RADEON_INFO_IB_VM_MAX_SIZE:
399 /* this is where we report if vm is supported or not */
400 if (rdev->family < CHIP_CAYMAN)
401 return -EINVAL;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400402 *value = RADEON_IB_VM_MAX_SIZE;
Jerome Glisse721604a2012-01-05 22:11:05 -0500403 break;
Tom Stellard609c1e12012-03-20 17:17:55 -0400404 case RADEON_INFO_MAX_PIPES:
Alex Deucher64f759c2012-07-06 17:40:32 -0400405 if (rdev->family >= CHIP_BONAIRE)
406 *value = rdev->config.cik.max_cu_per_sh;
407 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400408 *value = rdev->config.si.max_cu_per_sh;
Michel Dänzerc1b2f692012-03-20 17:18:26 -0400409 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400410 *value = rdev->config.cayman.max_pipes_per_simd;
Tom Stellard609c1e12012-03-20 17:17:55 -0400411 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400412 *value = rdev->config.evergreen.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400413 else if (rdev->family >= CHIP_RV770)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400414 *value = rdev->config.rv770.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400415 else if (rdev->family >= CHIP_R600)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400416 *value = rdev->config.r600.max_pipes;
Tom Stellard609c1e12012-03-20 17:17:55 -0400417 else {
418 return -EINVAL;
419 }
420 break;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400421 case RADEON_INFO_TIMESTAMP:
422 if (rdev->family < CHIP_R600) {
423 DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
424 return -EINVAL;
425 }
426 value = (uint32_t*)&value64;
427 value_size = sizeof(uint64_t);
428 value64 = radeon_get_gpu_clock_counter(rdev);
429 break;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500430 case RADEON_INFO_MAX_SE:
Alex Deucher64f759c2012-07-06 17:40:32 -0400431 if (rdev->family >= CHIP_BONAIRE)
432 *value = rdev->config.cik.max_shader_engines;
433 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400434 *value = rdev->config.si.max_shader_engines;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500435 else if (rdev->family >= CHIP_CAYMAN)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400436 *value = rdev->config.cayman.max_shader_engines;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500437 else if (rdev->family >= CHIP_CEDAR)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400438 *value = rdev->config.evergreen.num_ses;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500439 else
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400440 *value = 1;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500441 break;
442 case RADEON_INFO_MAX_SH_PER_SE:
Alex Deucher64f759c2012-07-06 17:40:32 -0400443 if (rdev->family >= CHIP_BONAIRE)
444 *value = rdev->config.cik.max_sh_per_se;
445 else if (rdev->family >= CHIP_TAHITI)
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400446 *value = rdev->config.si.max_sh_per_se;
Alex Deucher2e1a7672012-12-04 12:55:37 -0500447 else
448 return -EINVAL;
449 break;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400450 case RADEON_INFO_FASTFB_WORKING:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400451 *value = rdev->fastfb_working;
Samuel Lia0a53aa2013-04-08 17:25:47 -0400452 break;
Christian König902aaef2013-04-09 10:35:42 -0400453 case RADEON_INFO_RING_WORKING:
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100454 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400455 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
456 return -EFAULT;
457 }
458 switch (*value) {
Christian König902aaef2013-04-09 10:35:42 -0400459 case RADEON_CS_RING_GFX:
460 case RADEON_CS_RING_COMPUTE:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400461 *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400462 break;
463 case RADEON_CS_RING_DMA:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400464 *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
465 *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400466 break;
467 case RADEON_CS_RING_UVD:
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400468 *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
Christian König902aaef2013-04-09 10:35:42 -0400469 break;
Christian Königf7ba8b02014-01-27 10:16:06 -0700470 case RADEON_CS_RING_VCE:
471 *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
472 break;
Christian König902aaef2013-04-09 10:35:42 -0400473 default:
474 return -EINVAL;
475 }
476 break;
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400477 case RADEON_INFO_SI_TILE_MODE_ARRAY:
Alex Deucher64f759c2012-07-06 17:40:32 -0400478 if (rdev->family >= CHIP_BONAIRE) {
Alex Deucher39aee492013-04-10 13:41:25 -0400479 value = rdev->config.cik.tile_mode_array;
480 value_size = sizeof(uint32_t)*32;
481 } else if (rdev->family >= CHIP_TAHITI) {
482 value = rdev->config.si.tile_mode_array;
483 value_size = sizeof(uint32_t)*32;
484 } else {
485 DRM_DEBUG_KMS("tile mode array is si+ only!\n");
Alex Deucher64f759c2012-07-06 17:40:32 -0400486 return -EINVAL;
487 }
Jerome Glisse64d7b8b2013-04-09 11:17:08 -0400488 break;
Michel Dänzer32f79a82013-11-18 18:26:00 +0900489 case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
490 if (rdev->family >= CHIP_BONAIRE) {
491 value = rdev->config.cik.macrotile_mode_array;
492 value_size = sizeof(uint32_t)*16;
493 } else {
494 DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
495 return -EINVAL;
496 }
497 break;
Tom Stellarde5b9e752013-08-16 17:47:39 -0400498 case RADEON_INFO_SI_CP_DMA_COMPUTE:
499 *value = 1;
500 break;
Marek Olšák439a1cf2013-12-22 02:18:01 +0100501 case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
502 if (rdev->family >= CHIP_BONAIRE) {
503 *value = rdev->config.cik.backend_enable_mask;
504 } else if (rdev->family >= CHIP_TAHITI) {
505 *value = rdev->config.si.backend_enable_mask;
506 } else {
507 DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
508 }
509 break;
Alex Deucherf5f1f892014-01-20 18:20:29 -0500510 case RADEON_INFO_MAX_SCLK:
511 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
512 rdev->pm.dpm_enabled)
513 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
514 else
515 *value = rdev->pm.default_sclk * 10;
516 break;
Christian König98ccc292014-01-23 09:50:49 -0700517 case RADEON_INFO_VCE_FW_VERSION:
518 *value = rdev->vce.fw_version;
519 break;
520 case RADEON_INFO_VCE_FB_VERSION:
521 *value = rdev->vce.fb_version;
522 break;
Marek Olšák67e8e3f2014-03-02 00:56:18 +0100523 case RADEON_INFO_NUM_BYTES_MOVED:
524 value = (uint32_t*)&value64;
525 value_size = sizeof(uint64_t);
526 value64 = atomic64_read(&rdev->num_bytes_moved);
527 break;
528 case RADEON_INFO_VRAM_USAGE:
529 value = (uint32_t*)&value64;
530 value_size = sizeof(uint64_t);
531 value64 = atomic64_read(&rdev->vram_usage);
532 break;
533 case RADEON_INFO_GTT_USAGE:
534 value = (uint32_t*)&value64;
535 value_size = sizeof(uint64_t);
536 value64 = atomic64_read(&rdev->gtt_usage);
537 break;
Alex Deucher65fcf662014-06-02 16:13:21 -0400538 case RADEON_INFO_ACTIVE_CU_COUNT:
539 if (rdev->family >= CHIP_BONAIRE)
540 *value = rdev->config.cik.active_cus;
541 else if (rdev->family >= CHIP_TAHITI)
542 *value = rdev->config.si.active_cus;
543 else if (rdev->family >= CHIP_CAYMAN)
544 *value = rdev->config.cayman.active_simds;
545 else if (rdev->family >= CHIP_CEDAR)
546 *value = rdev->config.evergreen.active_simds;
547 else if (rdev->family >= CHIP_RV770)
548 *value = rdev->config.rv770.active_simds;
549 else if (rdev->family >= CHIP_R600)
550 *value = rdev->config.r600.active_simds;
551 else
552 *value = 1;
553 break;
Alex Deucherd6d2a182014-09-30 10:04:40 -0400554 case RADEON_INFO_CURRENT_GPU_TEMP:
555 /* get temperature in millidegrees C */
556 if (rdev->asic->pm.get_temperature)
557 *value = radeon_get_temperature(rdev);
558 else
559 *value = 0;
560 break;
Alex Deucher5c363a82014-09-30 11:33:30 -0400561 case RADEON_INFO_CURRENT_GPU_SCLK:
562 /* get sclk in Mhz */
563 if (rdev->pm.dpm_enabled)
564 *value = radeon_dpm_get_current_sclk(rdev) / 100;
565 else
566 *value = rdev->pm.current_sclk / 100;
567 break;
568 case RADEON_INFO_CURRENT_GPU_MCLK:
569 /* get mclk in Mhz */
570 if (rdev->pm.dpm_enabled)
571 *value = radeon_dpm_get_current_mclk(rdev) / 100;
572 else
573 *value = rdev->pm.current_mclk / 100;
574 break;
Alex Deucher4535cb92014-10-01 11:26:50 -0400575 case RADEON_INFO_READ_REG:
576 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
577 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
578 return -EFAULT;
579 }
580 if (radeon_get_allowed_info_register(rdev, *value, value))
581 return -EINVAL;
582 break;
Michel Dänzer3bc980b2015-06-16 17:28:16 +0900583 case RADEON_INFO_VA_UNMAP_WORKING:
584 *value = true;
585 break;
Marek Olšák72b90762015-04-29 19:40:33 +0200586 case RADEON_INFO_GPU_RESET_COUNTER:
587 *value = atomic_read(&rdev->gpu_reset_counter);
588 break;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200589 default:
Dave Airlied9fdaaf2010-08-02 10:42:55 +1000590 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200591 return -EINVAL;
592 }
Daniel Vetter1d6ac182013-12-11 11:34:44 +0100593 if (copy_to_user(value_ptr, (char*)value, value_size)) {
Marek Olšák6759a0a2012-08-09 16:34:17 +0200594 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200595 return -EFAULT;
596 }
597 return 0;
598}
599
600
601/*
602 * Outdated mess for old drm with Xorg being in charge (void function now).
603 */
Alex Deucherf482a142012-07-17 14:02:34 -0400604/**
Alex Deucher8c70e1c2015-10-02 16:52:58 -0400605 * radeon_driver_lastclose_kms - drm callback for last close
Alex Deucherf482a142012-07-17 14:02:34 -0400606 *
607 * @dev: drm dev pointer
608 *
Lukas Wunner8e5de1d2015-09-05 11:14:43 +0200609 * Switch vga_switcheroo state after last close (all asics).
Alex Deucherf482a142012-07-17 14:02:34 -0400610 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200611void radeon_driver_lastclose_kms(struct drm_device *dev)
612{
Alex Deucher8c70e1c2015-10-02 16:52:58 -0400613 struct radeon_device *rdev = dev->dev_private;
614
615 radeon_fbdev_restore_mode(rdev);
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000616 vga_switcheroo_process_delayed_switch();
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200617}
618
Alex Deucherf482a142012-07-17 14:02:34 -0400619/**
620 * radeon_driver_open_kms - drm callback for open
621 *
622 * @dev: drm dev pointer
623 * @file_priv: drm file
624 *
625 * On device open, init vm on cayman+ (all asics).
626 * Returns 0 on success, error on failure.
627 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200628int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
629{
Jerome Glisse721604a2012-01-05 22:11:05 -0500630 struct radeon_device *rdev = dev->dev_private;
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000631 int r;
Jerome Glisse721604a2012-01-05 22:11:05 -0500632
633 file_priv->driver_priv = NULL;
634
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000635 r = pm_runtime_get_sync(dev->dev);
636 if (r < 0)
637 return r;
638
Jerome Glisse721604a2012-01-05 22:11:05 -0500639 /* new gpu have virtual address space support */
640 if (rdev->family >= CHIP_CAYMAN) {
641 struct radeon_fpriv *fpriv;
Christian Königcc9e67e2014-07-18 13:48:10 +0200642 struct radeon_vm *vm;
Jerome Glisse721604a2012-01-05 22:11:05 -0500643 int r;
644
645 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
646 if (unlikely(!fpriv)) {
647 return -ENOMEM;
648 }
649
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400650 if (rdev->accel_working) {
Alex Deucher544143f2015-01-28 14:36:26 -0500651 vm = &fpriv->vm;
652 r = radeon_vm_init(rdev, vm);
653 if (r) {
654 kfree(fpriv);
655 return r;
656 }
657
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400658 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
659 if (r) {
Christian Königcc9e67e2014-07-18 13:48:10 +0200660 radeon_vm_fini(rdev, vm);
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400661 kfree(fpriv);
662 return r;
663 }
664
665 /* map the ib pool buffer read only into
666 * virtual address space */
Christian Königcc9e67e2014-07-18 13:48:10 +0200667 vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
668 rdev->ring_tmp_bo.bo);
669 r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
670 RADEON_VA_IB_OFFSET,
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400671 RADEON_VM_PAGE_READABLE |
672 RADEON_VM_PAGE_SNOOPED);
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400673 if (r) {
Christian Königcc9e67e2014-07-18 13:48:10 +0200674 radeon_vm_fini(rdev, vm);
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400675 kfree(fpriv);
676 return r;
677 }
Quentin Casasnovas74073c92014-03-18 17:16:52 +0100678 }
Jerome Glisse721604a2012-01-05 22:11:05 -0500679 file_priv->driver_priv = fpriv;
680 }
Dave Airlie10ebc0b2012-09-17 14:40:31 +1000681
682 pm_runtime_mark_last_busy(dev->dev);
683 pm_runtime_put_autosuspend(dev->dev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200684 return 0;
685}
686
Alex Deucherf482a142012-07-17 14:02:34 -0400687/**
688 * radeon_driver_postclose_kms - drm callback for post close
689 *
690 * @dev: drm dev pointer
691 * @file_priv: drm file
692 *
693 * On device post close, tear down vm on cayman+ (all asics).
694 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200695void radeon_driver_postclose_kms(struct drm_device *dev,
696 struct drm_file *file_priv)
697{
Jerome Glisse721604a2012-01-05 22:11:05 -0500698 struct radeon_device *rdev = dev->dev_private;
699
700 /* new gpu have virtual address space support */
701 if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
702 struct radeon_fpriv *fpriv = file_priv->driver_priv;
Christian Königcc9e67e2014-07-18 13:48:10 +0200703 struct radeon_vm *vm = &fpriv->vm;
Christian Königd72d43c2012-10-09 13:31:18 +0200704 int r;
705
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400706 if (rdev->accel_working) {
707 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
708 if (!r) {
Christian Königcc9e67e2014-07-18 13:48:10 +0200709 if (vm->ib_bo_va)
710 radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
Jérôme Glisse24f47ac2014-05-07 16:35:24 -0400711 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
712 }
Alex Deucher544143f2015-01-28 14:36:26 -0500713 radeon_vm_fini(rdev, vm);
Christian Königd72d43c2012-10-09 13:31:18 +0200714 }
Jerome Glisse721604a2012-01-05 22:11:05 -0500715
Jerome Glisse721604a2012-01-05 22:11:05 -0500716 kfree(fpriv);
717 file_priv->driver_priv = NULL;
718 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200719}
720
Alex Deucherf482a142012-07-17 14:02:34 -0400721/**
722 * radeon_driver_preclose_kms - drm callback for pre close
723 *
724 * @dev: drm dev pointer
725 * @file_priv: drm file
726 *
727 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
728 * (all asics).
729 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200730void radeon_driver_preclose_kms(struct drm_device *dev,
731 struct drm_file *file_priv)
732{
Dave Airlieab9e1f52010-07-13 11:11:11 +1000733 struct radeon_device *rdev = dev->dev_private;
Daniel Vetter45c1da52015-10-15 09:36:34 +0200734
735 mutex_lock(&rdev->gem.mutex);
Dave Airlieab9e1f52010-07-13 11:11:11 +1000736 if (rdev->hyperz_filp == file_priv)
737 rdev->hyperz_filp = NULL;
Marek Olšákdca0d612011-01-27 22:46:15 +0100738 if (rdev->cmask_filp == file_priv)
739 rdev->cmask_filp = NULL;
Daniel Vetter45c1da52015-10-15 09:36:34 +0200740 mutex_unlock(&rdev->gem.mutex);
741
Christian Königf2ba57b2013-04-08 12:41:29 +0200742 radeon_uvd_free_handles(rdev, file_priv);
Christian Königd93f7932013-05-23 12:10:04 +0200743 radeon_vce_free_handles(rdev, file_priv);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200744}
745
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200746/*
747 * VBlank related functions.
748 */
Alex Deucherf482a142012-07-17 14:02:34 -0400749/**
750 * radeon_get_vblank_counter_kms - get frame count
751 *
752 * @dev: drm dev pointer
Thierry Reding4e926d22015-12-16 15:31:47 +0100753 * @pipe: crtc to get the frame count from
Alex Deucherf482a142012-07-17 14:02:34 -0400754 *
755 * Gets the frame count on the requested crtc (all asics).
756 * Returns frame count on success, -EINVAL on failure.
757 */
Thierry Reding4e926d22015-12-16 15:31:47 +0100758u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200759{
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100760 int vpos, hpos, stat;
761 u32 count;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200762 struct radeon_device *rdev = dev->dev_private;
763
Thierry Reding85a21ea2016-01-04 18:19:12 +0100764 if (pipe >= rdev->num_crtc) {
Thierry Reding4e926d22015-12-16 15:31:47 +0100765 DRM_ERROR("Invalid crtc %u\n", pipe);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200766 return -EINVAL;
767 }
768
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100769 /* The hw increments its frame counter at start of vsync, not at start
770 * of vblank, as is required by DRM core vblank counter handling.
771 * Cook the hw count here to make it appear to the caller as if it
772 * incremented at start of vblank. We measure distance to start of
773 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
774 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
775 * result by 1 to give the proper appearance to caller.
776 */
Thierry Reding4e926d22015-12-16 15:31:47 +0100777 if (rdev->mode_info.crtcs[pipe]) {
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100778 /* Repeat readout if needed to provide stable result if
779 * we cross start of vsync during the queries.
780 */
781 do {
Thierry Reding4e926d22015-12-16 15:31:47 +0100782 count = radeon_get_vblank_counter(rdev, pipe);
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100783 /* Ask radeon_get_crtc_scanoutpos to return vpos as
784 * distance to start of vblank, instead of regular
785 * vertical scanout pos.
786 */
787 stat = radeon_get_crtc_scanoutpos(
Thierry Reding4e926d22015-12-16 15:31:47 +0100788 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100789 &vpos, &hpos, NULL, NULL,
Thierry Reding4e926d22015-12-16 15:31:47 +0100790 &rdev->mode_info.crtcs[pipe]->base.hwmode);
791 } while (count != radeon_get_vblank_counter(rdev, pipe));
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100792
793 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
794 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
795 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
796 }
797 else {
Thierry Reding4e926d22015-12-16 15:31:47 +0100798 DRM_DEBUG_VBL("crtc %u: dist from vblank start %d\n",
799 pipe, vpos);
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100800
801 /* Bump counter if we are at >= leading edge of vblank,
802 * but before vsync where vpos would turn negative and
803 * the hw counter really increments.
804 */
805 if (vpos >= 0)
806 count++;
807 }
808 }
809 else {
810 /* Fallback to use value as is. */
Thierry Reding4e926d22015-12-16 15:31:47 +0100811 count = radeon_get_vblank_counter(rdev, pipe);
Mario Kleinerc55d21e2015-11-25 20:14:31 +0100812 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
813 }
814
815 return count;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200816}
817
Alex Deucherf482a142012-07-17 14:02:34 -0400818/**
819 * radeon_enable_vblank_kms - enable vblank interrupt
820 *
821 * @dev: drm dev pointer
822 * @crtc: crtc to enable vblank interrupt for
823 *
824 * Enable the interrupt on the requested crtc (all asics).
825 * Returns 0 on success, -EINVAL on failure.
826 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200827int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
828{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200829 struct radeon_device *rdev = dev->dev_private;
Christian Koenigfb982572012-05-17 01:33:30 +0200830 unsigned long irqflags;
831 int r;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200832
Dave Airlie9c950a42010-04-23 13:21:58 +1000833 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200834 DRM_ERROR("Invalid crtc %d\n", crtc);
835 return -EINVAL;
836 }
837
Christian Koenigfb982572012-05-17 01:33:30 +0200838 spin_lock_irqsave(&rdev->irq.lock, irqflags);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200839 rdev->irq.crtc_vblank_int[crtc] = true;
Christian Koenigfb982572012-05-17 01:33:30 +0200840 r = radeon_irq_set(rdev);
841 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
842 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200843}
844
Alex Deucherf482a142012-07-17 14:02:34 -0400845/**
846 * radeon_disable_vblank_kms - disable vblank interrupt
847 *
848 * @dev: drm dev pointer
849 * @crtc: crtc to disable vblank interrupt for
850 *
851 * Disable the interrupt on the requested crtc (all asics).
852 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200853void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
854{
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200855 struct radeon_device *rdev = dev->dev_private;
Christian Koenigfb982572012-05-17 01:33:30 +0200856 unsigned long irqflags;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200857
Dave Airlie9c950a42010-04-23 13:21:58 +1000858 if (crtc < 0 || crtc >= rdev->num_crtc) {
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200859 DRM_ERROR("Invalid crtc %d\n", crtc);
860 return;
861 }
862
Christian Koenigfb982572012-05-17 01:33:30 +0200863 spin_lock_irqsave(&rdev->irq.lock, irqflags);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200864 rdev->irq.crtc_vblank_int[crtc] = false;
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200865 radeon_irq_set(rdev);
Christian Koenigfb982572012-05-17 01:33:30 +0200866 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200867}
868
Alex Deucherf482a142012-07-17 14:02:34 -0400869/**
870 * radeon_get_vblank_timestamp_kms - get vblank timestamp
871 *
872 * @dev: drm dev pointer
873 * @crtc: crtc to get the timestamp for
874 * @max_error: max error
875 * @vblank_time: time value
876 * @flags: flags passed to the driver
877 *
878 * Gets the timestamp on the requested crtc based on the
879 * scanout position. (all asics).
880 * Returns postive status flags on success, negative error on failure.
881 */
Mario Kleinerf5a80202010-10-23 04:42:17 +0200882int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
883 int *max_error,
884 struct timeval *vblank_time,
885 unsigned flags)
886{
887 struct drm_crtc *drmcrtc;
888 struct radeon_device *rdev = dev->dev_private;
889
890 if (crtc < 0 || crtc >= dev->num_crtcs) {
891 DRM_ERROR("Invalid crtc %d\n", crtc);
892 return -EINVAL;
893 }
894
895 /* Get associated drm_crtc: */
896 drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
Petr Mladekf5475cc2014-11-27 16:57:21 +0100897 if (!drmcrtc)
898 return -EINVAL;
Mario Kleinerf5a80202010-10-23 04:42:17 +0200899
900 /* Helper routine in DRM core does all the work: */
901 return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
902 vblank_time, flags,
Ville Syrjäläeba1f352015-09-14 22:43:43 +0300903 &drmcrtc->hwmode);
Mario Kleinerf5a80202010-10-23 04:42:17 +0200904}
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200905
Rob Clarkbaa70942013-08-02 13:27:49 -0400906const struct drm_ioctl_desc radeon_ioctls_kms[] = {
Daniel Vetter4b635392015-09-08 13:56:26 +0200907 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
908 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
909 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
910 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
911 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
912 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
913 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
914 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
915 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
916 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
917 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
918 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
919 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
920 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
921 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
922 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
923 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
924 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
925 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
926 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
927 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
928 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
929 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
930 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
931 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
932 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
933 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200934 /* KMS */
Daniel Vetterf8c47142015-09-08 13:56:30 +0200935 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
936 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
937 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
938 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
939 DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
940 DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
941 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
942 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
943 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
944 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
945 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
946 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
947 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
948 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
949 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200950};
Damien Lespiauf95aeb12014-06-09 14:39:49 +0100951int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);