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Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
Jeff Garzikfb9f8902007-03-02 18:17:22 -05002 * pata_cmd64x.c - CMD64x PATA for new ATA layer
Jeff Garzik669a5db2006-08-29 18:12:40 -04003 * (C) 2005 Red Hat Inc
Alan Coxab771632008-10-27 15:09:10 +00004 * Alan Cox <alan@lxorguk.ukuu.org.uk>
Bartlomiej Zolnierkiewicza2bd6222010-01-18 18:14:55 +01005 * (C) 2009-2010 Bartlomiej Zolnierkiewicz
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +03006 * (C) 2012 MontaVista Software, LLC <source@mvista.com>
Jeff Garzik669a5db2006-08-29 18:12:40 -04007 *
8 * Based upon
9 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
10 *
11 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
12 * Note, this driver is not used at all on other systems because
13 * there the "BIOS" has done all of the following already.
14 * Due to massive hardware bugs, UltraDMA is only supported
15 * on the 646U2 and not on the 646U.
16 *
17 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
18 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
19 *
20 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
21 *
22 * TODO
23 * Testing work
24 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040025
Jeff Garzik669a5db2006-08-29 18:12:40 -040026#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/pci.h>
Jeff Garzik669a5db2006-08-29 18:12:40 -040029#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <scsi/scsi_host.h>
32#include <linux/libata.h>
33
34#define DRV_NAME "pata_cmd64x"
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +030035#define DRV_VERSION "0.2.18"
Jeff Garzik669a5db2006-08-29 18:12:40 -040036
37/*
38 * CMD64x specific registers definition.
39 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040040
Jeff Garzik669a5db2006-08-29 18:12:40 -040041enum {
42 CFR = 0x50,
Bartlomiej Zolnierkiewicz03a849e2010-01-18 18:15:11 +010043 CFR_INTR_CH0 = 0x04,
James Bottomley9281b162011-04-24 14:30:14 -050044 CNTRL = 0x51,
45 CNTRL_CH0 = 0x04,
46 CNTRL_CH1 = 0x08,
Jeff Garzik669a5db2006-08-29 18:12:40 -040047 CMDTIM = 0x52,
48 ARTTIM0 = 0x53,
49 DRWTIM0 = 0x54,
50 ARTTIM1 = 0x55,
51 DRWTIM1 = 0x56,
52 ARTTIM23 = 0x57,
53 ARTTIM23_DIS_RA2 = 0x04,
54 ARTTIM23_DIS_RA3 = 0x08,
55 ARTTIM23_INTR_CH1 = 0x10,
Jeff Garzik669a5db2006-08-29 18:12:40 -040056 DRWTIM2 = 0x58,
57 BRST = 0x59,
58 DRWTIM3 = 0x5b,
59 BMIDECR0 = 0x70,
60 MRDMODE = 0x71,
61 MRDMODE_INTR_CH0 = 0x04,
62 MRDMODE_INTR_CH1 = 0x08,
Jeff Garzik669a5db2006-08-29 18:12:40 -040063 BMIDESR0 = 0x72,
64 UDIDETCR0 = 0x73,
65 DTPR0 = 0x74,
66 BMIDECR1 = 0x78,
67 BMIDECSR = 0x79,
Jeff Garzik669a5db2006-08-29 18:12:40 -040068 UDIDETCR1 = 0x7B,
69 DTPR1 = 0x7C
70};
71
Jeff Garzika73984a2007-03-09 08:37:46 -050072static int cmd648_cable_detect(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -040073{
74 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
75 u8 r;
76
77 /* Check cable detect bits */
78 pci_read_config_byte(pdev, BMIDECSR, &r);
79 if (r & (1 << ap->port_no))
Jeff Garzika73984a2007-03-09 08:37:46 -050080 return ATA_CBL_PATA80;
81 return ATA_CBL_PATA40;
Jeff Garzik669a5db2006-08-29 18:12:40 -040082}
83
84/**
Bartlomiej Zolnierkiewicz57242762011-10-11 19:57:40 +020085 * cmd64x_set_timing - set PIO and MWDMA timing
Jeff Garzik669a5db2006-08-29 18:12:40 -040086 * @ap: ATA interface
87 * @adev: ATA device
Alan Cox05d1eff2007-08-10 13:59:49 -070088 * @mode: mode
Jeff Garzik669a5db2006-08-29 18:12:40 -040089 *
Alan Cox05d1eff2007-08-10 13:59:49 -070090 * Called to do the PIO and MWDMA mode setup.
Jeff Garzik669a5db2006-08-29 18:12:40 -040091 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040092
Alan Cox05d1eff2007-08-10 13:59:49 -070093static void cmd64x_set_timing(struct ata_port *ap, struct ata_device *adev, u8 mode)
Jeff Garzik669a5db2006-08-29 18:12:40 -040094{
95 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
96 struct ata_timing t;
97 const unsigned long T = 1000000 / 33;
98 const u8 setup_data[] = { 0x40, 0x40, 0x40, 0x80, 0x00 };
Jeff Garzik85cd7252006-08-31 00:03:49 -040099
Jeff Garzik669a5db2006-08-29 18:12:40 -0400100 u8 reg;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400101
Jeff Garzik669a5db2006-08-29 18:12:40 -0400102 /* Port layout is not logical so use a table */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400103 const u8 arttim_port[2][2] = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400104 { ARTTIM0, ARTTIM1 },
105 { ARTTIM23, ARTTIM23 }
106 };
107 const u8 drwtim_port[2][2] = {
108 { DRWTIM0, DRWTIM1 },
109 { DRWTIM2, DRWTIM3 }
110 };
Jeff Garzik85cd7252006-08-31 00:03:49 -0400111
Jeff Garzik669a5db2006-08-29 18:12:40 -0400112 int arttim = arttim_port[ap->port_no][adev->devno];
113 int drwtim = drwtim_port[ap->port_no][adev->devno];
Jeff Garzik85cd7252006-08-31 00:03:49 -0400114
Alan Cox05d1eff2007-08-10 13:59:49 -0700115 /* ata_timing_compute is smart and will produce timings for MWDMA
116 that don't violate the drives PIO capabilities. */
117 if (ata_timing_compute(adev, mode, &t, T, 0) < 0) {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400118 printk(KERN_ERR DRV_NAME ": mode computation failed.\n");
119 return;
120 }
121 if (ap->port_no) {
122 /* Slave has shared address setup */
123 struct ata_device *pair = ata_dev_pair(adev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400124
Jeff Garzik669a5db2006-08-29 18:12:40 -0400125 if (pair) {
126 struct ata_timing tp;
127 ata_timing_compute(pair, pair->pio_mode, &tp, T, 0);
128 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
129 }
130 }
Jeff Garzik85cd7252006-08-31 00:03:49 -0400131
Jeff Garzik669a5db2006-08-29 18:12:40 -0400132 printk(KERN_DEBUG DRV_NAME ": active %d recovery %d setup %d.\n",
133 t.active, t.recover, t.setup);
134 if (t.recover > 16) {
135 t.active += t.recover - 16;
136 t.recover = 16;
137 }
138 if (t.active > 16)
139 t.active = 16;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400140
Jeff Garzik669a5db2006-08-29 18:12:40 -0400141 /* Now convert the clocks into values we can actually stuff into
142 the chip */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400143
Bartlomiej Zolnierkiewicza2bd6222010-01-18 18:14:55 +0100144 if (t.recover == 16)
145 t.recover = 0;
146 else if (t.recover > 1)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400147 t.recover--;
148 else
149 t.recover = 15;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400150
Jeff Garzik669a5db2006-08-29 18:12:40 -0400151 if (t.setup > 4)
152 t.setup = 0xC0;
153 else
154 t.setup = setup_data[t.setup];
Jeff Garzik85cd7252006-08-31 00:03:49 -0400155
Jeff Garzik669a5db2006-08-29 18:12:40 -0400156 t.active &= 0x0F; /* 0 = 16 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400157
Jeff Garzik669a5db2006-08-29 18:12:40 -0400158 /* Load setup timing */
159 pci_read_config_byte(pdev, arttim, &reg);
160 reg &= 0x3F;
161 reg |= t.setup;
162 pci_write_config_byte(pdev, arttim, reg);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400163
Jeff Garzik669a5db2006-08-29 18:12:40 -0400164 /* Load active/recovery */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400165 pci_write_config_byte(pdev, drwtim, (t.active << 4) | t.recover);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400166}
167
168/**
Alan Cox05d1eff2007-08-10 13:59:49 -0700169 * cmd64x_set_piomode - set initial PIO mode data
170 * @ap: ATA interface
171 * @adev: ATA device
172 *
173 * Used when configuring the devices ot set the PIO timings. All the
174 * actual work is done by the PIO/MWDMA setting helper
175 */
176
177static void cmd64x_set_piomode(struct ata_port *ap, struct ata_device *adev)
178{
179 cmd64x_set_timing(ap, adev, adev->pio_mode);
180}
181
182/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400183 * cmd64x_set_dmamode - set initial DMA mode data
184 * @ap: ATA interface
185 * @adev: ATA device
186 *
187 * Called to do the DMA mode setup.
188 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400189
Jeff Garzik669a5db2006-08-29 18:12:40 -0400190static void cmd64x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
191{
192 static const u8 udma_data[] = {
Alan6a40da02007-01-24 11:49:03 +0000193 0x30, 0x20, 0x10, 0x20, 0x10, 0x00
Jeff Garzik669a5db2006-08-29 18:12:40 -0400194 };
Jeff Garzik85cd7252006-08-31 00:03:49 -0400195
Jeff Garzik669a5db2006-08-29 18:12:40 -0400196 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
197 u8 regU, regD;
198
199 int pciU = UDIDETCR0 + 8 * ap->port_no;
200 int pciD = BMIDESR0 + 8 * ap->port_no;
201 int shift = 2 * adev->devno;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400202
Jeff Garzik669a5db2006-08-29 18:12:40 -0400203 pci_read_config_byte(pdev, pciD, &regD);
204 pci_read_config_byte(pdev, pciU, &regU);
205
Alan6a40da02007-01-24 11:49:03 +0000206 /* DMA bits off */
207 regD &= ~(0x20 << adev->devno);
208 /* DMA control bits */
209 regU &= ~(0x30 << shift);
210 /* DMA timing bits */
211 regU &= ~(0x05 << adev->devno);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400212
Alan6a40da02007-01-24 11:49:03 +0000213 if (adev->dma_mode >= XFER_UDMA_0) {
Adrian Bunk24b7ce92007-10-20 01:02:48 +0200214 /* Merge the timing value */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400215 regU |= udma_data[adev->dma_mode - XFER_UDMA_0] << shift;
Alan6a40da02007-01-24 11:49:03 +0000216 /* Merge the control bits */
217 regU |= 1 << adev->devno; /* UDMA on */
Bartlomiej Zolnierkiewicz509426b2009-12-20 19:22:33 +0100218 if (adev->dma_mode > XFER_UDMA_2) /* 15nS timing */
Alan6a40da02007-01-24 11:49:03 +0000219 regU |= 4 << adev->devno;
Alan Cox05d1eff2007-08-10 13:59:49 -0700220 } else {
221 regU &= ~ (1 << adev->devno); /* UDMA off */
222 cmd64x_set_timing(ap, adev, adev->dma_mode);
223 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400224
225 regD |= 0x20 << adev->devno;
226
227 pci_write_config_byte(pdev, pciU, regU);
228 pci_write_config_byte(pdev, pciD, regD);
229}
230
231/**
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +0300232 * cmd64x_sff_irq_check - check IDE interrupt
233 * @ap: ATA interface
234 *
235 * Check IDE interrupt in CFR/ARTTIM23 registers.
236 */
237
238static bool cmd64x_sff_irq_check(struct ata_port *ap)
239{
240 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
241 int irq_mask = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
242 int irq_reg = ap->port_no ? ARTTIM23 : CFR;
243 u8 irq_stat;
244
245 /* NOTE: reading the register should clear the interrupt */
246 pci_read_config_byte(pdev, irq_reg, &irq_stat);
247
248 return irq_stat & irq_mask;
249}
250
251/**
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300252 * cmd64x_sff_irq_clear - clear IDE interrupt
253 * @ap: ATA interface
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300254 *
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300255 * Clear IDE interrupt in CFR/ARTTIM23 and DMA status registers.
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300256 */
257
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300258static void cmd64x_sff_irq_clear(struct ata_port *ap)
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300259{
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300260 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
261 int irq_reg = ap->port_no ? ARTTIM23 : CFR;
262 u8 irq_stat;
263
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300264 ata_bmdma_irq_clear(ap);
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300265
266 /* Reading the register should be enough to clear the interrupt */
267 pci_read_config_byte(pdev, irq_reg, &irq_stat);
268}
269
270/**
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +0300271 * cmd648_sff_irq_check - check IDE interrupt
272 * @ap: ATA interface
273 *
274 * Check IDE interrupt in MRDMODE register.
275 */
276
277static bool cmd648_sff_irq_check(struct ata_port *ap)
278{
279 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
280 unsigned long base = pci_resource_start(pdev, 4);
281 int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
282 u8 mrdmode = inb(base + 1);
283
284 return mrdmode & irq_mask;
285}
286
287/**
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300288 * cmd648_sff_irq_clear - clear IDE interrupt
289 * @ap: ATA interface
Jeff Garzik669a5db2006-08-29 18:12:40 -0400290 *
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300291 * Clear IDE interrupt in MRDMODE and DMA status registers.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400292 */
293
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300294static void cmd648_sff_irq_clear(struct ata_port *ap)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400295{
Jeff Garzik669a5db2006-08-29 18:12:40 -0400296 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300297 unsigned long base = pci_resource_start(pdev, 4);
298 int irq_mask = ap->port_no ? MRDMODE_INTR_CH1 : MRDMODE_INTR_CH0;
299 u8 mrdmode;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400300
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300301 ata_bmdma_irq_clear(ap);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400302
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300303 /* Clear this port's interrupt bit (leaving the other port alone) */
304 mrdmode = inb(base + 1);
305 mrdmode &= ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1);
306 outb(mrdmode | irq_mask, base + 1);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400307}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400308
Jeff Garzik669a5db2006-08-29 18:12:40 -0400309/**
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300310 * cmd646r1_bmdma_stop - DMA stop callback
Jeff Garzik669a5db2006-08-29 18:12:40 -0400311 * @qc: Command in progress
312 *
Jeff Garzik06393af2009-12-20 15:39:55 -0500313 * Stub for now while investigating the r1 quirk in the old driver.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400314 */
315
Jeff Garzik06393af2009-12-20 15:39:55 -0500316static void cmd646r1_bmdma_stop(struct ata_queued_cmd *qc)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400317{
318 ata_bmdma_stop(qc);
319}
Jeff Garzik85cd7252006-08-31 00:03:49 -0400320
Jeff Garzik669a5db2006-08-29 18:12:40 -0400321static struct scsi_host_template cmd64x_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900322 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400323};
324
Tejun Heo029cfd62008-03-25 12:22:49 +0900325static const struct ata_port_operations cmd64x_base_ops = {
326 .inherits = &ata_bmdma_port_ops,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400327 .set_piomode = cmd64x_set_piomode,
328 .set_dmamode = cmd64x_set_dmamode,
Tejun Heo029cfd62008-03-25 12:22:49 +0900329};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400330
Tejun Heo029cfd62008-03-25 12:22:49 +0900331static struct ata_port_operations cmd64x_port_ops = {
332 .inherits = &cmd64x_base_ops,
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +0300333 .sff_irq_check = cmd64x_sff_irq_check,
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300334 .sff_irq_clear = cmd64x_sff_irq_clear,
Jeff Garzika73984a2007-03-09 08:37:46 -0500335 .cable_detect = ata_cable_40wire,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400336};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400337
338static struct ata_port_operations cmd646r1_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900339 .inherits = &cmd64x_base_ops,
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +0300340 .sff_irq_check = cmd64x_sff_irq_check,
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300341 .sff_irq_clear = cmd64x_sff_irq_clear,
Jeff Garzik06393af2009-12-20 15:39:55 -0500342 .bmdma_stop = cmd646r1_bmdma_stop,
Tejun Heo029cfd62008-03-25 12:22:49 +0900343 .cable_detect = ata_cable_40wire,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400344};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400345
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300346static struct ata_port_operations cmd646r3_port_ops = {
347 .inherits = &cmd64x_base_ops,
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +0300348 .sff_irq_check = cmd648_sff_irq_check,
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300349 .sff_irq_clear = cmd648_sff_irq_clear,
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300350 .cable_detect = ata_cable_40wire,
351};
352
Jeff Garzik669a5db2006-08-29 18:12:40 -0400353static struct ata_port_operations cmd648_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900354 .inherits = &cmd64x_base_ops,
Sergei Shtylyovb8cec3c2012-03-11 22:28:18 +0300355 .sff_irq_check = cmd648_sff_irq_check,
Sergei Shtylyov419fd242012-03-11 22:27:01 +0300356 .sff_irq_clear = cmd648_sff_irq_clear,
Tejun Heo029cfd62008-03-25 12:22:49 +0900357 .cable_detect = cmd648_cable_detect,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400358};
359
Bartlomiej Zolnierkiewiczf4c6ae52011-10-11 19:56:03 +0200360static void cmd64x_fixup(struct pci_dev *pdev)
361{
362 u8 mrdmode;
363
364 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
365 pci_read_config_byte(pdev, MRDMODE, &mrdmode);
366 mrdmode &= ~0x30; /* IRQ set up */
367 mrdmode |= 0x02; /* Memory read line enable */
368 pci_write_config_byte(pdev, MRDMODE, mrdmode);
369
370 /* PPC specific fixup copied from old driver */
371#ifdef CONFIG_PPC
372 pci_write_config_byte(pdev, UDIDETCR0, 0xF0);
373#endif
374}
375
Jeff Garzik669a5db2006-08-29 18:12:40 -0400376static int cmd64x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
377{
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300378 static const struct ata_port_info cmd_info[7] = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400379 { /* CMD 643 - no UDMA */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400380 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100381 .pio_mask = ATA_PIO4,
382 .mwdma_mask = ATA_MWDMA2,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400383 .port_ops = &cmd64x_port_ops
384 },
385 { /* CMD 646 with broken UDMA */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400386 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100387 .pio_mask = ATA_PIO4,
388 .mwdma_mask = ATA_MWDMA2,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400389 .port_ops = &cmd64x_port_ops
390 },
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300391 { /* CMD 646U with broken UDMA */
392 .flags = ATA_FLAG_SLAVE_POSS,
393 .pio_mask = ATA_PIO4,
394 .mwdma_mask = ATA_MWDMA2,
395 .port_ops = &cmd646r3_port_ops
396 },
397 { /* CMD 646U2 with working UDMA */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400398 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100399 .pio_mask = ATA_PIO4,
400 .mwdma_mask = ATA_MWDMA2,
Alan Coxdbf0c892007-07-26 18:43:01 +0100401 .udma_mask = ATA_UDMA2,
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300402 .port_ops = &cmd646r3_port_ops
Jeff Garzik669a5db2006-08-29 18:12:40 -0400403 },
404 { /* CMD 646 rev 1 */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400405 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100406 .pio_mask = ATA_PIO4,
407 .mwdma_mask = ATA_MWDMA2,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400408 .port_ops = &cmd646r1_port_ops
409 },
410 { /* CMD 648 */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400411 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100412 .pio_mask = ATA_PIO4,
413 .mwdma_mask = ATA_MWDMA2,
Alan Coxdbf0c892007-07-26 18:43:01 +0100414 .udma_mask = ATA_UDMA4,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400415 .port_ops = &cmd648_port_ops
416 },
417 { /* CMD 649 */
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400418 .flags = ATA_FLAG_SLAVE_POSS,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100419 .pio_mask = ATA_PIO4,
420 .mwdma_mask = ATA_MWDMA2,
Alan Coxdbf0c892007-07-26 18:43:01 +0100421 .udma_mask = ATA_UDMA5,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400422 .port_ops = &cmd648_port_ops
423 }
424 };
Jeff Garzik641589b2012-07-25 16:07:40 -0400425 const struct ata_port_info *ppi[] = {
James Bottomley9281b162011-04-24 14:30:14 -0500426 &cmd_info[id->driver_data],
427 &cmd_info[id->driver_data],
428 NULL
429 };
Bartlomiej Zolnierkiewiczf4c6ae52011-10-11 19:56:03 +0200430 u8 reg;
Tejun Heof08048e2008-03-25 12:22:47 +0900431 int rc;
James Bottomley9281b162011-04-24 14:30:14 -0500432 struct pci_dev *bridge = pdev->bus->self;
433 /* mobility split bridges don't report enabled ports correctly */
434 int port_ok = !(bridge && bridge->vendor ==
435 PCI_VENDOR_ID_MOBILITY_ELECTRONICS);
436 /* all (with exceptions below) apart from 643 have CNTRL_CH0 bit */
437 int cntrl_ch0_ok = (id->driver_data != 0);
Tejun Heof08048e2008-03-25 12:22:47 +0900438
439 rc = pcim_enable_device(pdev);
440 if (rc)
441 return rc;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400442
Jeff Garzik669a5db2006-08-29 18:12:40 -0400443 if (id->driver_data == 0) /* 643 */
Tejun Heo9363c382008-04-07 22:47:16 +0900444 ata_pci_bmdma_clear_simplex(pdev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400445
Sergei Shtylyov8fcfa7b2012-03-11 22:29:02 +0300446 if (pdev->device == PCI_DEVICE_ID_CMD_646)
447 switch (pdev->revision) {
448 /* UDMA works since rev 5 */
449 default:
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300450 ppi[0] = &cmd_info[3];
451 ppi[1] = &cmd_info[3];
452 break;
453 /* Interrupts in MRDMODE since rev 3 */
454 case 3:
455 case 4:
Tejun Heo1626aeb2007-05-04 12:43:58 +0200456 ppi[0] = &cmd_info[2];
James Bottomley9281b162011-04-24 14:30:14 -0500457 ppi[1] = &cmd_info[2];
Sergei Shtylyov8fcfa7b2012-03-11 22:29:02 +0300458 break;
Sergei Shtylyov8fcfa7b2012-03-11 22:29:02 +0300459 /* Rev 1 with other problems? */
460 case 1:
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300461 ppi[0] = &cmd_info[4];
462 ppi[1] = &cmd_info[4];
Sergei Shtylyov8fcfa7b2012-03-11 22:29:02 +0300463 /* FALL THRU */
464 /* Early revs have no CNTRL_CH0 */
465 case 2:
466 case 0:
James Bottomley9281b162011-04-24 14:30:14 -0500467 cntrl_ch0_ok = 0;
Sergei Shtylyov8fcfa7b2012-03-11 22:29:02 +0300468 break;
469 }
Jeff Garzik669a5db2006-08-29 18:12:40 -0400470
Bartlomiej Zolnierkiewiczf4c6ae52011-10-11 19:56:03 +0200471 cmd64x_fixup(pdev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400472
James Bottomley9281b162011-04-24 14:30:14 -0500473 /* check for enabled ports */
474 pci_read_config_byte(pdev, CNTRL, &reg);
475 if (!port_ok)
Joe Perchesa52f5142012-10-28 01:05:40 -0700476 dev_notice(&pdev->dev, "Mobility Bridge detected, ignoring CNTRL port enable/disable\n");
James Bottomley9281b162011-04-24 14:30:14 -0500477 if (port_ok && cntrl_ch0_ok && !(reg & CNTRL_CH0)) {
Joe Perchesa52f5142012-10-28 01:05:40 -0700478 dev_notice(&pdev->dev, "Primary port is disabled\n");
James Bottomley9281b162011-04-24 14:30:14 -0500479 ppi[0] = &ata_dummy_port_info;
Jeff Garzik641589b2012-07-25 16:07:40 -0400480
James Bottomley9281b162011-04-24 14:30:14 -0500481 }
482 if (port_ok && !(reg & CNTRL_CH1)) {
Joe Perchesa52f5142012-10-28 01:05:40 -0700483 dev_notice(&pdev->dev, "Secondary port is disabled\n");
James Bottomley9281b162011-04-24 14:30:14 -0500484 ppi[1] = &ata_dummy_port_info;
485 }
486
Tejun Heo1c5afdf2010-05-19 22:10:22 +0200487 return ata_pci_bmdma_init_one(pdev, ppi, &cmd64x_sht, NULL, 0);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400488}
489
Tejun Heo438ac6d2007-03-02 17:31:26 +0900490#ifdef CONFIG_PM
Alan7f72a372006-11-22 16:59:07 +0000491static int cmd64x_reinit_one(struct pci_dev *pdev)
492{
Jingoo Han0a86e1c2013-06-03 14:05:36 +0900493 struct ata_host *host = pci_get_drvdata(pdev);
Tejun Heof08048e2008-03-25 12:22:47 +0900494 int rc;
495
496 rc = ata_pci_device_do_resume(pdev);
497 if (rc)
498 return rc;
499
Bartlomiej Zolnierkiewiczf4c6ae52011-10-11 19:56:03 +0200500 cmd64x_fixup(pdev);
501
Tejun Heof08048e2008-03-25 12:22:47 +0900502 ata_host_resume(host);
503 return 0;
Alan7f72a372006-11-22 16:59:07 +0000504}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900505#endif
Alan7f72a372006-11-22 16:59:07 +0000506
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400507static const struct pci_device_id cmd64x[] = {
508 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
509 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
Sergei Shtylyov8a686bc2012-03-11 22:25:30 +0300510 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 5 },
511 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 6 },
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400512
513 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400514};
515
516static struct pci_driver cmd64x_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400517 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400518 .id_table = cmd64x,
519 .probe = cmd64x_init_one,
Alan7f72a372006-11-22 16:59:07 +0000520 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900521#ifdef CONFIG_PM
Alan7f72a372006-11-22 16:59:07 +0000522 .suspend = ata_pci_device_suspend,
523 .resume = cmd64x_reinit_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900524#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400525};
526
Axel Lin2fc75da2012-04-19 13:43:05 +0800527module_pci_driver(cmd64x_pci_driver);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400528
Jeff Garzik669a5db2006-08-29 18:12:40 -0400529MODULE_AUTHOR("Alan Cox");
530MODULE_DESCRIPTION("low-level driver for CMD64x series PATA controllers");
531MODULE_LICENSE("GPL");
532MODULE_DEVICE_TABLE(pci, cmd64x);
533MODULE_VERSION(DRV_VERSION);