| Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. |
| 3 | * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
| 10 | #ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H |
| 11 | #define _DT_BINDINGS_CLOCK_EXYNOS7_H |
| 12 | |
| 13 | /* TOPC */ |
| 14 | #define DOUT_ACLK_PERIS 1 |
| 15 | #define DOUT_SCLK_BUS0_PLL 2 |
| 16 | #define DOUT_SCLK_BUS1_PLL 3 |
| 17 | #define DOUT_SCLK_CC_PLL 4 |
| 18 | #define DOUT_SCLK_MFC_PLL 5 |
| Naveen Krishna Ch | f5e127c | 2014-10-28 16:48:53 +0530 | [diff] [blame] | 19 | #define DOUT_ACLK_CCORE_133 6 |
| 20 | #define TOPC_NR_CLK 7 |
| Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 21 | |
| 22 | /* TOP0 */ |
| 23 | #define DOUT_ACLK_PERIC1 1 |
| 24 | #define DOUT_ACLK_PERIC0 2 |
| 25 | #define CLK_SCLK_UART0 3 |
| 26 | #define CLK_SCLK_UART1 4 |
| 27 | #define CLK_SCLK_UART2 5 |
| 28 | #define CLK_SCLK_UART3 6 |
| 29 | #define TOP0_NR_CLK 7 |
| 30 | |
| Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 31 | /* TOP1 */ |
| 32 | #define DOUT_ACLK_FSYS1_200 1 |
| 33 | #define DOUT_ACLK_FSYS0_200 2 |
| 34 | #define DOUT_SCLK_MMC2 3 |
| 35 | #define DOUT_SCLK_MMC1 4 |
| 36 | #define DOUT_SCLK_MMC0 5 |
| 37 | #define CLK_SCLK_MMC2 6 |
| 38 | #define CLK_SCLK_MMC1 7 |
| 39 | #define CLK_SCLK_MMC0 8 |
| 40 | #define TOP1_NR_CLK 9 |
| 41 | |
| Naveen Krishna Ch | f5e127c | 2014-10-28 16:48:53 +0530 | [diff] [blame] | 42 | /* CCORE */ |
| 43 | #define PCLK_RTC 1 |
| 44 | #define CCORE_NR_CLK 2 |
| 45 | |
| Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 46 | /* PERIC0 */ |
| 47 | #define PCLK_UART0 1 |
| 48 | #define SCLK_UART0 2 |
| Naveen Krishna Ch | 57a2b48 | 2014-10-21 11:13:51 +0530 | [diff] [blame] | 49 | #define PCLK_HSI2C0 3 |
| 50 | #define PCLK_HSI2C1 4 |
| 51 | #define PCLK_HSI2C4 5 |
| 52 | #define PCLK_HSI2C5 6 |
| 53 | #define PCLK_HSI2C9 7 |
| 54 | #define PCLK_HSI2C10 8 |
| 55 | #define PCLK_HSI2C11 9 |
| Naveen Krishna Ch | 2ab2dfe | 2014-10-28 16:48:54 +0530 | [diff] [blame] | 56 | #define PCLK_PWM 10 |
| 57 | #define SCLK_PWM 11 |
| Abhilash Kesavan | 932e982 | 2014-10-28 16:48:55 +0530 | [diff] [blame^] | 58 | #define PCLK_ADCIF 12 |
| 59 | #define PERIC0_NR_CLK 13 |
| Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 60 | |
| 61 | /* PERIC1 */ |
| 62 | #define PCLK_UART1 1 |
| 63 | #define PCLK_UART2 2 |
| 64 | #define PCLK_UART3 3 |
| 65 | #define SCLK_UART1 4 |
| 66 | #define SCLK_UART2 5 |
| 67 | #define SCLK_UART3 6 |
| Naveen Krishna Ch | 57a2b48 | 2014-10-21 11:13:51 +0530 | [diff] [blame] | 68 | #define PCLK_HSI2C2 7 |
| 69 | #define PCLK_HSI2C3 8 |
| 70 | #define PCLK_HSI2C6 9 |
| 71 | #define PCLK_HSI2C7 10 |
| 72 | #define PCLK_HSI2C8 11 |
| 73 | #define PERIC1_NR_CLK 12 |
| Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 74 | |
| 75 | /* PERIS */ |
| 76 | #define PCLK_CHIPID 1 |
| 77 | #define SCLK_CHIPID 2 |
| Naveen Krishna Ch | 2ab2dfe | 2014-10-28 16:48:54 +0530 | [diff] [blame] | 78 | #define PCLK_WDT 3 |
| 79 | #define PCLK_TMU 4 |
| 80 | #define SCLK_TMU 5 |
| 81 | #define PERIS_NR_CLK 6 |
| Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 82 | |
| Naveen Krishna Ch | 6d0c8c7 | 2014-10-21 11:13:52 +0530 | [diff] [blame] | 83 | /* FSYS0 */ |
| 84 | #define ACLK_MMC2 1 |
| 85 | #define FSYS0_NR_CLK 2 |
| 86 | |
| 87 | /* FSYS1 */ |
| 88 | #define ACLK_MMC1 1 |
| 89 | #define ACLK_MMC0 2 |
| 90 | #define FSYS1_NR_CLK 3 |
| 91 | |
| Naveen Krishna Ch | 532abc3 | 2014-09-22 10:17:04 +0530 | [diff] [blame] | 92 | #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */ |