blob: 26e5a968d49d1ffa39619d172237f28c4c74f1a7 [file] [log] [blame]
Heiko Stuebnerf75efdd2013-09-29 13:25:08 +02001/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/interrupt-controller/irq.h>
17#include <dt-bindings/interrupt-controller/arm-gic.h>
18#include "skeleton.dtsi"
19
20/ {
21 interrupt-parent = <&gic>;
22
23 soc {
24 #address-cells = <1>;
25 #size-cells = <1>;
26 compatible = "simple-bus";
27 ranges;
28
Heiko Stuebnerf6f70cf2013-06-17 21:28:57 +020029 scu@1013c000 {
30 compatible = "arm,cortex-a9-scu";
31 reg = <0x1013c000 0x100>;
32 };
33
Heiko Stuebner46b82192013-06-17 22:17:16 +020034 pmu@20004000 {
35 compatible = "rockchip,rk3066-pmu";
36 reg = <0x20004000 0x100>;
37 };
38
Heiko Stuebnerf75efdd2013-09-29 13:25:08 +020039 gic: interrupt-controller@1013d000 {
40 compatible = "arm,cortex-a9-gic";
41 interrupt-controller;
42 #interrupt-cells = <3>;
43 reg = <0x1013d000 0x1000>,
44 <0x1013c100 0x0100>;
45 };
46
47 L2: l2-cache-controller@10138000 {
48 compatible = "arm,pl310-cache";
49 reg = <0x10138000 0x1000>;
50 cache-unified;
51 cache-level = <2>;
52 };
53
Heiko Stuebnerf95a2b32013-09-30 16:29:55 +020054 global-timer@1013c200 {
55 compatible = "arm,cortex-a9-global-timer";
56 reg = <0x1013c200 0x20>;
57 interrupts = <GIC_PPI 11 0x304>;
58 clocks = <&dummy150m>;
59 };
60
Heiko Stuebnerf75efdd2013-09-29 13:25:08 +020061 local-timer@1013c600 {
62 compatible = "arm,cortex-a9-twd-timer";
63 reg = <0x1013c600 0x20>;
64 interrupts = <GIC_PPI 13 0x304>;
65 clocks = <&dummy150m>;
66 };
67
68 uart0: serial@10124000 {
69 compatible = "snps,dw-apb-uart";
70 reg = <0x10124000 0x400>;
71 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
72 reg-shift = <2>;
73 reg-io-width = <1>;
74 clocks = <&clk_gates1 8>;
75 status = "disabled";
76 };
77
78 uart1: serial@10126000 {
79 compatible = "snps,dw-apb-uart";
80 reg = <0x10126000 0x400>;
81 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
82 reg-shift = <2>;
83 reg-io-width = <1>;
84 clocks = <&clk_gates1 10>;
85 status = "disabled";
86 };
87
88 uart2: serial@20064000 {
89 compatible = "snps,dw-apb-uart";
90 reg = <0x20064000 0x400>;
91 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
92 reg-shift = <2>;
93 reg-io-width = <1>;
94 clocks = <&clk_gates1 12>;
95 status = "disabled";
96 };
97
98 uart3: serial@20068000 {
99 compatible = "snps,dw-apb-uart";
100 reg = <0x20068000 0x400>;
101 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
102 reg-shift = <2>;
103 reg-io-width = <1>;
104 clocks = <&clk_gates1 14>;
105 status = "disabled";
106 };
107
108 dwmmc@10214000 {
109 compatible = "rockchip,rk2928-dw-mshc";
110 reg = <0x10214000 0x1000>;
111 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
112 #address-cells = <1>;
113 #size-cells = <0>;
114
115 clocks = <&clk_gates5 10>, <&clk_gates2 11>;
116 clock-names = "biu", "ciu";
117
118 status = "disabled";
119 };
120
121 dwmmc@10218000 {
122 compatible = "rockchip,rk2928-dw-mshc";
123 reg = <0x10218000 0x1000>;
124 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
125 #address-cells = <1>;
126 #size-cells = <0>;
127
128 clocks = <&clk_gates5 11>, <&clk_gates2 13>;
129 clock-names = "biu", "ciu";
130
131 status = "disabled";
132 };
133 };
134};