blob: bfd113ce3b4764c9211c0edb6345c0ee0be505d8 [file] [log] [blame]
Mythri P Kc3198a52011-03-12 12:04:27 +05301/*
2 * hdmi.c
3 *
4 * HDMI interface DSS driver setting for TI's OMAP4 family of processor.
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22#define DSS_SUBSYS_NAME "HDMI"
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/err.h>
27#include <linux/io.h>
28#include <linux/interrupt.h>
29#include <linux/mutex.h>
30#include <linux/delay.h>
31#include <linux/string.h>
Tomi Valkeinen24e62892011-05-23 11:51:18 +030032#include <linux/platform_device.h>
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +030033#include <linux/pm_runtime.h>
34#include <linux/clk.h>
Tomi Valkeinena0b38cc2011-05-11 14:05:07 +030035#include <video/omapdss.h>
Ricardo Neriad44cc32011-05-18 22:31:56 -050036#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
37 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
38#include <sound/soc.h>
39#include <sound/pcm_params.h>
40#endif
Mythri P Kc3198a52011-03-12 12:04:27 +053041
42#include "dss.h"
43#include "hdmi.h"
Ricardo Neriad44cc32011-05-18 22:31:56 -050044#include "dss_features.h"
Mythri P Kc3198a52011-03-12 12:04:27 +053045
Mythri P K95a8aeb2011-09-08 19:06:18 +053046#define HDMI_WP 0x0
47#define HDMI_CORE_SYS 0x400
48#define HDMI_CORE_AV 0x900
49#define HDMI_PLLCTRL 0x200
50#define HDMI_PHY 0x300
51
Mythri P Kc3198a52011-03-12 12:04:27 +053052static struct {
53 struct mutex lock;
54 struct omap_display_platform_data *pdata;
55 struct platform_device *pdev;
Mythri P K95a8aeb2011-09-08 19:06:18 +053056 struct hdmi_ip_data ip_data;
Mythri P Kc3198a52011-03-12 12:04:27 +053057 int code;
58 int mode;
59 u8 edid[HDMI_EDID_MAX_LENGTH];
60 u8 edid_set;
61 bool custom_set;
62 struct hdmi_config cfg;
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +030063
64 struct clk *sys_clk;
Mythri P Kc3198a52011-03-12 12:04:27 +053065} hdmi;
66
67/*
68 * Logic for the below structure :
69 * user enters the CEA or VESA timings by specifying the HDMI/DVI code.
70 * There is a correspondence between CEA/VESA timing and code, please
71 * refer to section 6.3 in HDMI 1.3 specification for timing code.
72 *
73 * In the below structure, cea_vesa_timings corresponds to all OMAP4
74 * supported CEA and VESA timing values.code_cea corresponds to the CEA
75 * code, It is used to get the timing from cea_vesa_timing array.Similarly
76 * with code_vesa. Code_index is used for back mapping, that is once EDID
77 * is read from the TV, EDID is parsed to find the timing values and then
78 * map it to corresponding CEA or VESA index.
79 */
80
81static const struct hdmi_timings cea_vesa_timings[OMAP_HDMI_TIMINGS_NB] = {
82 { {640, 480, 25200, 96, 16, 48, 2, 10, 33} , 0 , 0},
83 { {1280, 720, 74250, 40, 440, 220, 5, 5, 20}, 1, 1},
84 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1},
85 { {720, 480, 27027, 62, 16, 60, 6, 9, 30}, 0, 0},
86 { {2880, 576, 108000, 256, 48, 272, 5, 5, 39}, 0, 0},
87 { {1440, 240, 27027, 124, 38, 114, 3, 4, 15}, 0, 0},
88 { {1440, 288, 27000, 126, 24, 138, 3, 2, 19}, 0, 0},
89 { {1920, 540, 74250, 44, 528, 148, 5, 2, 15}, 1, 1},
90 { {1920, 540, 74250, 44, 88, 148, 5, 2, 15}, 1, 1},
91 { {1920, 1080, 148500, 44, 88, 148, 5, 4, 36}, 1, 1},
92 { {720, 576, 27000, 64, 12, 68, 5, 5, 39}, 0, 0},
93 { {1440, 576, 54000, 128, 24, 136, 5, 5, 39}, 0, 0},
94 { {1920, 1080, 148500, 44, 528, 148, 5, 4, 36}, 1, 1},
95 { {2880, 480, 108108, 248, 64, 240, 6, 9, 30}, 0, 0},
96 { {1920, 1080, 74250, 44, 638, 148, 5, 4, 36}, 1, 1},
97 /* VESA From Here */
98 { {640, 480, 25175, 96, 16, 48, 2 , 11, 31}, 0, 0},
99 { {800, 600, 40000, 128, 40, 88, 4 , 1, 23}, 1, 1},
100 { {848, 480, 33750, 112, 16, 112, 8 , 6, 23}, 1, 1},
101 { {1280, 768, 79500, 128, 64, 192, 7 , 3, 20}, 1, 0},
102 { {1280, 800, 83500, 128, 72, 200, 6 , 3, 22}, 1, 0},
103 { {1360, 768, 85500, 112, 64, 256, 6 , 3, 18}, 1, 1},
104 { {1280, 960, 108000, 112, 96, 312, 3 , 1, 36}, 1, 1},
105 { {1280, 1024, 108000, 112, 48, 248, 3 , 1, 38}, 1, 1},
106 { {1024, 768, 65000, 136, 24, 160, 6, 3, 29}, 0, 0},
107 { {1400, 1050, 121750, 144, 88, 232, 4, 3, 32}, 1, 0},
108 { {1440, 900, 106500, 152, 80, 232, 6, 3, 25}, 1, 0},
109 { {1680, 1050, 146250, 176 , 104, 280, 6, 3, 30}, 1, 0},
110 { {1366, 768, 85500, 143, 70, 213, 3, 3, 24}, 1, 1},
111 { {1920, 1080, 148500, 44, 148, 80, 5, 4, 36}, 1, 1},
112 { {1280, 768, 68250, 32, 48, 80, 7, 3, 12}, 0, 1},
113 { {1400, 1050, 101000, 32, 48, 80, 4, 3, 23}, 0, 1},
114 { {1680, 1050, 119000, 32, 48, 80, 6, 3, 21}, 0, 1},
115 { {1280, 800, 79500, 32, 48, 80, 6, 3, 14}, 0, 1},
116 { {1280, 720, 74250, 40, 110, 220, 5, 5, 20}, 1, 1}
117};
118
119/*
120 * This is a static mapping array which maps the timing values
121 * with corresponding CEA / VESA code
122 */
123static const int code_index[OMAP_HDMI_TIMINGS_NB] = {
124 1, 19, 4, 2, 37, 6, 21, 20, 5, 16, 17, 29, 31, 35, 32,
125 /* <--15 CEA 17--> vesa*/
126 4, 9, 0xE, 0x17, 0x1C, 0x27, 0x20, 0x23, 0x10, 0x2A,
127 0X2F, 0x3A, 0X51, 0X52, 0x16, 0x29, 0x39, 0x1B
128};
129
130/*
131 * This is reverse static mapping which maps the CEA / VESA code
132 * to the corresponding timing values
133 */
134static const int code_cea[39] = {
135 -1, 0, 3, 3, 2, 8, 5, 5, -1, -1,
136 -1, -1, -1, -1, -1, -1, 9, 10, 10, 1,
137 7, 6, 6, -1, -1, -1, -1, -1, -1, 11,
138 11, 12, 14, -1, -1, 13, 13, 4, 4
139};
140
141static const int code_vesa[85] = {
142 -1, -1, -1, -1, 15, -1, -1, -1, -1, 16,
143 -1, -1, -1, -1, 17, -1, 23, -1, -1, -1,
144 -1, -1, 29, 18, -1, -1, -1, 32, 19, -1,
145 -1, -1, 21, -1, -1, 22, -1, -1, -1, 20,
146 -1, 30, 24, -1, -1, -1, -1, 25, -1, -1,
147 -1, -1, -1, -1, -1, -1, -1, 31, 26, -1,
148 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
149 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
150 -1, 27, 28, -1, 33};
151
152static const u8 edid_header[8] = {0x0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x0};
153
Mythri P K95a8aeb2011-09-08 19:06:18 +0530154static inline void hdmi_write_reg(void __iomem *base_addr,
155 const struct hdmi_reg idx, u32 val)
Mythri P Kc3198a52011-03-12 12:04:27 +0530156{
Mythri P K95a8aeb2011-09-08 19:06:18 +0530157 __raw_writel(val, base_addr + idx.idx);
Mythri P Kc3198a52011-03-12 12:04:27 +0530158}
159
Mythri P K95a8aeb2011-09-08 19:06:18 +0530160static inline u32 hdmi_read_reg(void __iomem *base_addr,
161 const struct hdmi_reg idx)
Mythri P Kc3198a52011-03-12 12:04:27 +0530162{
Mythri P K95a8aeb2011-09-08 19:06:18 +0530163 return __raw_readl(base_addr + idx.idx);
Mythri P Kc3198a52011-03-12 12:04:27 +0530164}
165
Mythri P K95a8aeb2011-09-08 19:06:18 +0530166static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
167{
168 return ip_data->base_wp;
169}
170
171static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
172{
173 return ip_data->base_wp + ip_data->phy_offset;
174}
175
176static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
177{
178 return ip_data->base_wp + ip_data->pll_offset;
179}
180
181static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
182{
183 return ip_data->base_wp + ip_data->core_av_offset;
184}
185
186static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
187{
188 return ip_data->base_wp + ip_data->core_sys_offset;
189}
190
191static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
192 const struct hdmi_reg idx,
Mythri P Kc3198a52011-03-12 12:04:27 +0530193 int b2, int b1, u32 val)
194{
195 u32 t = 0;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530196 while (val != REG_GET(base_addr, idx, b2, b1)) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530197 udelay(1);
198 if (t++ > 10000)
199 return !val;
200 }
201 return val;
202}
203
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300204static int hdmi_runtime_get(void)
205{
206 int r;
207
208 DSSDBG("hdmi_runtime_get\n");
209
210 r = pm_runtime_get_sync(&hdmi.pdev->dev);
211 WARN_ON(r < 0);
212 return r < 0 ? r : 0;
213}
214
215static void hdmi_runtime_put(void)
216{
217 int r;
218
219 DSSDBG("hdmi_runtime_put\n");
220
221 r = pm_runtime_put(&hdmi.pdev->dev);
222 WARN_ON(r < 0);
223}
224
Mythri P Kc3198a52011-03-12 12:04:27 +0530225int hdmi_init_display(struct omap_dss_device *dssdev)
226{
227 DSSDBG("init_display\n");
228
229 return 0;
230}
231
Mythri P K95a8aeb2011-09-08 19:06:18 +0530232static int hdmi_pll_init(struct hdmi_ip_data *ip_data,
233 enum hdmi_clk_refsel refsel, int dcofreq,
Mythri P Kc3198a52011-03-12 12:04:27 +0530234 struct hdmi_pll_info *fmt, u16 sd)
235{
236 u32 r;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530237 void __iomem *pll_base = hdmi_pll_base(ip_data);
Mythri P Kc3198a52011-03-12 12:04:27 +0530238
239 /* PLL start always use manual mode */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530240 REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530241
Mythri P K95a8aeb2011-09-08 19:06:18 +0530242 r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
Mythri P Kc3198a52011-03-12 12:04:27 +0530243 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
244 r = FLD_MOD(r, fmt->regn, 8, 1); /* CFG1_PLL_REGN */
245
Mythri P K95a8aeb2011-09-08 19:06:18 +0530246 hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
Mythri P Kc3198a52011-03-12 12:04:27 +0530247
Mythri P K95a8aeb2011-09-08 19:06:18 +0530248 r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
Mythri P Kc3198a52011-03-12 12:04:27 +0530249
250 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
251 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
252 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
253
254 if (dcofreq) {
255 /* divider programming for frequency beyond 1000Mhz */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530256 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, sd, 17, 10);
Mythri P Kc3198a52011-03-12 12:04:27 +0530257 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
258 } else {
259 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
260 }
261
Mythri P K95a8aeb2011-09-08 19:06:18 +0530262 hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
Mythri P Kc3198a52011-03-12 12:04:27 +0530263
Mythri P K95a8aeb2011-09-08 19:06:18 +0530264 r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
Mythri P Kc3198a52011-03-12 12:04:27 +0530265 r = FLD_MOD(r, fmt->regm2, 24, 18);
266 r = FLD_MOD(r, fmt->regmf, 17, 0);
267
Mythri P K95a8aeb2011-09-08 19:06:18 +0530268 hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
Mythri P Kc3198a52011-03-12 12:04:27 +0530269
270 /* go now */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530271 REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530272
273 /* wait for bit change */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530274 if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
275 0, 0, 1) != 1) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530276 DSSERR("PLL GO bit not set\n");
277 return -ETIMEDOUT;
278 }
279
280 /* Wait till the lock bit is set in PLL status */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530281 if (hdmi_wait_for_bit_change(pll_base,
282 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530283 DSSWARN("cannot lock PLL\n");
284 DSSWARN("CFG1 0x%x\n",
Mythri P K95a8aeb2011-09-08 19:06:18 +0530285 hdmi_read_reg(pll_base, PLLCTRL_CFG1));
Mythri P Kc3198a52011-03-12 12:04:27 +0530286 DSSWARN("CFG2 0x%x\n",
Mythri P K95a8aeb2011-09-08 19:06:18 +0530287 hdmi_read_reg(pll_base, PLLCTRL_CFG2));
Mythri P Kc3198a52011-03-12 12:04:27 +0530288 DSSWARN("CFG4 0x%x\n",
Mythri P K95a8aeb2011-09-08 19:06:18 +0530289 hdmi_read_reg(pll_base, PLLCTRL_CFG4));
Mythri P Kc3198a52011-03-12 12:04:27 +0530290 return -ETIMEDOUT;
291 }
292
293 DSSDBG("PLL locked!\n");
294
295 return 0;
296}
297
298/* PHY_PWR_CMD */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530299static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
Mythri P Kc3198a52011-03-12 12:04:27 +0530300{
301 /* Command for power control of HDMI PHY */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530302 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
Mythri P Kc3198a52011-03-12 12:04:27 +0530303
304 /* Status of the power control of HDMI PHY */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530305 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
306 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530307 DSSERR("Failed to set PHY power mode to %d\n", val);
308 return -ETIMEDOUT;
309 }
310
311 return 0;
312}
313
314/* PLL_PWR_CMD */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530315int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
Mythri P Kc3198a52011-03-12 12:04:27 +0530316{
317 /* Command for power control of HDMI PLL */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530318 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
Mythri P Kc3198a52011-03-12 12:04:27 +0530319
320 /* wait till PHY_PWR_STATUS is set */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530321 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
322 1, 0, val) != val) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530323 DSSERR("Failed to set PHY_PWR_STATUS\n");
324 return -ETIMEDOUT;
325 }
326
327 return 0;
328}
329
Mythri P K95a8aeb2011-09-08 19:06:18 +0530330static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
Mythri P Kc3198a52011-03-12 12:04:27 +0530331{
332 /* SYSRESET controlled by power FSM */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530333 REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
Mythri P Kc3198a52011-03-12 12:04:27 +0530334
335 /* READ 0x0 reset is in progress */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530336 if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
337 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530338 DSSERR("Failed to sysreset PLL\n");
339 return -ETIMEDOUT;
340 }
341
342 return 0;
343}
344
Mythri P K95a8aeb2011-09-08 19:06:18 +0530345static int hdmi_phy_init(struct hdmi_ip_data *ip_data)
Mythri P Kc3198a52011-03-12 12:04:27 +0530346{
347 u16 r = 0;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530348 void __iomem *phy_base = hdmi_phy_base(ip_data);
Mythri P Kc3198a52011-03-12 12:04:27 +0530349
Mythri P K95a8aeb2011-09-08 19:06:18 +0530350 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
Mythri P Kc3198a52011-03-12 12:04:27 +0530351 if (r)
352 return r;
353
Mythri P K95a8aeb2011-09-08 19:06:18 +0530354 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
Mythri P Kc3198a52011-03-12 12:04:27 +0530355 if (r)
356 return r;
357
358 /*
359 * Read address 0 in order to get the SCP reset done completed
360 * Dummy access performed to make sure reset is done
361 */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530362 hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
Mythri P Kc3198a52011-03-12 12:04:27 +0530363
364 /*
365 * Write to phy address 0 to configure the clock
366 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
367 */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530368 REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
Mythri P Kc3198a52011-03-12 12:04:27 +0530369
370 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530371 hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
Mythri P Kc3198a52011-03-12 12:04:27 +0530372
373 /* Setup max LDO voltage */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530374 REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530375
376 /* Write to phy address 3 to change the polarity control */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530377 REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
Mythri P Kc3198a52011-03-12 12:04:27 +0530378
379 return 0;
380}
381
Mythri P K95a8aeb2011-09-08 19:06:18 +0530382static int hdmi_pll_program(struct hdmi_ip_data *ip_data,
383 struct hdmi_pll_info *fmt)
Mythri P Kc3198a52011-03-12 12:04:27 +0530384{
385 u16 r = 0;
386 enum hdmi_clk_refsel refsel;
387
Mythri P K95a8aeb2011-09-08 19:06:18 +0530388 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
Mythri P Kc3198a52011-03-12 12:04:27 +0530389 if (r)
390 return r;
391
Mythri P K95a8aeb2011-09-08 19:06:18 +0530392 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
Mythri P Kc3198a52011-03-12 12:04:27 +0530393 if (r)
394 return r;
395
Mythri P K95a8aeb2011-09-08 19:06:18 +0530396 r = hdmi_pll_reset(ip_data);
Mythri P Kc3198a52011-03-12 12:04:27 +0530397 if (r)
398 return r;
399
400 refsel = HDMI_REFSEL_SYSCLK;
401
Mythri P K95a8aeb2011-09-08 19:06:18 +0530402 r = hdmi_pll_init(ip_data, refsel, fmt->dcofreq, fmt, fmt->regsd);
Mythri P Kc3198a52011-03-12 12:04:27 +0530403 if (r)
404 return r;
405
406 return 0;
407}
408
Mythri P K95a8aeb2011-09-08 19:06:18 +0530409static void hdmi_phy_off(struct hdmi_ip_data *ip_data)
Mythri P Kc3198a52011-03-12 12:04:27 +0530410{
Mythri P K95a8aeb2011-09-08 19:06:18 +0530411 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
Mythri P Kc3198a52011-03-12 12:04:27 +0530412}
413
Mythri P K95a8aeb2011-09-08 19:06:18 +0530414static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
415 u8 *pedid, int ext)
Mythri P Kc3198a52011-03-12 12:04:27 +0530416{
417 u32 i, j;
418 char checksum = 0;
419 u32 offset = 0;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530420 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
Mythri P Kc3198a52011-03-12 12:04:27 +0530421
422 /* Turn on CLK for DDC */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530423 REG_FLD_MOD(hdmi_av_base(ip_data), HDMI_CORE_AV_DPD, 0x7, 2, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530424
425 /*
426 * SW HACK : Without the Delay DDC(i2c bus) reads 0 values /
427 * right shifted values( The behavior is not consistent and seen only
428 * with some TV's)
429 */
430 usleep_range(800, 1000);
431
432 if (!ext) {
433 /* Clk SCL Devices */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530434 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530435
436 /* HDMI_CORE_DDC_STATUS_IN_PROG */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530437 if (hdmi_wait_for_bit_change(core_sys_base,
438 HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530439 DSSERR("Failed to program DDC\n");
440 return -ETIMEDOUT;
441 }
442
443 /* Clear FIFO */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530444 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530445
446 /* HDMI_CORE_DDC_STATUS_IN_PROG */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530447 if (hdmi_wait_for_bit_change(core_sys_base,
448 HDMI_CORE_DDC_STATUS, 4, 4, 0) != 0) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530449 DSSERR("Failed to program DDC\n");
450 return -ETIMEDOUT;
451 }
452
453 } else {
454 if (ext % 2 != 0)
455 offset = 0x80;
456 }
457
458 /* Load Segment Address Register */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530459 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_SEGM, ext/2, 7, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530460
461 /* Load Slave Address Register */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530462 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
Mythri P Kc3198a52011-03-12 12:04:27 +0530463
464 /* Load Offset Address Register */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530465 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530466
467 /* Load Byte Count */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530468 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
469 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530470
471 /* Set DDC_CMD */
472 if (ext)
Mythri P K95a8aeb2011-09-08 19:06:18 +0530473 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530474 else
Mythri P K95a8aeb2011-09-08 19:06:18 +0530475 REG_FLD_MOD(core_sys_base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530476
477 /* HDMI_CORE_DDC_STATUS_BUS_LOW */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530478 if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530479 DSSWARN("I2C Bus Low?\n");
480 return -EIO;
481 }
482 /* HDMI_CORE_DDC_STATUS_NO_ACK */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530483 if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530484 DSSWARN("I2C No Ack\n");
485 return -EIO;
486 }
487
488 i = ext * 128;
489 j = 0;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530490 while (((REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) ||
491 (REG_GET(core_sys_base,
492 HDMI_CORE_DDC_STATUS, 2, 2) == 0)) && j < 128) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530493
Mythri P K95a8aeb2011-09-08 19:06:18 +0530494 if (REG_GET(core_sys_base, HDMI_CORE_DDC_STATUS, 2, 2) == 0) {
Mythri P Kc3198a52011-03-12 12:04:27 +0530495 /* FIFO not empty */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530496 pedid[i++] = REG_GET(core_sys_base,
497 HDMI_CORE_DDC_DATA, 7, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530498 j++;
499 }
500 }
501
502 for (j = 0; j < 128; j++)
503 checksum += pedid[j];
504
505 if (checksum != 0) {
506 DSSERR("E-EDID checksum failed!!\n");
507 return -EIO;
508 }
509
510 return 0;
511}
512
Mythri P K95a8aeb2011-09-08 19:06:18 +0530513static int read_edid(struct hdmi_ip_data *ip_data, u8 *pedid, u16 max_length)
Mythri P Kc3198a52011-03-12 12:04:27 +0530514{
515 int r = 0, n = 0, i = 0;
516 int max_ext_blocks = (max_length / 128) - 1;
517
Mythri P K95a8aeb2011-09-08 19:06:18 +0530518 r = hdmi_core_ddc_edid(ip_data, pedid, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530519 if (r) {
520 return r;
521 } else {
522 n = pedid[0x7e];
523
524 /*
525 * README: need to comply with max_length set by the caller.
526 * Better implementation should be to allocate necessary
527 * memory to store EDID according to nb_block field found
528 * in first block
529 */
530 if (n > max_ext_blocks)
531 n = max_ext_blocks;
532
533 for (i = 1; i <= n; i++) {
Mythri P K95a8aeb2011-09-08 19:06:18 +0530534 r = hdmi_core_ddc_edid(ip_data, pedid, i);
Mythri P Kc3198a52011-03-12 12:04:27 +0530535 if (r)
536 return r;
537 }
538 }
539 return 0;
540}
541
542static int get_timings_index(void)
543{
544 int code;
545
546 if (hdmi.mode == 0)
547 code = code_vesa[hdmi.code];
548 else
549 code = code_cea[hdmi.code];
550
551 if (code == -1) {
552 /* HDMI code 4 corresponds to 640 * 480 VGA */
553 hdmi.code = 4;
554 /* DVI mode 1 corresponds to HDMI 0 to DVI */
555 hdmi.mode = HDMI_DVI;
556
557 code = code_vesa[hdmi.code];
558 }
559 return code;
560}
561
562static struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing)
563{
564 int i = 0, code = -1, temp_vsync = 0, temp_hsync = 0;
565 int timing_vsync = 0, timing_hsync = 0;
566 struct omap_video_timings temp;
567 struct hdmi_cm cm = {-1};
568 DSSDBG("hdmi_get_code\n");
569
570 for (i = 0; i < OMAP_HDMI_TIMINGS_NB; i++) {
571 temp = cea_vesa_timings[i].timings;
572 if ((temp.pixel_clock == timing->pixel_clock) &&
573 (temp.x_res == timing->x_res) &&
574 (temp.y_res == timing->y_res)) {
575
576 temp_hsync = temp.hfp + temp.hsw + temp.hbp;
577 timing_hsync = timing->hfp + timing->hsw + timing->hbp;
578 temp_vsync = temp.vfp + temp.vsw + temp.vbp;
579 timing_vsync = timing->vfp + timing->vsw + timing->vbp;
580
581 DSSDBG("temp_hsync = %d , temp_vsync = %d"
582 "timing_hsync = %d, timing_vsync = %d\n",
583 temp_hsync, temp_hsync,
584 timing_hsync, timing_vsync);
585
586 if ((temp_hsync == timing_hsync) &&
587 (temp_vsync == timing_vsync)) {
588 code = i;
589 cm.code = code_index[i];
590 if (code < 14)
591 cm.mode = HDMI_HDMI;
592 else
593 cm.mode = HDMI_DVI;
594 DSSDBG("Hdmi_code = %d mode = %d\n",
595 cm.code, cm.mode);
596 break;
597 }
598 }
599 }
600
601 return cm;
602}
603
604static void get_horz_vert_timing_info(int current_descriptor_addrs, u8 *edid ,
605 struct omap_video_timings *timings)
606{
607 /* X and Y resolution */
608 timings->x_res = (((edid[current_descriptor_addrs + 4] & 0xF0) << 4) |
609 edid[current_descriptor_addrs + 2]);
610 timings->y_res = (((edid[current_descriptor_addrs + 7] & 0xF0) << 4) |
611 edid[current_descriptor_addrs + 5]);
612
613 timings->pixel_clock = ((edid[current_descriptor_addrs + 1] << 8) |
614 edid[current_descriptor_addrs]);
615
616 timings->pixel_clock = 10 * timings->pixel_clock;
617
618 /* HORIZONTAL FRONT PORCH */
619 timings->hfp = edid[current_descriptor_addrs + 8] |
620 ((edid[current_descriptor_addrs + 11] & 0xc0) << 2);
621 /* HORIZONTAL SYNC WIDTH */
622 timings->hsw = edid[current_descriptor_addrs + 9] |
623 ((edid[current_descriptor_addrs + 11] & 0x30) << 4);
624 /* HORIZONTAL BACK PORCH */
625 timings->hbp = (((edid[current_descriptor_addrs + 4] & 0x0F) << 8) |
626 edid[current_descriptor_addrs + 3]) -
627 (timings->hfp + timings->hsw);
628 /* VERTICAL FRONT PORCH */
629 timings->vfp = ((edid[current_descriptor_addrs + 10] & 0xF0) >> 4) |
630 ((edid[current_descriptor_addrs + 11] & 0x0f) << 2);
631 /* VERTICAL SYNC WIDTH */
632 timings->vsw = (edid[current_descriptor_addrs + 10] & 0x0F) |
633 ((edid[current_descriptor_addrs + 11] & 0x03) << 4);
634 /* VERTICAL BACK PORCH */
635 timings->vbp = (((edid[current_descriptor_addrs + 7] & 0x0F) << 8) |
636 edid[current_descriptor_addrs + 6]) -
637 (timings->vfp + timings->vsw);
638
639}
640
641/* Description : This function gets the resolution information from EDID */
642static void get_edid_timing_data(u8 *edid)
643{
644 u8 count;
645 u16 current_descriptor_addrs;
646 struct hdmi_cm cm;
647 struct omap_video_timings edid_timings;
648
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300649 /* search block 0, there are 4 DTDs arranged in priority order */
Mythri P Kc3198a52011-03-12 12:04:27 +0530650 for (count = 0; count < EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR; count++) {
651 current_descriptor_addrs =
652 EDID_DESCRIPTOR_BLOCK0_ADDRESS +
653 count * EDID_TIMING_DESCRIPTOR_SIZE;
654 get_horz_vert_timing_info(current_descriptor_addrs,
655 edid, &edid_timings);
656 cm = hdmi_get_code(&edid_timings);
657 DSSDBG("Block0[%d] value matches code = %d , mode = %d\n",
658 count, cm.code, cm.mode);
659 if (cm.code == -1) {
660 continue;
661 } else {
662 hdmi.code = cm.code;
663 hdmi.mode = cm.mode;
664 DSSDBG("code = %d , mode = %d\n",
665 hdmi.code, hdmi.mode);
666 return;
667 }
668 }
669 if (edid[0x7e] != 0x00) {
670 for (count = 0; count < EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR;
671 count++) {
672 current_descriptor_addrs =
673 EDID_DESCRIPTOR_BLOCK1_ADDRESS +
674 count * EDID_TIMING_DESCRIPTOR_SIZE;
675 get_horz_vert_timing_info(current_descriptor_addrs,
676 edid, &edid_timings);
677 cm = hdmi_get_code(&edid_timings);
678 DSSDBG("Block1[%d] value matches code = %d, mode = %d",
679 count, cm.code, cm.mode);
680 if (cm.code == -1) {
681 continue;
682 } else {
683 hdmi.code = cm.code;
684 hdmi.mode = cm.mode;
685 DSSDBG("code = %d , mode = %d\n",
686 hdmi.code, hdmi.mode);
687 return;
688 }
689 }
690 }
691
692 DSSINFO("no valid timing found , falling back to VGA\n");
693 hdmi.code = 4; /* setting default value of 640 480 VGA */
694 hdmi.mode = HDMI_DVI;
695}
696
697static void hdmi_read_edid(struct omap_video_timings *dp)
698{
699 int ret = 0, code;
700
701 memset(hdmi.edid, 0, HDMI_EDID_MAX_LENGTH);
702
703 if (!hdmi.edid_set)
Mythri P K95a8aeb2011-09-08 19:06:18 +0530704 ret = read_edid(&hdmi.ip_data, hdmi.edid,
705 HDMI_EDID_MAX_LENGTH);
Mythri P Kc3198a52011-03-12 12:04:27 +0530706 if (!ret) {
707 if (!memcmp(hdmi.edid, edid_header, sizeof(edid_header))) {
708 /* search for timings of default resolution */
709 get_edid_timing_data(hdmi.edid);
710 hdmi.edid_set = true;
711 }
712 } else {
713 DSSWARN("failed to read E-EDID\n");
714 }
715
716 if (!hdmi.edid_set) {
717 DSSINFO("fallback to VGA\n");
718 hdmi.code = 4; /* setting default value of 640 480 VGA */
719 hdmi.mode = HDMI_DVI;
720 }
721
722 code = get_timings_index();
723
724 *dp = cea_vesa_timings[code].timings;
725}
726
727static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
728 struct hdmi_core_infoframe_avi *avi_cfg,
729 struct hdmi_core_packet_enable_repeat *repeat_cfg)
730{
731 DSSDBG("Enter hdmi_core_init\n");
732
733 /* video core */
734 video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
735 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
736 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
737 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
738 video_cfg->hdmi_dvi = HDMI_DVI;
739 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
740
741 /* info frame */
742 avi_cfg->db1_format = 0;
743 avi_cfg->db1_active_info = 0;
744 avi_cfg->db1_bar_info_dv = 0;
745 avi_cfg->db1_scan_info = 0;
746 avi_cfg->db2_colorimetry = 0;
747 avi_cfg->db2_aspect_ratio = 0;
748 avi_cfg->db2_active_fmt_ar = 0;
749 avi_cfg->db3_itc = 0;
750 avi_cfg->db3_ec = 0;
751 avi_cfg->db3_q_range = 0;
752 avi_cfg->db3_nup_scaling = 0;
753 avi_cfg->db4_videocode = 0;
754 avi_cfg->db5_pixel_repeat = 0;
755 avi_cfg->db6_7_line_eoftop = 0 ;
756 avi_cfg->db8_9_line_sofbottom = 0;
757 avi_cfg->db10_11_pixel_eofleft = 0;
758 avi_cfg->db12_13_pixel_sofright = 0;
759
760 /* packet enable and repeat */
761 repeat_cfg->audio_pkt = 0;
762 repeat_cfg->audio_pkt_repeat = 0;
763 repeat_cfg->avi_infoframe = 0;
764 repeat_cfg->avi_infoframe_repeat = 0;
765 repeat_cfg->gen_cntrl_pkt = 0;
766 repeat_cfg->gen_cntrl_pkt_repeat = 0;
767 repeat_cfg->generic_pkt = 0;
768 repeat_cfg->generic_pkt_repeat = 0;
769}
770
Mythri P K95a8aeb2011-09-08 19:06:18 +0530771static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
Mythri P Kc3198a52011-03-12 12:04:27 +0530772{
773 DSSDBG("Enter hdmi_core_powerdown_disable\n");
Mythri P K95a8aeb2011-09-08 19:06:18 +0530774 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530775}
776
Mythri P K95a8aeb2011-09-08 19:06:18 +0530777static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
Mythri P Kc3198a52011-03-12 12:04:27 +0530778{
779 DSSDBG("Enter hdmi_core_swreset_release\n");
Mythri P K95a8aeb2011-09-08 19:06:18 +0530780 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530781}
782
Mythri P K95a8aeb2011-09-08 19:06:18 +0530783static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
Mythri P Kc3198a52011-03-12 12:04:27 +0530784{
785 DSSDBG("Enter hdmi_core_swreset_assert\n");
Mythri P K95a8aeb2011-09-08 19:06:18 +0530786 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +0530787}
788
Mythri P K95a8aeb2011-09-08 19:06:18 +0530789/* HDMI_CORE_VIDEO_CONFIG */
790static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
791 struct hdmi_core_video_config *cfg)
Mythri P Kc3198a52011-03-12 12:04:27 +0530792{
793 u32 r = 0;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530794 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
Mythri P Kc3198a52011-03-12 12:04:27 +0530795
796 /* sys_ctrl1 default configuration not tunable */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530797 r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
Mythri P Kc3198a52011-03-12 12:04:27 +0530798 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
799 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
800 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
801 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
Mythri P K95a8aeb2011-09-08 19:06:18 +0530802 hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
Mythri P Kc3198a52011-03-12 12:04:27 +0530803
Mythri P K95a8aeb2011-09-08 19:06:18 +0530804 REG_FLD_MOD(core_sys_base,
805 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
Mythri P Kc3198a52011-03-12 12:04:27 +0530806
807 /* Vid_Mode */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530808 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
Mythri P Kc3198a52011-03-12 12:04:27 +0530809
810 /* dither truncation configuration */
811 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
812 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
813 r = FLD_MOD(r, 1, 5, 5);
814 } else {
815 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
816 r = FLD_MOD(r, 0, 5, 5);
817 }
Mythri P K95a8aeb2011-09-08 19:06:18 +0530818 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
Mythri P Kc3198a52011-03-12 12:04:27 +0530819
820 /* HDMI_Ctrl */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530821 r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
Mythri P Kc3198a52011-03-12 12:04:27 +0530822 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
823 r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
824 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
Mythri P K95a8aeb2011-09-08 19:06:18 +0530825 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
Mythri P Kc3198a52011-03-12 12:04:27 +0530826
827 /* TMDS_CTRL */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530828 REG_FLD_MOD(core_sys_base,
829 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
Mythri P Kc3198a52011-03-12 12:04:27 +0530830}
831
Mythri P K95a8aeb2011-09-08 19:06:18 +0530832static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data,
Mythri P Kc3198a52011-03-12 12:04:27 +0530833 struct hdmi_core_infoframe_avi info_avi)
834{
835 u32 val;
836 char sum = 0, checksum = 0;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530837 void __iomem *av_base = hdmi_av_base(ip_data);
Mythri P Kc3198a52011-03-12 12:04:27 +0530838
839 sum += 0x82 + 0x002 + 0x00D;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530840 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
841 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
842 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
Mythri P Kc3198a52011-03-12 12:04:27 +0530843
844 val = (info_avi.db1_format << 5) |
845 (info_avi.db1_active_info << 4) |
846 (info_avi.db1_bar_info_dv << 2) |
847 (info_avi.db1_scan_info);
Mythri P K95a8aeb2011-09-08 19:06:18 +0530848 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
Mythri P Kc3198a52011-03-12 12:04:27 +0530849 sum += val;
850
851 val = (info_avi.db2_colorimetry << 6) |
852 (info_avi.db2_aspect_ratio << 4) |
853 (info_avi.db2_active_fmt_ar);
Mythri P K95a8aeb2011-09-08 19:06:18 +0530854 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
Mythri P Kc3198a52011-03-12 12:04:27 +0530855 sum += val;
856
857 val = (info_avi.db3_itc << 7) |
858 (info_avi.db3_ec << 4) |
859 (info_avi.db3_q_range << 2) |
860 (info_avi.db3_nup_scaling);
Mythri P K95a8aeb2011-09-08 19:06:18 +0530861 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
Mythri P Kc3198a52011-03-12 12:04:27 +0530862 sum += val;
863
Mythri P K95a8aeb2011-09-08 19:06:18 +0530864 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
865 info_avi.db4_videocode);
Mythri P Kc3198a52011-03-12 12:04:27 +0530866 sum += info_avi.db4_videocode;
867
868 val = info_avi.db5_pixel_repeat;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530869 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
Mythri P Kc3198a52011-03-12 12:04:27 +0530870 sum += val;
871
872 val = info_avi.db6_7_line_eoftop & 0x00FF;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530873 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
Mythri P Kc3198a52011-03-12 12:04:27 +0530874 sum += val;
875
876 val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
Mythri P K95a8aeb2011-09-08 19:06:18 +0530877 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
Mythri P Kc3198a52011-03-12 12:04:27 +0530878 sum += val;
879
880 val = info_avi.db8_9_line_sofbottom & 0x00FF;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530881 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
Mythri P Kc3198a52011-03-12 12:04:27 +0530882 sum += val;
883
884 val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
Mythri P K95a8aeb2011-09-08 19:06:18 +0530885 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
Mythri P Kc3198a52011-03-12 12:04:27 +0530886 sum += val;
887
888 val = info_avi.db10_11_pixel_eofleft & 0x00FF;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530889 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
Mythri P Kc3198a52011-03-12 12:04:27 +0530890 sum += val;
891
892 val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
Mythri P K95a8aeb2011-09-08 19:06:18 +0530893 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
Mythri P Kc3198a52011-03-12 12:04:27 +0530894 sum += val;
895
896 val = info_avi.db12_13_pixel_sofright & 0x00FF;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530897 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
Mythri P Kc3198a52011-03-12 12:04:27 +0530898 sum += val;
899
900 val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
Mythri P K95a8aeb2011-09-08 19:06:18 +0530901 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
Mythri P Kc3198a52011-03-12 12:04:27 +0530902 sum += val;
903
904 checksum = 0x100 - sum;
Mythri P K95a8aeb2011-09-08 19:06:18 +0530905 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
Mythri P Kc3198a52011-03-12 12:04:27 +0530906}
907
Mythri P K95a8aeb2011-09-08 19:06:18 +0530908static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
Mythri P Kc3198a52011-03-12 12:04:27 +0530909 struct hdmi_core_packet_enable_repeat repeat_cfg)
910{
911 /* enable/repeat the infoframe */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530912 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
Mythri P Kc3198a52011-03-12 12:04:27 +0530913 (repeat_cfg.audio_pkt << 5) |
914 (repeat_cfg.audio_pkt_repeat << 4) |
915 (repeat_cfg.avi_infoframe << 1) |
916 (repeat_cfg.avi_infoframe_repeat));
917
918 /* enable/repeat the packet */
Mythri P K95a8aeb2011-09-08 19:06:18 +0530919 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
Mythri P Kc3198a52011-03-12 12:04:27 +0530920 (repeat_cfg.gen_cntrl_pkt << 3) |
921 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
922 (repeat_cfg.generic_pkt << 1) |
923 (repeat_cfg.generic_pkt_repeat));
924}
925
926static void hdmi_wp_init(struct omap_video_timings *timings,
927 struct hdmi_video_format *video_fmt,
928 struct hdmi_video_interface *video_int)
929{
930 DSSDBG("Enter hdmi_wp_init\n");
931
932 timings->hbp = 0;
933 timings->hfp = 0;
934 timings->hsw = 0;
935 timings->vbp = 0;
936 timings->vfp = 0;
937 timings->vsw = 0;
938
939 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
940 video_fmt->y_res = 0;
941 video_fmt->x_res = 0;
942
943 video_int->vsp = 0;
944 video_int->hsp = 0;
945
946 video_int->interlacing = 0;
947 video_int->tm = 0; /* HDMI_TIMING_SLAVE */
948
949}
950
Mythri P K95a8aeb2011-09-08 19:06:18 +0530951static void hdmi_wp_video_start(struct hdmi_ip_data *ip_data, bool start)
Mythri P Kc3198a52011-03-12 12:04:27 +0530952{
Mythri P K95a8aeb2011-09-08 19:06:18 +0530953 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31);
Mythri P Kc3198a52011-03-12 12:04:27 +0530954}
955
956static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
957 struct omap_video_timings *timings, struct hdmi_config *param)
958{
959 DSSDBG("Enter hdmi_wp_video_init_format\n");
960
961 video_fmt->y_res = param->timings.timings.y_res;
962 video_fmt->x_res = param->timings.timings.x_res;
963
964 timings->hbp = param->timings.timings.hbp;
965 timings->hfp = param->timings.timings.hfp;
966 timings->hsw = param->timings.timings.hsw;
967 timings->vbp = param->timings.timings.vbp;
968 timings->vfp = param->timings.timings.vfp;
969 timings->vsw = param->timings.timings.vsw;
970}
971
Mythri P K95a8aeb2011-09-08 19:06:18 +0530972static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
Mythri P Kc3198a52011-03-12 12:04:27 +0530973 struct hdmi_video_format *video_fmt)
974{
975 u32 l = 0;
976
Mythri P K95a8aeb2011-09-08 19:06:18 +0530977 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
978 video_fmt->packing_mode, 10, 8);
Mythri P Kc3198a52011-03-12 12:04:27 +0530979
980 l |= FLD_VAL(video_fmt->y_res, 31, 16);
981 l |= FLD_VAL(video_fmt->x_res, 15, 0);
Mythri P K95a8aeb2011-09-08 19:06:18 +0530982 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
Mythri P Kc3198a52011-03-12 12:04:27 +0530983}
984
Mythri P K95a8aeb2011-09-08 19:06:18 +0530985static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data,
Mythri P Kc3198a52011-03-12 12:04:27 +0530986 struct hdmi_video_interface *video_int)
987{
988 u32 r;
989 DSSDBG("Enter hdmi_wp_video_config_interface\n");
990
Mythri P K95a8aeb2011-09-08 19:06:18 +0530991 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
Mythri P Kc3198a52011-03-12 12:04:27 +0530992 r = FLD_MOD(r, video_int->vsp, 7, 7);
993 r = FLD_MOD(r, video_int->hsp, 6, 6);
994 r = FLD_MOD(r, video_int->interlacing, 3, 3);
995 r = FLD_MOD(r, video_int->tm, 1, 0);
Mythri P K95a8aeb2011-09-08 19:06:18 +0530996 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
Mythri P Kc3198a52011-03-12 12:04:27 +0530997}
998
Mythri P K95a8aeb2011-09-08 19:06:18 +0530999static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
Mythri P Kc3198a52011-03-12 12:04:27 +05301000 struct omap_video_timings *timings)
1001{
1002 u32 timing_h = 0;
1003 u32 timing_v = 0;
1004
1005 DSSDBG("Enter hdmi_wp_video_config_timing\n");
1006
1007 timing_h |= FLD_VAL(timings->hbp, 31, 20);
1008 timing_h |= FLD_VAL(timings->hfp, 19, 8);
1009 timing_h |= FLD_VAL(timings->hsw, 7, 0);
Mythri P K95a8aeb2011-09-08 19:06:18 +05301010 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
Mythri P Kc3198a52011-03-12 12:04:27 +05301011
1012 timing_v |= FLD_VAL(timings->vbp, 31, 20);
1013 timing_v |= FLD_VAL(timings->vfp, 19, 8);
1014 timing_v |= FLD_VAL(timings->vsw, 7, 0);
Mythri P K95a8aeb2011-09-08 19:06:18 +05301015 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
Mythri P Kc3198a52011-03-12 12:04:27 +05301016}
1017
Mythri P K95a8aeb2011-09-08 19:06:18 +05301018static void hdmi_basic_configure(struct hdmi_ip_data *ip_data,
1019 struct hdmi_config *cfg)
Mythri P Kc3198a52011-03-12 12:04:27 +05301020{
1021 /* HDMI */
1022 struct omap_video_timings video_timing;
1023 struct hdmi_video_format video_format;
1024 struct hdmi_video_interface video_interface;
1025 /* HDMI core */
1026 struct hdmi_core_infoframe_avi avi_cfg;
1027 struct hdmi_core_video_config v_core_cfg;
1028 struct hdmi_core_packet_enable_repeat repeat_cfg;
1029
1030 hdmi_wp_init(&video_timing, &video_format,
1031 &video_interface);
1032
1033 hdmi_core_init(&v_core_cfg,
1034 &avi_cfg,
1035 &repeat_cfg);
1036
1037 hdmi_wp_video_init_format(&video_format,
1038 &video_timing, cfg);
1039
Mythri P K95a8aeb2011-09-08 19:06:18 +05301040 hdmi_wp_video_config_timing(ip_data, &video_timing);
Mythri P Kc3198a52011-03-12 12:04:27 +05301041
1042 /* video config */
1043 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
1044
Mythri P K95a8aeb2011-09-08 19:06:18 +05301045 hdmi_wp_video_config_format(ip_data, &video_format);
Mythri P Kc3198a52011-03-12 12:04:27 +05301046
1047 video_interface.vsp = cfg->timings.vsync_pol;
1048 video_interface.hsp = cfg->timings.hsync_pol;
1049 video_interface.interlacing = cfg->interlace;
1050 video_interface.tm = 1 ; /* HDMI_TIMING_MASTER_24BIT */
1051
Mythri P K95a8aeb2011-09-08 19:06:18 +05301052 hdmi_wp_video_config_interface(ip_data, &video_interface);
Mythri P Kc3198a52011-03-12 12:04:27 +05301053
1054 /*
1055 * configure core video part
1056 * set software reset in the core
1057 */
Mythri P K95a8aeb2011-09-08 19:06:18 +05301058 hdmi_core_swreset_assert(ip_data);
Mythri P Kc3198a52011-03-12 12:04:27 +05301059
1060 /* power down off */
Mythri P K95a8aeb2011-09-08 19:06:18 +05301061 hdmi_core_powerdown_disable(ip_data);
Mythri P Kc3198a52011-03-12 12:04:27 +05301062
1063 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
1064 v_core_cfg.hdmi_dvi = cfg->cm.mode;
1065
Mythri P K95a8aeb2011-09-08 19:06:18 +05301066 hdmi_core_video_config(ip_data, &v_core_cfg);
Mythri P Kc3198a52011-03-12 12:04:27 +05301067
1068 /* release software reset in the core */
Mythri P K95a8aeb2011-09-08 19:06:18 +05301069 hdmi_core_swreset_release(ip_data);
Mythri P Kc3198a52011-03-12 12:04:27 +05301070
1071 /*
1072 * configure packet
1073 * info frame video see doc CEA861-D page 65
1074 */
1075 avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
1076 avi_cfg.db1_active_info =
1077 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
1078 avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
1079 avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
1080 avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
1081 avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
1082 avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
1083 avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
1084 avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
1085 avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
1086 avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
1087 avi_cfg.db4_videocode = cfg->cm.code;
1088 avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
1089 avi_cfg.db6_7_line_eoftop = 0;
1090 avi_cfg.db8_9_line_sofbottom = 0;
1091 avi_cfg.db10_11_pixel_eofleft = 0;
1092 avi_cfg.db12_13_pixel_sofright = 0;
1093
Mythri P K95a8aeb2011-09-08 19:06:18 +05301094 hdmi_core_aux_infoframe_avi_config(ip_data, avi_cfg);
Mythri P Kc3198a52011-03-12 12:04:27 +05301095
1096 /* enable/repeat the infoframe */
1097 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
1098 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
1099 /* wakeup */
1100 repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
1101 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
Mythri P K95a8aeb2011-09-08 19:06:18 +05301102 hdmi_core_av_packet_config(ip_data, repeat_cfg);
Mythri P Kc3198a52011-03-12 12:04:27 +05301103}
1104
1105static void update_hdmi_timings(struct hdmi_config *cfg,
1106 struct omap_video_timings *timings, int code)
1107{
1108 cfg->timings.timings.x_res = timings->x_res;
1109 cfg->timings.timings.y_res = timings->y_res;
1110 cfg->timings.timings.hbp = timings->hbp;
1111 cfg->timings.timings.hfp = timings->hfp;
1112 cfg->timings.timings.hsw = timings->hsw;
1113 cfg->timings.timings.vbp = timings->vbp;
1114 cfg->timings.timings.vfp = timings->vfp;
1115 cfg->timings.timings.vsw = timings->vsw;
1116 cfg->timings.timings.pixel_clock = timings->pixel_clock;
1117 cfg->timings.vsync_pol = cea_vesa_timings[code].vsync_pol;
1118 cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol;
1119}
1120
Archit Taneja6cb07b22011-04-12 13:52:25 +05301121static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
1122 struct hdmi_pll_info *pi)
Mythri P Kc3198a52011-03-12 12:04:27 +05301123{
Archit Taneja6cb07b22011-04-12 13:52:25 +05301124 unsigned long clkin, refclk;
Mythri P Kc3198a52011-03-12 12:04:27 +05301125 u32 mf;
1126
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001127 clkin = clk_get_rate(hdmi.sys_clk) / 10000;
Mythri P Kc3198a52011-03-12 12:04:27 +05301128 /*
1129 * Input clock is predivided by N + 1
1130 * out put of which is reference clk
1131 */
Archit Taneja6cb07b22011-04-12 13:52:25 +05301132 pi->regn = dssdev->clocks.hdmi.regn;
1133 refclk = clkin / (pi->regn + 1);
Mythri P Kc3198a52011-03-12 12:04:27 +05301134
1135 /*
1136 * multiplier is pixel_clk/ref_clk
1137 * Multiplying by 100 to avoid fractional part removal
1138 */
Archit Taneja6cb07b22011-04-12 13:52:25 +05301139 pi->regm = (phy * 100 / (refclk)) / 100;
1140 pi->regm2 = dssdev->clocks.hdmi.regm2;
Mythri P Kc3198a52011-03-12 12:04:27 +05301141
1142 /*
1143 * fractional multiplier is remainder of the difference between
1144 * multiplier and actual phy(required pixel clock thus should be
1145 * multiplied by 2^18(262144) divided by the reference clock
1146 */
1147 mf = (phy - pi->regm * refclk) * 262144;
Archit Taneja6cb07b22011-04-12 13:52:25 +05301148 pi->regmf = mf / (refclk);
Mythri P Kc3198a52011-03-12 12:04:27 +05301149
1150 /*
1151 * Dcofreq should be set to 1 if required pixel clock
1152 * is greater than 1000MHz
1153 */
1154 pi->dcofreq = phy > 1000 * 100;
Archit Taneja6cb07b22011-04-12 13:52:25 +05301155 pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10;
Mythri P Kc3198a52011-03-12 12:04:27 +05301156
1157 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
1158 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
1159}
1160
Mythri P Kc3198a52011-03-12 12:04:27 +05301161static int hdmi_power_on(struct omap_dss_device *dssdev)
1162{
1163 int r, code = 0;
1164 struct hdmi_pll_info pll_data;
1165 struct omap_video_timings *p;
Archit Taneja6cb07b22011-04-12 13:52:25 +05301166 unsigned long phy;
Mythri P Kc3198a52011-03-12 12:04:27 +05301167
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001168 r = hdmi_runtime_get();
1169 if (r)
1170 return r;
Mythri P Kc3198a52011-03-12 12:04:27 +05301171
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03001172 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +05301173
1174 p = &dssdev->panel.timings;
1175
1176 DSSDBG("hdmi_power_on x_res= %d y_res = %d\n",
1177 dssdev->panel.timings.x_res,
1178 dssdev->panel.timings.y_res);
1179
1180 if (!hdmi.custom_set) {
1181 DSSDBG("Read EDID as no EDID is not set on poweron\n");
1182 hdmi_read_edid(p);
1183 }
1184 code = get_timings_index();
1185 dssdev->panel.timings = cea_vesa_timings[code].timings;
1186 update_hdmi_timings(&hdmi.cfg, p, code);
1187
Mythri P Kc3198a52011-03-12 12:04:27 +05301188 phy = p->pixel_clock;
1189
Archit Taneja6cb07b22011-04-12 13:52:25 +05301190 hdmi_compute_pll(dssdev, phy, &pll_data);
Mythri P Kc3198a52011-03-12 12:04:27 +05301191
Mythri P K95a8aeb2011-09-08 19:06:18 +05301192 hdmi_wp_video_start(&hdmi.ip_data, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +05301193
Mythri P K95a8aeb2011-09-08 19:06:18 +05301194 /* config the PLL and PHY hdmi_set_pll_pwrfirst */
1195 r = hdmi_pll_program(&hdmi.ip_data, &pll_data);
Mythri P Kc3198a52011-03-12 12:04:27 +05301196 if (r) {
1197 DSSDBG("Failed to lock PLL\n");
1198 goto err;
1199 }
1200
Mythri P K95a8aeb2011-09-08 19:06:18 +05301201 r = hdmi_phy_init(&hdmi.ip_data);
Mythri P Kc3198a52011-03-12 12:04:27 +05301202 if (r) {
1203 DSSDBG("Failed to start PHY\n");
1204 goto err;
1205 }
1206
1207 hdmi.cfg.cm.mode = hdmi.mode;
1208 hdmi.cfg.cm.code = hdmi.code;
Mythri P K95a8aeb2011-09-08 19:06:18 +05301209 hdmi_basic_configure(&hdmi.ip_data, &hdmi.cfg);
Mythri P Kc3198a52011-03-12 12:04:27 +05301210
1211 /* Make selection of HDMI in DSS */
1212 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
1213
1214 /* Select the dispc clock source as PRCM clock, to ensure that it is not
1215 * DSI PLL source as the clock selected by DSI PLL might not be
1216 * sufficient for the resolution selected / that can be changed
1217 * dynamically by user. This can be moved to single location , say
1218 * Boardfile.
1219 */
Archit Taneja6cb07b22011-04-12 13:52:25 +05301220 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
Mythri P Kc3198a52011-03-12 12:04:27 +05301221
1222 /* bypass TV gamma table */
1223 dispc_enable_gamma_table(0);
1224
1225 /* tv size */
1226 dispc_set_digit_size(dssdev->panel.timings.x_res,
1227 dssdev->panel.timings.y_res);
1228
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03001229 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 1);
Mythri P Kc3198a52011-03-12 12:04:27 +05301230
Mythri P K95a8aeb2011-09-08 19:06:18 +05301231 hdmi_wp_video_start(&hdmi.ip_data, 1);
Mythri P Kc3198a52011-03-12 12:04:27 +05301232
1233 return 0;
1234err:
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001235 hdmi_runtime_put();
Mythri P Kc3198a52011-03-12 12:04:27 +05301236 return -EIO;
1237}
1238
1239static void hdmi_power_off(struct omap_dss_device *dssdev)
1240{
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03001241 dispc_mgr_enable(OMAP_DSS_CHANNEL_DIGIT, 0);
Mythri P Kc3198a52011-03-12 12:04:27 +05301242
Mythri P K95a8aeb2011-09-08 19:06:18 +05301243 hdmi_wp_video_start(&hdmi.ip_data, 0);
1244 hdmi_phy_off(&hdmi.ip_data);
1245 hdmi_set_pll_pwr(&hdmi.ip_data, HDMI_PLLPWRCMD_ALLOFF);
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001246 hdmi_runtime_put();
Mythri P Kc3198a52011-03-12 12:04:27 +05301247
1248 hdmi.edid_set = 0;
1249}
1250
1251int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev,
1252 struct omap_video_timings *timings)
1253{
1254 struct hdmi_cm cm;
1255
1256 cm = hdmi_get_code(timings);
1257 if (cm.code == -1) {
1258 DSSERR("Invalid timing entered\n");
1259 return -EINVAL;
1260 }
1261
1262 return 0;
1263
1264}
1265
1266void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev)
1267{
1268 struct hdmi_cm cm;
1269
1270 hdmi.custom_set = 1;
1271 cm = hdmi_get_code(&dssdev->panel.timings);
1272 hdmi.code = cm.code;
1273 hdmi.mode = cm.mode;
1274 omapdss_hdmi_display_enable(dssdev);
1275 hdmi.custom_set = 0;
1276}
1277
1278int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev)
1279{
1280 int r = 0;
1281
1282 DSSDBG("ENTER hdmi_display_enable\n");
1283
1284 mutex_lock(&hdmi.lock);
1285
Tomi Valkeinen05e1d602011-06-23 16:38:21 +03001286 if (dssdev->manager == NULL) {
1287 DSSERR("failed to enable display: no manager\n");
1288 r = -ENODEV;
1289 goto err0;
1290 }
1291
Mythri P Kc3198a52011-03-12 12:04:27 +05301292 r = omap_dss_start_device(dssdev);
1293 if (r) {
1294 DSSERR("failed to start device\n");
1295 goto err0;
1296 }
1297
1298 if (dssdev->platform_enable) {
1299 r = dssdev->platform_enable(dssdev);
1300 if (r) {
1301 DSSERR("failed to enable GPIO's\n");
1302 goto err1;
1303 }
1304 }
1305
1306 r = hdmi_power_on(dssdev);
1307 if (r) {
1308 DSSERR("failed to power on device\n");
1309 goto err2;
1310 }
1311
1312 mutex_unlock(&hdmi.lock);
1313 return 0;
1314
1315err2:
1316 if (dssdev->platform_disable)
1317 dssdev->platform_disable(dssdev);
1318err1:
1319 omap_dss_stop_device(dssdev);
1320err0:
1321 mutex_unlock(&hdmi.lock);
1322 return r;
1323}
1324
1325void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev)
1326{
1327 DSSDBG("Enter hdmi_display_disable\n");
1328
1329 mutex_lock(&hdmi.lock);
1330
1331 hdmi_power_off(dssdev);
1332
1333 if (dssdev->platform_disable)
1334 dssdev->platform_disable(dssdev);
1335
1336 omap_dss_stop_device(dssdev);
1337
1338 mutex_unlock(&hdmi.lock);
1339}
1340
Ricardo Neri82335c42011-04-05 16:05:18 -05001341#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1342 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
Mythri P K95a8aeb2011-09-08 19:06:18 +05301343static void hdmi_wp_audio_config_format(struct hdmi_ip_data *ip_data,
1344 struct hdmi_audio_format *aud_fmt)
Ricardo Neri82335c42011-04-05 16:05:18 -05001345{
1346 u32 r;
1347
1348 DSSDBG("Enter hdmi_wp_audio_config_format\n");
1349
Mythri P K95a8aeb2011-09-08 19:06:18 +05301350 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG);
Ricardo Neri82335c42011-04-05 16:05:18 -05001351 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
1352 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
1353 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
1354 r = FLD_MOD(r, aud_fmt->type, 4, 4);
1355 r = FLD_MOD(r, aud_fmt->justification, 3, 3);
1356 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
1357 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
1358 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
Mythri P K95a8aeb2011-09-08 19:06:18 +05301359 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r);
Ricardo Neri82335c42011-04-05 16:05:18 -05001360}
1361
Mythri P K95a8aeb2011-09-08 19:06:18 +05301362static void hdmi_wp_audio_config_dma(struct hdmi_ip_data *ip_data,
1363 struct hdmi_audio_dma *aud_dma)
Ricardo Neri82335c42011-04-05 16:05:18 -05001364{
1365 u32 r;
1366
1367 DSSDBG("Enter hdmi_wp_audio_config_dma\n");
1368
Mythri P K95a8aeb2011-09-08 19:06:18 +05301369 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2);
Ricardo Neri82335c42011-04-05 16:05:18 -05001370 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
1371 r = FLD_MOD(r, aud_dma->block_size, 7, 0);
Mythri P K95a8aeb2011-09-08 19:06:18 +05301372 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r);
Ricardo Neri82335c42011-04-05 16:05:18 -05001373
Mythri P K95a8aeb2011-09-08 19:06:18 +05301374 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL);
Ricardo Neri82335c42011-04-05 16:05:18 -05001375 r = FLD_MOD(r, aud_dma->mode, 9, 9);
1376 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
Mythri P K95a8aeb2011-09-08 19:06:18 +05301377 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r);
Ricardo Neri82335c42011-04-05 16:05:18 -05001378}
1379
Mythri P K95a8aeb2011-09-08 19:06:18 +05301380static void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
1381 struct hdmi_core_audio_config *cfg)
Ricardo Neri82335c42011-04-05 16:05:18 -05001382{
1383 u32 r;
Mythri P K95a8aeb2011-09-08 19:06:18 +05301384 void __iomem *av_base = hdmi_av_base(ip_data);
Ricardo Neri82335c42011-04-05 16:05:18 -05001385
1386 /* audio clock recovery parameters */
Mythri P K95a8aeb2011-09-08 19:06:18 +05301387 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
Ricardo Neri82335c42011-04-05 16:05:18 -05001388 r = FLD_MOD(r, cfg->use_mclk, 2, 2);
1389 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
1390 r = FLD_MOD(r, cfg->cts_mode, 0, 0);
Mythri P K95a8aeb2011-09-08 19:06:18 +05301391 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
Ricardo Neri82335c42011-04-05 16:05:18 -05001392
Mythri P K95a8aeb2011-09-08 19:06:18 +05301393 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
1394 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
1395 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
Ricardo Neri82335c42011-04-05 16:05:18 -05001396
1397 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
Mythri P K95a8aeb2011-09-08 19:06:18 +05301398 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
1399 REG_FLD_MOD(av_base,
1400 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
1401 REG_FLD_MOD(av_base,
1402 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
Ricardo Neri82335c42011-04-05 16:05:18 -05001403 } else {
1404 /*
1405 * HDMI IP uses this configuration to divide the MCLK to
1406 * update CTS value.
1407 */
Mythri P K95a8aeb2011-09-08 19:06:18 +05301408 REG_FLD_MOD(av_base,
1409 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
Ricardo Neri82335c42011-04-05 16:05:18 -05001410
1411 /* Configure clock for audio packets */
Mythri P K95a8aeb2011-09-08 19:06:18 +05301412 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
1413 cfg->aud_par_busclk, 7, 0);
1414 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
1415 (cfg->aud_par_busclk >> 8), 7, 0);
1416 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
1417 (cfg->aud_par_busclk >> 16), 7, 0);
Ricardo Neri82335c42011-04-05 16:05:18 -05001418 }
1419
1420 /* Override of SPDIF sample frequency with value in I2S_CHST4 */
Mythri P K95a8aeb2011-09-08 19:06:18 +05301421 REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
1422 cfg->fs_override, 1, 1);
Ricardo Neri82335c42011-04-05 16:05:18 -05001423
1424 /* I2S parameters */
Mythri P K95a8aeb2011-09-08 19:06:18 +05301425 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_CHST4,
1426 cfg->freq_sample, 3, 0);
Ricardo Neri82335c42011-04-05 16:05:18 -05001427
Mythri P K95a8aeb2011-09-08 19:06:18 +05301428 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
Ricardo Neri82335c42011-04-05 16:05:18 -05001429 r = FLD_MOD(r, cfg->i2s_cfg.en_high_bitrate_aud, 7, 7);
1430 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
1431 r = FLD_MOD(r, cfg->i2s_cfg.cbit_order, 5, 5);
1432 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
1433 r = FLD_MOD(r, cfg->i2s_cfg.ws_polarity, 3, 3);
1434 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
1435 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
1436 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
Mythri P K95a8aeb2011-09-08 19:06:18 +05301437 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
Ricardo Neri82335c42011-04-05 16:05:18 -05001438
Mythri P K95a8aeb2011-09-08 19:06:18 +05301439 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_CHST5);
Ricardo Neri82335c42011-04-05 16:05:18 -05001440 r = FLD_MOD(r, cfg->freq_sample, 7, 4);
1441 r = FLD_MOD(r, cfg->i2s_cfg.word_length, 3, 1);
1442 r = FLD_MOD(r, cfg->i2s_cfg.word_max_length, 0, 0);
Mythri P K95a8aeb2011-09-08 19:06:18 +05301443 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, r);
Ricardo Neri82335c42011-04-05 16:05:18 -05001444
Mythri P K95a8aeb2011-09-08 19:06:18 +05301445 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
1446 cfg->i2s_cfg.in_length_bits, 3, 0);
Ricardo Neri82335c42011-04-05 16:05:18 -05001447
1448 /* Audio channels and mode parameters */
Mythri P K95a8aeb2011-09-08 19:06:18 +05301449 REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
1450 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
Ricardo Neri82335c42011-04-05 16:05:18 -05001451 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
1452 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
1453 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
1454 r = FLD_MOD(r, cfg->en_spdif, 1, 1);
Mythri P K95a8aeb2011-09-08 19:06:18 +05301455 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
Ricardo Neri82335c42011-04-05 16:05:18 -05001456}
1457
Mythri P K95a8aeb2011-09-08 19:06:18 +05301458static void hdmi_core_audio_infoframe_config(struct hdmi_ip_data *ip_data,
Ricardo Neri82335c42011-04-05 16:05:18 -05001459 struct hdmi_core_infoframe_audio *info_aud)
1460{
1461 u8 val;
1462 u8 sum = 0, checksum = 0;
Mythri P K95a8aeb2011-09-08 19:06:18 +05301463 void __iomem *av_base = hdmi_av_base(ip_data);
Ricardo Neri82335c42011-04-05 16:05:18 -05001464
1465 /*
1466 * Set audio info frame type, version and length as
1467 * described in HDMI 1.4a Section 8.2.2 specification.
1468 * Checksum calculation is defined in Section 5.3.5.
1469 */
Mythri P K95a8aeb2011-09-08 19:06:18 +05301470 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
1471 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
1472 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
Ricardo Neri82335c42011-04-05 16:05:18 -05001473 sum += 0x84 + 0x001 + 0x00a;
1474
1475 val = (info_aud->db1_coding_type << 4)
1476 | (info_aud->db1_channel_count - 1);
Mythri P K95a8aeb2011-09-08 19:06:18 +05301477 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), val);
Ricardo Neri82335c42011-04-05 16:05:18 -05001478 sum += val;
1479
1480 val = (info_aud->db2_sample_freq << 2) | info_aud->db2_sample_size;
Mythri P K95a8aeb2011-09-08 19:06:18 +05301481 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), val);
Ricardo Neri82335c42011-04-05 16:05:18 -05001482 sum += val;
1483
Mythri P K95a8aeb2011-09-08 19:06:18 +05301484 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), 0x00);
Ricardo Neri82335c42011-04-05 16:05:18 -05001485
1486 val = info_aud->db4_channel_alloc;
Mythri P K95a8aeb2011-09-08 19:06:18 +05301487 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), val);
Ricardo Neri82335c42011-04-05 16:05:18 -05001488 sum += val;
1489
1490 val = (info_aud->db5_downmix_inh << 7) | (info_aud->db5_lsv << 3);
Mythri P K95a8aeb2011-09-08 19:06:18 +05301491 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), val);
Ricardo Neri82335c42011-04-05 16:05:18 -05001492 sum += val;
1493
Mythri P K95a8aeb2011-09-08 19:06:18 +05301494 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
1495 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
1496 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
1497 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
1498 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
Ricardo Neri82335c42011-04-05 16:05:18 -05001499
1500 checksum = 0x100 - sum;
Mythri P K95a8aeb2011-09-08 19:06:18 +05301501 hdmi_write_reg(av_base,
1502 HDMI_CORE_AV_AUDIO_CHSUM, checksum);
Ricardo Neri82335c42011-04-05 16:05:18 -05001503
1504 /*
1505 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
1506 * is available.
1507 */
1508}
1509
Mythri P K95a8aeb2011-09-08 19:06:18 +05301510static int hdmi_config_audio_acr(struct hdmi_ip_data *ip_data,
1511 u32 sample_freq, u32 *n, u32 *cts)
Ricardo Neri82335c42011-04-05 16:05:18 -05001512{
1513 u32 r;
1514 u32 deep_color = 0;
1515 u32 pclk = hdmi.cfg.timings.timings.pixel_clock;
1516
1517 if (n == NULL || cts == NULL)
1518 return -EINVAL;
1519 /*
1520 * Obtain current deep color configuration. This needed
1521 * to calculate the TMDS clock based on the pixel clock.
1522 */
Mythri P K95a8aeb2011-09-08 19:06:18 +05301523 r = REG_GET(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, 1, 0);
Ricardo Neri82335c42011-04-05 16:05:18 -05001524 switch (r) {
1525 case 1: /* No deep color selected */
1526 deep_color = 100;
1527 break;
1528 case 2: /* 10-bit deep color selected */
1529 deep_color = 125;
1530 break;
1531 case 3: /* 12-bit deep color selected */
1532 deep_color = 150;
1533 break;
1534 default:
1535 return -EINVAL;
1536 }
1537
1538 switch (sample_freq) {
1539 case 32000:
1540 if ((deep_color == 125) && ((pclk == 54054)
1541 || (pclk == 74250)))
1542 *n = 8192;
1543 else
1544 *n = 4096;
1545 break;
1546 case 44100:
1547 *n = 6272;
1548 break;
1549 case 48000:
1550 if ((deep_color == 125) && ((pclk == 54054)
1551 || (pclk == 74250)))
1552 *n = 8192;
1553 else
1554 *n = 6144;
1555 break;
1556 default:
1557 *n = 0;
1558 return -EINVAL;
1559 }
1560
1561 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
1562 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
1563
1564 return 0;
1565}
Ricardo Neriad44cc32011-05-18 22:31:56 -05001566
Mythri P K95a8aeb2011-09-08 19:06:18 +05301567static int hdmi_audio_hw_params(struct hdmi_ip_data *ip_data,
1568 struct snd_pcm_substream *substream,
Ricardo Neriad44cc32011-05-18 22:31:56 -05001569 struct snd_pcm_hw_params *params,
1570 struct snd_soc_dai *dai)
1571{
1572 struct hdmi_audio_format audio_format;
1573 struct hdmi_audio_dma audio_dma;
1574 struct hdmi_core_audio_config core_cfg;
1575 struct hdmi_core_infoframe_audio aud_if_cfg;
1576 int err, n, cts;
1577 enum hdmi_core_audio_sample_freq sample_freq;
1578
1579 switch (params_format(params)) {
1580 case SNDRV_PCM_FORMAT_S16_LE:
1581 core_cfg.i2s_cfg.word_max_length =
1582 HDMI_AUDIO_I2S_MAX_WORD_20BITS;
1583 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS;
1584 core_cfg.i2s_cfg.in_length_bits =
1585 HDMI_AUDIO_I2S_INPUT_LENGTH_16;
1586 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1587 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
1588 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
1589 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1590 audio_dma.transfer_size = 0x10;
1591 break;
1592 case SNDRV_PCM_FORMAT_S24_LE:
1593 core_cfg.i2s_cfg.word_max_length =
1594 HDMI_AUDIO_I2S_MAX_WORD_24BITS;
1595 core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS;
1596 core_cfg.i2s_cfg.in_length_bits =
1597 HDMI_AUDIO_I2S_INPUT_LENGTH_24;
1598 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
1599 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
1600 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1601 core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1602 audio_dma.transfer_size = 0x20;
1603 break;
1604 default:
1605 return -EINVAL;
1606 }
1607
1608 switch (params_rate(params)) {
1609 case 32000:
1610 sample_freq = HDMI_AUDIO_FS_32000;
1611 break;
1612 case 44100:
1613 sample_freq = HDMI_AUDIO_FS_44100;
1614 break;
1615 case 48000:
1616 sample_freq = HDMI_AUDIO_FS_48000;
1617 break;
1618 default:
1619 return -EINVAL;
1620 }
1621
Mythri P K95a8aeb2011-09-08 19:06:18 +05301622 err = hdmi_config_audio_acr(ip_data, params_rate(params), &n, &cts);
Ricardo Neriad44cc32011-05-18 22:31:56 -05001623 if (err < 0)
1624 return err;
1625
1626 /* Audio wrapper config */
1627 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
1628 audio_format.active_chnnls_msk = 0x03;
1629 audio_format.type = HDMI_AUDIO_TYPE_LPCM;
1630 audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
1631 /* Disable start/stop signals of IEC 60958 blocks */
1632 audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF;
1633
1634 audio_dma.block_size = 0xC0;
1635 audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
1636 audio_dma.fifo_threshold = 0x20; /* in number of samples */
1637
Mythri P K95a8aeb2011-09-08 19:06:18 +05301638 hdmi_wp_audio_config_dma(ip_data, &audio_dma);
1639 hdmi_wp_audio_config_format(ip_data, &audio_format);
Ricardo Neriad44cc32011-05-18 22:31:56 -05001640
1641 /*
1642 * I2S config
1643 */
1644 core_cfg.i2s_cfg.en_high_bitrate_aud = false;
1645 /* Only used with high bitrate audio */
1646 core_cfg.i2s_cfg.cbit_order = false;
1647 /* Serial data and word select should change on sck rising edge */
1648 core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
1649 core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
1650 /* Set I2S word select polarity */
1651 core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT;
1652 core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
1653 /* Set serial data to word select shift. See Phillips spec. */
1654 core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
1655 /* Enable one of the four available serial data channels */
1656 core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
1657
1658 /* Core audio config */
1659 core_cfg.freq_sample = sample_freq;
1660 core_cfg.n = n;
1661 core_cfg.cts = cts;
1662 if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
1663 core_cfg.aud_par_busclk = 0;
1664 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
1665 core_cfg.use_mclk = false;
1666 } else {
1667 core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
1668 core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
1669 core_cfg.use_mclk = true;
1670 core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
1671 }
1672 core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
1673 core_cfg.en_spdif = false;
1674 /* Use sample frequency from channel status word */
1675 core_cfg.fs_override = true;
1676 /* Enable ACR packets */
1677 core_cfg.en_acr_pkt = true;
1678 /* Disable direct streaming digital audio */
1679 core_cfg.en_dsd_audio = false;
1680 /* Use parallel audio interface */
1681 core_cfg.en_parallel_aud_input = true;
1682
Mythri P K95a8aeb2011-09-08 19:06:18 +05301683 hdmi_core_audio_config(ip_data, &core_cfg);
Ricardo Neriad44cc32011-05-18 22:31:56 -05001684
1685 /*
1686 * Configure packet
1687 * info frame audio see doc CEA861-D page 74
1688 */
1689 aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM;
1690 aud_if_cfg.db1_channel_count = 2;
1691 aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM;
1692 aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM;
1693 aud_if_cfg.db4_channel_alloc = 0x00;
1694 aud_if_cfg.db5_downmix_inh = false;
1695 aud_if_cfg.db5_lsv = 0;
1696
Mythri P K95a8aeb2011-09-08 19:06:18 +05301697 hdmi_core_audio_infoframe_config(ip_data, &aud_if_cfg);
Ricardo Neriad44cc32011-05-18 22:31:56 -05001698 return 0;
1699}
1700
Mythri P K95a8aeb2011-09-08 19:06:18 +05301701static int hdmi_audio_trigger(struct hdmi_ip_data *ip_data,
1702 struct snd_pcm_substream *substream, int cmd,
1703 struct snd_soc_dai *dai)
Ricardo Neriad44cc32011-05-18 22:31:56 -05001704{
1705 int err = 0;
1706 switch (cmd) {
1707 case SNDRV_PCM_TRIGGER_START:
1708 case SNDRV_PCM_TRIGGER_RESUME:
1709 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Mythri P K95a8aeb2011-09-08 19:06:18 +05301710 REG_FLD_MOD(hdmi_av_base(ip_data),
1711 HDMI_CORE_AV_AUD_MODE, 1, 0, 0);
1712 REG_FLD_MOD(hdmi_wp_base(ip_data),
1713 HDMI_WP_AUDIO_CTRL, 1, 31, 31);
1714 REG_FLD_MOD(hdmi_wp_base(ip_data),
1715 HDMI_WP_AUDIO_CTRL, 1, 30, 30);
Ricardo Neriad44cc32011-05-18 22:31:56 -05001716 break;
1717
1718 case SNDRV_PCM_TRIGGER_STOP:
1719 case SNDRV_PCM_TRIGGER_SUSPEND:
1720 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Mythri P K95a8aeb2011-09-08 19:06:18 +05301721 REG_FLD_MOD(hdmi_av_base(ip_data),
1722 HDMI_CORE_AV_AUD_MODE, 0, 0, 0);
1723 REG_FLD_MOD(hdmi_wp_base(ip_data),
1724 HDMI_WP_AUDIO_CTRL, 0, 30, 30);
1725 REG_FLD_MOD(hdmi_wp_base(ip_data),
1726 HDMI_WP_AUDIO_CTRL, 0, 31, 31);
Ricardo Neriad44cc32011-05-18 22:31:56 -05001727 break;
1728 default:
1729 err = -EINVAL;
1730 }
1731 return err;
1732}
1733
1734static int hdmi_audio_startup(struct snd_pcm_substream *substream,
1735 struct snd_soc_dai *dai)
1736{
1737 if (!hdmi.mode) {
1738 pr_err("Current video settings do not support audio.\n");
1739 return -EIO;
1740 }
1741 return 0;
1742}
1743
1744static struct snd_soc_codec_driver hdmi_audio_codec_drv = {
1745};
1746
1747static struct snd_soc_dai_ops hdmi_audio_codec_ops = {
1748 .hw_params = hdmi_audio_hw_params,
1749 .trigger = hdmi_audio_trigger,
1750 .startup = hdmi_audio_startup,
1751};
1752
1753static struct snd_soc_dai_driver hdmi_codec_dai_drv = {
1754 .name = "hdmi-audio-codec",
1755 .playback = {
1756 .channels_min = 2,
1757 .channels_max = 2,
1758 .rates = SNDRV_PCM_RATE_32000 |
1759 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
1760 .formats = SNDRV_PCM_FMTBIT_S16_LE |
1761 SNDRV_PCM_FMTBIT_S24_LE,
1762 },
1763 .ops = &hdmi_audio_codec_ops,
1764};
Ricardo Neri82335c42011-04-05 16:05:18 -05001765#endif
1766
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001767static int hdmi_get_clocks(struct platform_device *pdev)
1768{
1769 struct clk *clk;
1770
1771 clk = clk_get(&pdev->dev, "sys_clk");
1772 if (IS_ERR(clk)) {
1773 DSSERR("can't get sys_clk\n");
1774 return PTR_ERR(clk);
1775 }
1776
1777 hdmi.sys_clk = clk;
1778
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001779 return 0;
1780}
1781
1782static void hdmi_put_clocks(void)
1783{
1784 if (hdmi.sys_clk)
1785 clk_put(hdmi.sys_clk);
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001786}
1787
Mythri P Kc3198a52011-03-12 12:04:27 +05301788/* HDMI HW IP initialisation */
1789static int omapdss_hdmihw_probe(struct platform_device *pdev)
1790{
1791 struct resource *hdmi_mem;
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001792 int r;
Mythri P Kc3198a52011-03-12 12:04:27 +05301793
1794 hdmi.pdata = pdev->dev.platform_data;
1795 hdmi.pdev = pdev;
1796
1797 mutex_init(&hdmi.lock);
1798
1799 hdmi_mem = platform_get_resource(hdmi.pdev, IORESOURCE_MEM, 0);
1800 if (!hdmi_mem) {
1801 DSSERR("can't get IORESOURCE_MEM HDMI\n");
1802 return -EINVAL;
1803 }
1804
1805 /* Base address taken from platform */
Mythri P K95a8aeb2011-09-08 19:06:18 +05301806 hdmi.ip_data.base_wp = ioremap(hdmi_mem->start,
1807 resource_size(hdmi_mem));
1808 if (!hdmi.ip_data.base_wp) {
Mythri P Kc3198a52011-03-12 12:04:27 +05301809 DSSERR("can't ioremap WP\n");
1810 return -ENOMEM;
1811 }
1812
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001813 r = hdmi_get_clocks(pdev);
1814 if (r) {
Mythri P K95a8aeb2011-09-08 19:06:18 +05301815 iounmap(hdmi.ip_data.base_wp);
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001816 return r;
1817 }
1818
1819 pm_runtime_enable(&pdev->dev);
1820
Mythri P K95a8aeb2011-09-08 19:06:18 +05301821 hdmi.ip_data.core_sys_offset = HDMI_CORE_SYS;
1822 hdmi.ip_data.core_av_offset = HDMI_CORE_AV;
1823 hdmi.ip_data.pll_offset = HDMI_PLLCTRL;
1824 hdmi.ip_data.phy_offset = HDMI_PHY;
1825
Mythri P Kc3198a52011-03-12 12:04:27 +05301826 hdmi_panel_init();
1827
Ricardo Neriad44cc32011-05-18 22:31:56 -05001828#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1829 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
1830
1831 /* Register ASoC codec DAI */
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001832 r = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv,
Ricardo Neriad44cc32011-05-18 22:31:56 -05001833 &hdmi_codec_dai_drv, 1);
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001834 if (r) {
Ricardo Neriad44cc32011-05-18 22:31:56 -05001835 DSSERR("can't register ASoC HDMI audio codec\n");
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001836 return r;
Ricardo Neriad44cc32011-05-18 22:31:56 -05001837 }
1838#endif
Mythri P Kc3198a52011-03-12 12:04:27 +05301839 return 0;
1840}
1841
1842static int omapdss_hdmihw_remove(struct platform_device *pdev)
1843{
1844 hdmi_panel_exit();
1845
Ricardo Neriad44cc32011-05-18 22:31:56 -05001846#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1847 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
1848 snd_soc_unregister_codec(&pdev->dev);
1849#endif
1850
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001851 pm_runtime_disable(&pdev->dev);
1852
1853 hdmi_put_clocks();
1854
Mythri P K95a8aeb2011-09-08 19:06:18 +05301855 iounmap(hdmi.ip_data.base_wp);
Mythri P Kc3198a52011-03-12 12:04:27 +05301856
1857 return 0;
1858}
1859
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001860static int hdmi_runtime_suspend(struct device *dev)
1861{
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001862 clk_disable(hdmi.sys_clk);
1863
1864 dispc_runtime_put();
1865 dss_runtime_put();
1866
1867 return 0;
1868}
1869
1870static int hdmi_runtime_resume(struct device *dev)
1871{
1872 int r;
1873
1874 r = dss_runtime_get();
1875 if (r < 0)
1876 goto err_get_dss;
1877
1878 r = dispc_runtime_get();
1879 if (r < 0)
1880 goto err_get_dispc;
1881
1882
1883 clk_enable(hdmi.sys_clk);
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001884
1885 return 0;
1886
1887err_get_dispc:
1888 dss_runtime_put();
1889err_get_dss:
1890 return r;
1891}
1892
1893static const struct dev_pm_ops hdmi_pm_ops = {
1894 .runtime_suspend = hdmi_runtime_suspend,
1895 .runtime_resume = hdmi_runtime_resume,
1896};
1897
Mythri P Kc3198a52011-03-12 12:04:27 +05301898static struct platform_driver omapdss_hdmihw_driver = {
1899 .probe = omapdss_hdmihw_probe,
1900 .remove = omapdss_hdmihw_remove,
1901 .driver = {
1902 .name = "omapdss_hdmi",
1903 .owner = THIS_MODULE,
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03001904 .pm = &hdmi_pm_ops,
Mythri P Kc3198a52011-03-12 12:04:27 +05301905 },
1906};
1907
1908int hdmi_init_platform_driver(void)
1909{
1910 return platform_driver_register(&omapdss_hdmihw_driver);
1911}
1912
1913void hdmi_uninit_platform_driver(void)
1914{
1915 return platform_driver_unregister(&omapdss_hdmihw_driver);
1916}