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Fabio Estevamacd70ba2018-05-23 16:17:36 -03001// SPDX-License-Identifier: GPL-2.0
2//
3// Regulator Driver for Freescale MC13783 PMIC
4//
5// Copyright 2010 Yong Shen <yong.shen@linaro.org>
6// Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7// Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
Sascha Hauer295c08b2009-08-19 01:43:50 +02008
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +01009#include <linux/mfd/mc13783.h>
Sascha Hauer295c08b2009-08-19 01:43:50 +020010#include <linux/regulator/machine.h>
11#include <linux/regulator/driver.h>
12#include <linux/platform_device.h>
Sascha Hauer295c08b2009-08-19 01:43:50 +020013#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090014#include <linux/slab.h>
Sascha Hauer295c08b2009-08-19 01:43:50 +020015#include <linux/init.h>
16#include <linux/err.h>
Paul Gortmaker65602c32011-07-17 16:28:23 -040017#include <linux/module.h>
Yong Shen167e3d82010-12-14 14:00:54 +080018#include "mc13xxx.h"
Sascha Hauer295c08b2009-08-19 01:43:50 +020019
Gaëtan Carlierba02dfd2012-08-28 13:09:10 +020020#define MC13783_REG_SWITCHERS0 24
21/* Enable does not exist for SW1A */
22#define MC13783_REG_SWITCHERS0_SW1AEN 0
23#define MC13783_REG_SWITCHERS0_SW1AVSEL 0
24#define MC13783_REG_SWITCHERS0_SW1AVSEL_M (63 << 0)
25
26#define MC13783_REG_SWITCHERS1 25
27/* Enable does not exist for SW1B */
28#define MC13783_REG_SWITCHERS1_SW1BEN 0
29#define MC13783_REG_SWITCHERS1_SW1BVSEL 0
30#define MC13783_REG_SWITCHERS1_SW1BVSEL_M (63 << 0)
31
32#define MC13783_REG_SWITCHERS2 26
33/* Enable does not exist for SW2A */
34#define MC13783_REG_SWITCHERS2_SW2AEN 0
35#define MC13783_REG_SWITCHERS2_SW2AVSEL 0
36#define MC13783_REG_SWITCHERS2_SW2AVSEL_M (63 << 0)
37
38#define MC13783_REG_SWITCHERS3 27
39/* Enable does not exist for SW2B */
40#define MC13783_REG_SWITCHERS3_SW2BEN 0
41#define MC13783_REG_SWITCHERS3_SW2BVSEL 0
42#define MC13783_REG_SWITCHERS3_SW2BVSEL_M (63 << 0)
43
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +010044#define MC13783_REG_SWITCHERS5 29
45#define MC13783_REG_SWITCHERS5_SW3EN (1 << 20)
Alberto Panizzo1bd588f2009-12-14 18:26:38 +010046#define MC13783_REG_SWITCHERS5_SW3VSEL 18
47#define MC13783_REG_SWITCHERS5_SW3VSEL_M (3 << 18)
48
49#define MC13783_REG_REGULATORSETTING0 30
50#define MC13783_REG_REGULATORSETTING0_VIOLOVSEL 2
51#define MC13783_REG_REGULATORSETTING0_VDIGVSEL 4
52#define MC13783_REG_REGULATORSETTING0_VGENVSEL 6
53#define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL 9
54#define MC13783_REG_REGULATORSETTING0_VRFREFVSEL 11
55#define MC13783_REG_REGULATORSETTING0_VRFCPVSEL 13
56#define MC13783_REG_REGULATORSETTING0_VSIMVSEL 14
57#define MC13783_REG_REGULATORSETTING0_VESIMVSEL 15
58#define MC13783_REG_REGULATORSETTING0_VCAMVSEL 16
59
60#define MC13783_REG_REGULATORSETTING0_VIOLOVSEL_M (3 << 2)
61#define MC13783_REG_REGULATORSETTING0_VDIGVSEL_M (3 << 4)
62#define MC13783_REG_REGULATORSETTING0_VGENVSEL_M (7 << 6)
63#define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL_M (3 << 9)
64#define MC13783_REG_REGULATORSETTING0_VRFREFVSEL_M (3 << 11)
65#define MC13783_REG_REGULATORSETTING0_VRFCPVSEL_M (1 << 13)
66#define MC13783_REG_REGULATORSETTING0_VSIMVSEL_M (1 << 14)
67#define MC13783_REG_REGULATORSETTING0_VESIMVSEL_M (1 << 15)
68#define MC13783_REG_REGULATORSETTING0_VCAMVSEL_M (7 << 16)
69
70#define MC13783_REG_REGULATORSETTING1 31
71#define MC13783_REG_REGULATORSETTING1_VVIBVSEL 0
72#define MC13783_REG_REGULATORSETTING1_VRF1VSEL 2
73#define MC13783_REG_REGULATORSETTING1_VRF2VSEL 4
74#define MC13783_REG_REGULATORSETTING1_VMMC1VSEL 6
75#define MC13783_REG_REGULATORSETTING1_VMMC2VSEL 9
76
77#define MC13783_REG_REGULATORSETTING1_VVIBVSEL_M (3 << 0)
78#define MC13783_REG_REGULATORSETTING1_VRF1VSEL_M (3 << 2)
79#define MC13783_REG_REGULATORSETTING1_VRF2VSEL_M (3 << 4)
80#define MC13783_REG_REGULATORSETTING1_VMMC1VSEL_M (7 << 6)
81#define MC13783_REG_REGULATORSETTING1_VMMC2VSEL_M (7 << 9)
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +010082
83#define MC13783_REG_REGULATORMODE0 32
84#define MC13783_REG_REGULATORMODE0_VAUDIOEN (1 << 0)
85#define MC13783_REG_REGULATORMODE0_VIOHIEN (1 << 3)
86#define MC13783_REG_REGULATORMODE0_VIOLOEN (1 << 6)
87#define MC13783_REG_REGULATORMODE0_VDIGEN (1 << 9)
88#define MC13783_REG_REGULATORMODE0_VGENEN (1 << 12)
89#define MC13783_REG_REGULATORMODE0_VRFDIGEN (1 << 15)
90#define MC13783_REG_REGULATORMODE0_VRFREFEN (1 << 18)
91#define MC13783_REG_REGULATORMODE0_VRFCPEN (1 << 21)
92
93#define MC13783_REG_REGULATORMODE1 33
94#define MC13783_REG_REGULATORMODE1_VSIMEN (1 << 0)
95#define MC13783_REG_REGULATORMODE1_VESIMEN (1 << 3)
96#define MC13783_REG_REGULATORMODE1_VCAMEN (1 << 6)
97#define MC13783_REG_REGULATORMODE1_VRFBGEN (1 << 9)
98#define MC13783_REG_REGULATORMODE1_VVIBEN (1 << 11)
99#define MC13783_REG_REGULATORMODE1_VRF1EN (1 << 12)
100#define MC13783_REG_REGULATORMODE1_VRF2EN (1 << 15)
101#define MC13783_REG_REGULATORMODE1_VMMC1EN (1 << 18)
102#define MC13783_REG_REGULATORMODE1_VMMC2EN (1 << 21)
103
104#define MC13783_REG_POWERMISC 34
105#define MC13783_REG_POWERMISC_GPO1EN (1 << 6)
106#define MC13783_REG_POWERMISC_GPO2EN (1 << 8)
107#define MC13783_REG_POWERMISC_GPO3EN (1 << 10)
108#define MC13783_REG_POWERMISC_GPO4EN (1 << 12)
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100109#define MC13783_REG_POWERMISC_PWGT1SPIEN (1 << 15)
110#define MC13783_REG_POWERMISC_PWGT2SPIEN (1 << 16)
111
112#define MC13783_REG_POWERMISC_PWGTSPI_M (3 << 15)
113
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +0100114
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100115/* Voltage Values */
Gaëtan Carlierba02dfd2012-08-28 13:09:10 +0200116static const int mc13783_sw1x_val[] = {
117 900000, 925000, 950000, 975000,
118 1000000, 1025000, 1050000, 1075000,
119 1100000, 1125000, 1150000, 1175000,
120 1200000, 1225000, 1250000, 1275000,
121 1300000, 1325000, 1350000, 1375000,
122 1400000, 1425000, 1450000, 1475000,
123 1500000, 1525000, 1550000, 1575000,
124 1600000, 1625000, 1650000, 1675000,
125 1700000, 1700000, 1700000, 1700000,
126 1800000, 1800000, 1800000, 1800000,
127 1850000, 1850000, 1850000, 1850000,
128 2000000, 2000000, 2000000, 2000000,
129 2100000, 2100000, 2100000, 2100000,
130 2200000, 2200000, 2200000, 2200000,
131 2200000, 2200000, 2200000, 2200000,
132 2200000, 2200000, 2200000, 2200000,
133};
134
135static const int mc13783_sw2x_val[] = {
136 900000, 925000, 950000, 975000,
137 1000000, 1025000, 1050000, 1075000,
138 1100000, 1125000, 1150000, 1175000,
139 1200000, 1225000, 1250000, 1275000,
140 1300000, 1325000, 1350000, 1375000,
141 1400000, 1425000, 1450000, 1475000,
142 1500000, 1525000, 1550000, 1575000,
143 1600000, 1625000, 1650000, 1675000,
144 1700000, 1700000, 1700000, 1700000,
145 1800000, 1800000, 1800000, 1800000,
146 1900000, 1900000, 1900000, 1900000,
147 2000000, 2000000, 2000000, 2000000,
148 2100000, 2100000, 2100000, 2100000,
149 2200000, 2200000, 2200000, 2200000,
150 2200000, 2200000, 2200000, 2200000,
151 2200000, 2200000, 2200000, 2200000,
152};
153
Axel Lin34e74f32012-06-08 15:41:48 +0800154static const unsigned int mc13783_sw3_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100155 5000000, 5000000, 5000000, 5500000,
156};
157
Axel Lin34e74f32012-06-08 15:41:48 +0800158static const unsigned int mc13783_vaudio_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100159 2775000,
160};
161
Axel Lin34e74f32012-06-08 15:41:48 +0800162static const unsigned int mc13783_viohi_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100163 2775000,
164};
165
Axel Lin34e74f32012-06-08 15:41:48 +0800166static const unsigned int mc13783_violo_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100167 1200000, 1300000, 1500000, 1800000,
168};
169
Axel Lin34e74f32012-06-08 15:41:48 +0800170static const unsigned int mc13783_vdig_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100171 1200000, 1300000, 1500000, 1800000,
172};
173
Axel Lin34e74f32012-06-08 15:41:48 +0800174static const unsigned int mc13783_vgen_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100175 1200000, 1300000, 1500000, 1800000,
176 1100000, 2000000, 2775000, 2400000,
177};
178
Axel Lin34e74f32012-06-08 15:41:48 +0800179static const unsigned int mc13783_vrfdig_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100180 1200000, 1500000, 1800000, 1875000,
181};
182
Axel Lin34e74f32012-06-08 15:41:48 +0800183static const unsigned int mc13783_vrfref_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100184 2475000, 2600000, 2700000, 2775000,
185};
186
Axel Lin34e74f32012-06-08 15:41:48 +0800187static const unsigned int mc13783_vrfcp_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100188 2700000, 2775000,
189};
190
Axel Lin34e74f32012-06-08 15:41:48 +0800191static const unsigned int mc13783_vsim_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100192 1800000, 2900000, 3000000,
193};
194
Axel Lin34e74f32012-06-08 15:41:48 +0800195static const unsigned int mc13783_vesim_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100196 1800000, 2900000,
197};
198
Axel Lin34e74f32012-06-08 15:41:48 +0800199static const unsigned int mc13783_vcam_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100200 1500000, 1800000, 2500000, 2550000,
201 2600000, 2750000, 2800000, 3000000,
202};
203
Axel Lin34e74f32012-06-08 15:41:48 +0800204static const unsigned int mc13783_vrfbg_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100205 1250000,
206};
207
Axel Lin34e74f32012-06-08 15:41:48 +0800208static const unsigned int mc13783_vvib_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100209 1300000, 1800000, 2000000, 3000000,
210};
211
Axel Lin34e74f32012-06-08 15:41:48 +0800212static const unsigned int mc13783_vmmc_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100213 1600000, 1800000, 2000000, 2600000,
214 2700000, 2800000, 2900000, 3000000,
215};
216
Axel Lin34e74f32012-06-08 15:41:48 +0800217static const unsigned int mc13783_vrf_val[] = {
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100218 1500000, 1875000, 2700000, 2775000,
Sascha Hauer295c08b2009-08-19 01:43:50 +0200219};
220
Axel Lin34e74f32012-06-08 15:41:48 +0800221static const unsigned int mc13783_gpo_val[] = {
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100222 3100000,
223};
224
Axel Lin34e74f32012-06-08 15:41:48 +0800225static const unsigned int mc13783_pwgtdrv_val[] = {
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100226 5500000,
227};
228
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100229static struct regulator_ops mc13783_gpo_regulator_ops;
Sascha Hauer295c08b2009-08-19 01:43:50 +0200230
Yong Shen167e3d82010-12-14 14:00:54 +0800231#define MC13783_DEFINE(prefix, name, reg, vsel_reg, voltages) \
232 MC13xxx_DEFINE(MC13783_REG_, name, reg, vsel_reg, voltages, \
233 mc13xxx_regulator_ops)
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100234
Yong Shen167e3d82010-12-14 14:00:54 +0800235#define MC13783_FIXED_DEFINE(prefix, name, reg, voltages) \
236 MC13xxx_FIXED_DEFINE(MC13783_REG_, name, reg, voltages, \
237 mc13xxx_fixed_regulator_ops)
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100238
Yong Shen167e3d82010-12-14 14:00:54 +0800239#define MC13783_GPO_DEFINE(prefix, name, reg, voltages) \
240 MC13xxx_GPO_DEFINE(MC13783_REG_, name, reg, voltages, \
241 mc13783_gpo_regulator_ops)
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +0100242
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100243#define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages) \
Yong Shen57c78e32010-12-14 14:00:53 +0800244 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100245#define MC13783_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages) \
Yong Shen57c78e32010-12-14 14:00:53 +0800246 MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages)
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +0100247
Yong Shen167e3d82010-12-14 14:00:54 +0800248static struct mc13xxx_regulator mc13783_regulators[] = {
Gaëtan Carlierba02dfd2012-08-28 13:09:10 +0200249 MC13783_DEFINE_SW(SW1A, SWITCHERS0, SWITCHERS0, mc13783_sw1x_val),
250 MC13783_DEFINE_SW(SW1B, SWITCHERS1, SWITCHERS1, mc13783_sw1x_val),
251 MC13783_DEFINE_SW(SW2A, SWITCHERS2, SWITCHERS2, mc13783_sw2x_val),
252 MC13783_DEFINE_SW(SW2B, SWITCHERS3, SWITCHERS3, mc13783_sw2x_val),
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100253 MC13783_DEFINE_SW(SW3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val),
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +0100254
Yong Shen57c78e32010-12-14 14:00:53 +0800255 MC13783_FIXED_DEFINE(REG, VAUDIO, REGULATORMODE0, mc13783_vaudio_val),
256 MC13783_FIXED_DEFINE(REG, VIOHI, REGULATORMODE0, mc13783_viohi_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900257 MC13783_DEFINE_REGU(VIOLO, REGULATORMODE0, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100258 mc13783_violo_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900259 MC13783_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100260 mc13783_vdig_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900261 MC13783_DEFINE_REGU(VGEN, REGULATORMODE0, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100262 mc13783_vgen_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900263 MC13783_DEFINE_REGU(VRFDIG, REGULATORMODE0, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100264 mc13783_vrfdig_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900265 MC13783_DEFINE_REGU(VRFREF, REGULATORMODE0, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100266 mc13783_vrfref_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900267 MC13783_DEFINE_REGU(VRFCP, REGULATORMODE0, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100268 mc13783_vrfcp_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900269 MC13783_DEFINE_REGU(VSIM, REGULATORMODE1, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100270 mc13783_vsim_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900271 MC13783_DEFINE_REGU(VESIM, REGULATORMODE1, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100272 mc13783_vesim_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900273 MC13783_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100274 mc13783_vcam_val),
Yong Shen57c78e32010-12-14 14:00:53 +0800275 MC13783_FIXED_DEFINE(REG, VRFBG, REGULATORMODE1, mc13783_vrfbg_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900276 MC13783_DEFINE_REGU(VVIB, REGULATORMODE1, REGULATORSETTING1,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100277 mc13783_vvib_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900278 MC13783_DEFINE_REGU(VRF1, REGULATORMODE1, REGULATORSETTING1,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100279 mc13783_vrf_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900280 MC13783_DEFINE_REGU(VRF2, REGULATORMODE1, REGULATORSETTING1,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100281 mc13783_vrf_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900282 MC13783_DEFINE_REGU(VMMC1, REGULATORMODE1, REGULATORSETTING1,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100283 mc13783_vmmc_val),
Jingoo Han6e044c32013-10-14 17:49:55 +0900284 MC13783_DEFINE_REGU(VMMC2, REGULATORMODE1, REGULATORSETTING1,
Alberto Panizzo1bd588f2009-12-14 18:26:38 +0100285 mc13783_vmmc_val),
Yong Shen57c78e32010-12-14 14:00:53 +0800286 MC13783_GPO_DEFINE(REG, GPO1, POWERMISC, mc13783_gpo_val),
287 MC13783_GPO_DEFINE(REG, GPO2, POWERMISC, mc13783_gpo_val),
288 MC13783_GPO_DEFINE(REG, GPO3, POWERMISC, mc13783_gpo_val),
289 MC13783_GPO_DEFINE(REG, GPO4, POWERMISC, mc13783_gpo_val),
290 MC13783_GPO_DEFINE(REG, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val),
291 MC13783_GPO_DEFINE(REG, PWGT2SPI, POWERMISC, mc13783_pwgtdrv_val),
Sascha Hauer295c08b2009-08-19 01:43:50 +0200292};
293
Yong Shen167e3d82010-12-14 14:00:54 +0800294static int mc13783_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
295 u32 val)
Sascha Hauer295c08b2009-08-19 01:43:50 +0200296{
Yong Shen167e3d82010-12-14 14:00:54 +0800297 struct mc13xxx *mc13783 = priv->mc13xxx;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100298 int ret;
299 u32 valread;
300
301 BUG_ON(val & ~mask);
302
Axel Lin2a2c3ac2012-07-19 11:16:06 +0800303 mc13xxx_lock(priv->mc13xxx);
Yong Shen167e3d82010-12-14 14:00:54 +0800304 ret = mc13xxx_reg_read(mc13783, MC13783_REG_POWERMISC, &valread);
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100305 if (ret)
Axel Lin2a2c3ac2012-07-19 11:16:06 +0800306 goto out;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100307
308 /* Update the stored state for Power Gates. */
309 priv->powermisc_pwgt_state =
310 (priv->powermisc_pwgt_state & ~mask) | val;
311 priv->powermisc_pwgt_state &= MC13783_REG_POWERMISC_PWGTSPI_M;
312
313 /* Construct the new register value */
314 valread = (valread & ~mask) | val;
315 /* Overwrite the PWGTxEN with the stored version */
316 valread = (valread & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
317 priv->powermisc_pwgt_state;
318
Axel Lin2a2c3ac2012-07-19 11:16:06 +0800319 ret = mc13xxx_reg_write(mc13783, MC13783_REG_POWERMISC, valread);
320out:
321 mc13xxx_unlock(priv->mc13xxx);
322 return ret;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100323}
324
325static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev)
326{
Yong Shen167e3d82010-12-14 14:00:54 +0800327 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
328 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100329 int id = rdev_get_id(rdev);
Yong Shen167e3d82010-12-14 14:00:54 +0800330 u32 en_val = mc13xxx_regulators[id].enable_bit;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100331
332 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
333
334 /* Power Gate enable value is 0 */
Yong Shen57c78e32010-12-14 14:00:53 +0800335 if (id == MC13783_REG_PWGT1SPI ||
336 id == MC13783_REG_PWGT2SPI)
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100337 en_val = 0;
338
Axel Lin2a2c3ac2012-07-19 11:16:06 +0800339 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100340 en_val);
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100341}
342
343static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev)
344{
Yong Shen167e3d82010-12-14 14:00:54 +0800345 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
346 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100347 int id = rdev_get_id(rdev);
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100348 u32 dis_val = 0;
349
350 dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
351
352 /* Power Gate disable value is 1 */
Yong Shen57c78e32010-12-14 14:00:53 +0800353 if (id == MC13783_REG_PWGT1SPI ||
354 id == MC13783_REG_PWGT2SPI)
Yong Shen167e3d82010-12-14 14:00:54 +0800355 dis_val = mc13xxx_regulators[id].enable_bit;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100356
Axel Lin2a2c3ac2012-07-19 11:16:06 +0800357 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100358 dis_val);
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100359}
360
361static int mc13783_gpo_regulator_is_enabled(struct regulator_dev *rdev)
362{
Yong Shen167e3d82010-12-14 14:00:54 +0800363 struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
364 struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100365 int ret, id = rdev_get_id(rdev);
366 unsigned int val;
367
Yong Shen167e3d82010-12-14 14:00:54 +0800368 mc13xxx_lock(priv->mc13xxx);
369 ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val);
370 mc13xxx_unlock(priv->mc13xxx);
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100371
372 if (ret)
373 return ret;
374
375 /* Power Gates state is stored in powermisc_pwgt_state
376 * where the meaning of bits is negated */
377 val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
378 (priv->powermisc_pwgt_state ^ MC13783_REG_POWERMISC_PWGTSPI_M);
379
Yong Shen167e3d82010-12-14 14:00:54 +0800380 return (val & mc13xxx_regulators[id].enable_bit) != 0;
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100381}
382
383static struct regulator_ops mc13783_gpo_regulator_ops = {
384 .enable = mc13783_gpo_regulator_enable,
385 .disable = mc13783_gpo_regulator_disable,
386 .is_enabled = mc13783_gpo_regulator_is_enabled,
Axel Lin34e74f32012-06-08 15:41:48 +0800387 .list_voltage = regulator_list_voltage_table,
Yong Shen167e3d82010-12-14 14:00:54 +0800388 .set_voltage = mc13xxx_fixed_regulator_set_voltage,
Alberto Panizzof4b97b32010-01-19 12:48:54 +0100389};
390
Bill Pembertona5023572012-11-19 13:22:22 -0500391static int mc13783_regulator_probe(struct platform_device *pdev)
Sascha Hauer295c08b2009-08-19 01:43:50 +0200392{
Yong Shen167e3d82010-12-14 14:00:54 +0800393 struct mc13xxx_regulator_priv *priv;
394 struct mc13xxx *mc13783 = dev_get_drvdata(pdev->dev.parent);
Samuel Ortiz8f1585a2011-09-19 11:33:17 +0200395 struct mc13xxx_regulator_platform_data *pdata =
Samuel Ortizc8a03c92011-04-08 01:55:01 +0200396 dev_get_platdata(&pdev->dev);
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400397 struct mc13xxx_regulator_init_data *mc13xxx_data;
Axel Lina9d58012012-04-10 13:51:06 +0800398 struct regulator_config config = { };
Sachin Kamat8e568632013-09-04 12:00:59 +0530399 int i, num_regulators;
Sascha Hauer295c08b2009-08-19 01:43:50 +0200400
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400401 num_regulators = mc13xxx_get_num_regulators_dt(pdev);
Sascha Hauer295c08b2009-08-19 01:43:50 +0200402
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400403 if (num_regulators <= 0 && pdata)
404 num_regulators = pdata->num_regulators;
405 if (num_regulators <= 0)
Sascha Hauer0757b602012-02-29 09:01:40 +0100406 return -EINVAL;
407
Kees Cook0ed2dd02018-05-08 16:08:53 -0700408 priv = devm_kzalloc(&pdev->dev,
409 struct_size(priv, regulators, num_regulators),
410 GFP_KERNEL);
Sascha Hauer295c08b2009-08-19 01:43:50 +0200411 if (!priv)
412 return -ENOMEM;
413
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400414 priv->num_regulators = num_regulators;
Yong Shen167e3d82010-12-14 14:00:54 +0800415 priv->mc13xxx_regulators = mc13783_regulators;
416 priv->mc13xxx = mc13783;
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400417 platform_set_drvdata(pdev, priv);
Sascha Hauer295c08b2009-08-19 01:43:50 +0200418
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400419 mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13783_regulators,
420 ARRAY_SIZE(mc13783_regulators));
421
422 for (i = 0; i < priv->num_regulators; i++) {
423 struct regulator_init_data *init_data;
Axel Lina9d58012012-04-10 13:51:06 +0800424 struct regulator_desc *desc;
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400425 struct device_node *node = NULL;
426 int id;
Sascha Hauer295c08b2009-08-19 01:43:50 +0200427
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400428 if (mc13xxx_data) {
429 id = mc13xxx_data[i].id;
430 init_data = mc13xxx_data[i].init_data;
431 node = mc13xxx_data[i].node;
432 } else {
433 id = pdata->regulators[i].id;
434 init_data = pdata->regulators[i].init_data;
435 }
436 desc = &mc13783_regulators[id].desc;
Axel Lina9d58012012-04-10 13:51:06 +0800437
438 config.dev = &pdev->dev;
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400439 config.init_data = init_data;
Axel Lina9d58012012-04-10 13:51:06 +0800440 config.driver_data = priv;
Alexander Shiyan86b139f2013-04-27 10:29:25 +0400441 config.of_node = node;
Axel Lina9d58012012-04-10 13:51:06 +0800442
Sachin Kamat8e568632013-09-04 12:00:59 +0530443 priv->regulators[i] = devm_regulator_register(&pdev->dev, desc,
444 &config);
Sascha Hauer295c08b2009-08-19 01:43:50 +0200445 if (IS_ERR(priv->regulators[i])) {
446 dev_err(&pdev->dev, "failed to register regulator %s\n",
447 mc13783_regulators[i].desc.name);
Sachin Kamat8e568632013-09-04 12:00:59 +0530448 return PTR_ERR(priv->regulators[i]);
Sascha Hauer295c08b2009-08-19 01:43:50 +0200449 }
450 }
451
Sascha Hauer295c08b2009-08-19 01:43:50 +0200452 return 0;
Sascha Hauer295c08b2009-08-19 01:43:50 +0200453}
454
455static struct platform_driver mc13783_regulator_driver = {
456 .driver = {
457 .name = "mc13783-regulator",
Sascha Hauer295c08b2009-08-19 01:43:50 +0200458 },
Alberto Panizzo735eb932009-12-14 18:53:35 +0100459 .probe = mc13783_regulator_probe,
Sascha Hauer295c08b2009-08-19 01:43:50 +0200460};
461
462static int __init mc13783_regulator_init(void)
463{
Alberto Panizzo735eb932009-12-14 18:53:35 +0100464 return platform_driver_register(&mc13783_regulator_driver);
Sascha Hauer295c08b2009-08-19 01:43:50 +0200465}
466subsys_initcall(mc13783_regulator_init);
467
468static void __exit mc13783_regulator_exit(void)
469{
470 platform_driver_unregister(&mc13783_regulator_driver);
471}
472module_exit(mc13783_regulator_exit);
473
Uwe Kleine-Königa10099b2009-11-10 09:18:07 +0100474MODULE_LICENSE("GPL v2");
Axel Lin1dcc4342010-05-06 11:33:36 +0800475MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
Sascha Hauer295c08b2009-08-19 01:43:50 +0200476MODULE_DESCRIPTION("Regulator Driver for Freescale MC13783 PMIC");
477MODULE_ALIAS("platform:mc13783-regulator");