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gerrit-public.fairphone.software / kernel / msm-4.19 / 96e65d7f3f88d6e117ff80f3003d13c65e85cb03 / . / drivers / net / dsa / bcm_sf2.h
blob: 8fd6c1451a84a5903776cbedd4bbec743a3c408d [file] [log] [blame]
Florian Fainelli246d7f72014-08-27 17:04:56 -0700[diff] [blame]1/*
2 * Broadcom Starfighter2 private context
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __BCM_SF2_H
13#define __BCM_SF2_H
14
15#include <linux/platform_device.h>
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/spinlock.h>
19#include <linux/mutex.h>
20#include <linux/mii.h>
21
22#include <net/dsa.h>
23
24#include "bcm_sf2_regs.h"
25
26struct bcm_sf2_hw_params {
27 u16 top_rev;
28 u16 core_rev;
Florian Fainelliaa9aef72014-09-19 13:07:55 -0700[diff] [blame]29 u16 gphy_rev;
Florian Fainelli246d7f72014-08-27 17:04:56 -0700[diff] [blame]30 u32 num_gphy;
31 u8 num_acb_queue;
32 u8 num_rgmii;
33 u8 num_ports;
34 u8 fcb_pause_override:1;
35 u8 acb_packets_inflight:1;
36};
37
38#define BCM_SF2_REGS_NAME {\
39 "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
40}
41
42#define BCM_SF2_REGS_NUM 6
43
44struct bcm_sf2_port_status {
45 unsigned int link;
46};
47
48struct bcm_sf2_priv {
49 /* Base registers, keep those in order with BCM_SF2_REGS_NAME */
50 void __iomem *core;
51 void __iomem *reg;
52 void __iomem *intrl2_0;
53 void __iomem *intrl2_1;
54 void __iomem *fcb;
55 void __iomem *acb;
56
57 /* spinlock protecting access to the indirect registers */
58 spinlock_t indir_lock;
59
60 int irq0;
61 int irq1;
62 u32 irq0_stat;
63 u32 irq0_mask;
64 u32 irq1_stat;
65 u32 irq1_mask;
66
67 /* Mutex protecting access to the MIB counters */
68 struct mutex stats_mutex;
69
70 struct bcm_sf2_hw_params hw_params;
71
72 struct bcm_sf2_port_status port_sts[DSA_MAX_PORTS];
Florian Fainelli96e65d72014-09-18 17:31:25 -0700[diff] [blame^]73
74 /* Mask of ports enabled for Wake-on-LAN */
75 u32 wol_ports_mask;
Florian Fainelli246d7f72014-08-27 17:04:56 -0700[diff] [blame]76};
77
78struct bcm_sf2_hw_stats {
79 const char *string;
80 u16 reg;
81 u8 sizeof_stat;
82};
83
84#define SF2_IO_MACRO(name) \
85static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off) \
86{ \
87 return __raw_readl(priv->name + off); \
88} \
89static inline void name##_writel(struct bcm_sf2_priv *priv, \
90 u32 val, u32 off) \
91{ \
92 __raw_writel(val, priv->name + off); \
93} \
94
95/* Accesses to 64-bits register requires us to latch the hi/lo pairs
96 * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
97 * spinlock is automatically grabbed and released to provide relative
98 * atomiticy with latched reads/writes.
99 */
100#define SF2_IO64_MACRO(name) \
101static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off) \
102{ \
103 u32 indir, dir; \
104 spin_lock(&priv->indir_lock); \
105 indir = reg_readl(priv, REG_DIR_DATA_READ); \
106 dir = __raw_readl(priv->name + off); \
107 spin_unlock(&priv->indir_lock); \
108 return (u64)indir << 32 | dir; \
109} \
110static inline void name##_writeq(struct bcm_sf2_priv *priv, u32 off, \
111 u64 val) \
112{ \
113 spin_lock(&priv->indir_lock); \
114 reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE); \
115 __raw_writel(lower_32_bits(val), priv->name + off); \
116 spin_unlock(&priv->indir_lock); \
117}
118
119#define SWITCH_INTR_L2(which) \
120static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
121 u32 mask) \
122{ \
123 intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \
124 priv->irq##which##_mask &= ~(mask); \
125} \
126static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
127 u32 mask) \
128{ \
129 intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \
130 priv->irq##which##_mask |= (mask); \
131} \
132
133SF2_IO_MACRO(core);
134SF2_IO_MACRO(reg);
135SF2_IO64_MACRO(core);
136SF2_IO_MACRO(intrl2_0);
137SF2_IO_MACRO(intrl2_1);
138SF2_IO_MACRO(fcb);
139SF2_IO_MACRO(acb);
140
141SWITCH_INTR_L2(0);
142SWITCH_INTR_L2(1);
143
144#endif /* __BCM_SF2_H */