blob: 894c5c472184f9cf9c08f34966b83ff982766939 [file] [log] [blame]
Peter De Schrijverb36ab972012-02-10 01:47:45 +02001/*
2 * arch/arm/mach-tegra/reset.c
3 *
4 * Copyright (C) 2011,2012 NVIDIA Corporation.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
Thierry Redinga0524ac2014-07-11 09:44:49 +020017#include <linux/bitops.h>
18#include <linux/cpumask.h>
Peter De Schrijverb36ab972012-02-10 01:47:45 +020019#include <linux/init.h>
20#include <linux/io.h>
Peter De Schrijverb36ab972012-02-10 01:47:45 +020021
Thierry Reding304664e2014-07-11 09:52:41 +020022#include <soc/tegra/fuse.h>
23
Peter De Schrijverb36ab972012-02-10 01:47:45 +020024#include <asm/cacheflush.h>
Alexandre Courbot265c89c2013-11-24 15:30:51 +090025#include <asm/firmware.h>
Thierry Redinga0524ac2014-07-11 09:44:49 +020026#include <asm/hardware/cache-l2x0.h>
Peter De Schrijverb36ab972012-02-10 01:47:45 +020027
Stephen Warren2be39c02012-10-04 14:24:09 -060028#include "iomap.h"
Stephen Warrenbb1de882012-10-04 14:16:59 -060029#include "irammap.h"
Peter De Schrijverb36ab972012-02-10 01:47:45 +020030#include "reset.h"
Joseph Lod3f29362012-10-31 17:41:16 +080031#include "sleep.h"
Peter De Schrijverb36ab972012-02-10 01:47:45 +020032
33#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
34 TEGRA_IRAM_RESET_HANDLER_OFFSET)
35
36static bool is_enabled;
37
Alexandre Courbotad14ece2013-11-24 15:30:50 +090038static void __init tegra_cpu_reset_handler_set(const u32 reset_address)
Peter De Schrijverb36ab972012-02-10 01:47:45 +020039{
Peter De Schrijverb36ab972012-02-10 01:47:45 +020040 void __iomem *evp_cpu_reset =
41 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
42 void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
43 u32 reg;
44
Peter De Schrijverb36ab972012-02-10 01:47:45 +020045 /*
46 * NOTE: This must be the one and only write to the EVP CPU reset
47 * vector in the entire system.
48 */
Alexandre Courbotad14ece2013-11-24 15:30:50 +090049 writel(reset_address, evp_cpu_reset);
Peter De Schrijverb36ab972012-02-10 01:47:45 +020050 wmb();
51 reg = readl(evp_cpu_reset);
52
53 /*
54 * Prevent further modifications to the physical reset vector.
55 * NOTE: Has no effect on chips prior to Tegra30.
56 */
Thierry Redingc090e112014-07-11 11:06:20 +020057 reg = readl(sb_ctrl);
58 reg |= 2;
59 writel(reg, sb_ctrl);
60 wmb();
Alexandre Courbotad14ece2013-11-24 15:30:50 +090061}
62
63static void __init tegra_cpu_reset_handler_enable(void)
64{
65 void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
66 const u32 reset_address = TEGRA_IRAM_RESET_BASE +
67 tegra_cpu_reset_handler_offset;
Alexandre Courbot265c89c2013-11-24 15:30:51 +090068 int err;
Alexandre Courbotad14ece2013-11-24 15:30:50 +090069
70 BUG_ON(is_enabled);
71 BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
72
73 memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
74 tegra_cpu_reset_handler_size);
75
Alexandre Courbot265c89c2013-11-24 15:30:51 +090076 err = call_firmware_op(set_cpu_boot_addr, 0, reset_address);
77 switch (err) {
78 case -ENOSYS:
79 tegra_cpu_reset_handler_set(reset_address);
80 /* pass-through */
81 case 0:
82 is_enabled = true;
83 break;
84 default:
85 pr_crit("Cannot set CPU reset handler: %d\n", err);
86 BUG();
87 }
Peter De Schrijverb36ab972012-02-10 01:47:45 +020088}
89
90void __init tegra_cpu_reset_handler_init(void)
91{
92
93#ifdef CONFIG_SMP
94 __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
Joseph Lo9e323662013-01-04 17:32:22 +080095 *((u32 *)cpu_possible_mask);
Peter De Schrijverb36ab972012-02-10 01:47:45 +020096 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
97 virt_to_phys((void *)tegra_secondary_startup);
98#endif
99
Joseph Lod3f29362012-10-31 17:41:16 +0800100#ifdef CONFIG_PM_SLEEP
Joseph Lo5b795d02013-08-12 17:40:00 +0800101 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
Stephen Warrenfddb7702013-08-20 16:19:15 -0600102 TEGRA_IRAM_LPx_RESUME_AREA;
Joseph Lod3f29362012-10-31 17:41:16 +0800103 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
104 virt_to_phys((void *)tegra_resume);
105#endif
106
Peter De Schrijverb36ab972012-02-10 01:47:45 +0200107 tegra_cpu_reset_handler_enable();
108}