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Fabio Estevam2688a322013-07-16 14:40:29 -03001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/ {
13 regulators {
14 compatible = "simple-bus";
Shawn Guo56160e32014-02-07 23:22:50 +080015 #address-cells = <1>;
16 #size-cells = <0>;
Fabio Estevam2688a322013-07-16 14:40:29 -030017
Shawn Guo56160e32014-02-07 23:22:50 +080018 reg_2p5v: regulator@0 {
Fabio Estevam2688a322013-07-16 14:40:29 -030019 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080020 reg = <0>;
Fabio Estevam2688a322013-07-16 14:40:29 -030021 regulator-name = "2P5V";
22 regulator-min-microvolt = <2500000>;
23 regulator-max-microvolt = <2500000>;
24 regulator-always-on;
25 };
26
Shawn Guo56160e32014-02-07 23:22:50 +080027 reg_3p3v: regulator@1 {
Fabio Estevam2688a322013-07-16 14:40:29 -030028 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080029 reg = <1>;
Fabio Estevam2688a322013-07-16 14:40:29 -030030 regulator-name = "3P3V";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
33 regulator-always-on;
34 };
35 };
36
37 sound {
38 compatible = "fsl,imx6-wandboard-sgtl5000",
39 "fsl,imx-audio-sgtl5000";
40 model = "imx6-wandboard-sgtl5000";
41 ssi-controller = <&ssi1>;
42 audio-codec = <&codec>;
43 audio-routing =
44 "MIC_IN", "Mic Jack",
45 "Mic Jack", "Mic Bias",
46 "Headphone Jack", "HP_OUT";
47 mux-int-port = <1>;
48 mux-ext-port = <3>;
49 };
Fabio Estevamc9d96df2013-09-02 23:51:41 -030050
51 sound-spdif {
52 compatible = "fsl,imx-audio-spdif";
53 model = "imx-spdif";
54 spdif-controller = <&spdif>;
55 spdif-out;
56 };
Fabio Estevam2688a322013-07-16 14:40:29 -030057};
58
59&audmux {
60 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +080061 pinctrl-0 = <&pinctrl_audmux>;
Fabio Estevam2688a322013-07-16 14:40:29 -030062 status = "okay";
63};
64
Fabio Estevamfed687c2014-04-22 11:26:22 -030065&hdmi {
66 ddc-i2c-bus = <&i2c1>;
67 status = "okay";
68};
69
70&i2c1 {
71 clock-frequency = <100000>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_i2c1>;
74 status = "okay";
75};
76
Fabio Estevam2688a322013-07-16 14:40:29 -030077&i2c2 {
78 clock-frequency = <100000>;
79 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +080080 pinctrl-0 = <&pinctrl_i2c2>;
Fabio Estevam2688a322013-07-16 14:40:29 -030081 status = "okay";
82
83 codec: sgtl5000@0a {
84 compatible = "fsl,sgtl5000";
85 reg = <0x0a>;
Shawn Guoa94f8ec2013-07-18 14:42:28 +080086 clocks = <&clks 201>;
Fabio Estevam2688a322013-07-16 14:40:29 -030087 VDDA-supply = <&reg_2p5v>;
88 VDDIO-supply = <&reg_3p3v>;
89 };
90};
91
92&iomuxc {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_hog>;
95
Shawn Guo817c27a2013-10-23 15:36:09 +080096 imx6qdl-wandboard {
Fabio Estevam2688a322013-07-16 14:40:29 -030097 pinctrl_hog: hoggrp {
98 fsl,pins = <
Tony Priska338be92013-07-28 12:00:20 +120099 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
100 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
101 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
102 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 /* WL_REF_ON */
103 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* WL_RST_N */
104 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */
105 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
106 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
Fabio Estevam80121372013-09-27 11:12:42 -0300107 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
Fabio Estevam2688a322013-07-16 14:40:29 -0300108 >;
109 };
Shawn Guo817c27a2013-10-23 15:36:09 +0800110
111 pinctrl_audmux: audmuxgrp {
112 fsl,pins = <
Nicolin Chen77112dd2014-02-08 10:14:28 +0800113 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
114 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
115 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
116 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
Shawn Guo817c27a2013-10-23 15:36:09 +0800117 >;
118 };
119
120 pinctrl_enet: enetgrp {
121 fsl,pins = <
122 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
123 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
124 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
125 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
126 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
127 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
128 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
129 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
130 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
131 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
132 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
133 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
134 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
135 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
136 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
137 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
Sascha Silbe9fc77822014-02-06 23:24:13 +0100138 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
Shawn Guo817c27a2013-10-23 15:36:09 +0800139 >;
140 };
141
Fabio Estevamfed687c2014-04-22 11:26:22 -0300142 pinctrl_i2c1: i2c1grp {
143 fsl,pins = <
144 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
145 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
146 >;
147 };
148
Shawn Guo817c27a2013-10-23 15:36:09 +0800149 pinctrl_i2c2: i2c2grp {
150 fsl,pins = <
151 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
152 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
153 >;
154 };
155
156 pinctrl_spdif: spdifgrp {
157 fsl,pins = <
158 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
159 >;
160 };
161
162 pinctrl_uart1: uart1grp {
163 fsl,pins = <
164 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
165 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
166 >;
167 };
168
169 pinctrl_uart3: uart3grp {
170 fsl,pins = <
171 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
172 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
173 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
174 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
175 >;
176 };
177
178 pinctrl_usbotg: usbotggrp {
179 fsl,pins = <
180 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
181 >;
182 };
183
184 pinctrl_usdhc1: usdhc1grp {
185 fsl,pins = <
186 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
187 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
188 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
189 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
190 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
191 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
192 >;
193 };
194
195 pinctrl_usdhc2: usdhc2grp {
196 fsl,pins = <
197 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
198 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
199 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
200 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
201 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
202 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
203 >;
204 };
205
206 pinctrl_usdhc3: usdhc3grp {
207 fsl,pins = <
208 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
209 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
210 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
211 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
212 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
213 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
214 >;
215 };
Fabio Estevam2688a322013-07-16 14:40:29 -0300216 };
217};
218
219&fec {
220 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800221 pinctrl-0 = <&pinctrl_enet>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300222 phy-mode = "rgmii";
Fabio Estevam80121372013-09-27 11:12:42 -0300223 phy-reset-gpios = <&gpio3 29 0>;
Sascha Silbe9fc77822014-02-06 23:24:13 +0100224 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
225 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300226 status = "okay";
227};
228
Fabio Estevamc9d96df2013-09-02 23:51:41 -0300229&spdif {
230 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800231 pinctrl-0 = <&pinctrl_spdif>;
Fabio Estevamc9d96df2013-09-02 23:51:41 -0300232 status = "okay";
233};
234
Fabio Estevam2688a322013-07-16 14:40:29 -0300235&ssi1 {
236 fsl,mode = "i2s-slave";
237 status = "okay";
238};
239
240&uart1 {
241 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800242 pinctrl-0 = <&pinctrl_uart1>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300243 status = "okay";
244};
245
246&uart3 {
247 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800248 pinctrl-0 = <&pinctrl_uart3>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300249 fsl,uart-has-rtscts;
250 status = "okay";
251};
252
253&usbh1 {
254 status = "okay";
255};
256
Fabio Estevame9ac8902013-08-21 10:27:02 -0300257&usbotg {
258 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800259 pinctrl-0 = <&pinctrl_usbotg>;
Fabio Estevame9ac8902013-08-21 10:27:02 -0300260 disable-over-current;
261 dr_mode = "peripheral";
262 status = "okay";
263};
264
Fabio Estevam2688a322013-07-16 14:40:29 -0300265&usdhc1 {
266 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800267 pinctrl-0 = <&pinctrl_usdhc1>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300268 cd-gpios = <&gpio1 2 0>;
269 status = "okay";
270};
271
272&usdhc2 {
273 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800274 pinctrl-0 = <&pinctrl_usdhc2>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300275 non-removable;
276 status = "okay";
277};
278
279&usdhc3 {
280 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800281 pinctrl-0 = <&pinctrl_usdhc3>;
Fabio Estevam2688a322013-07-16 14:40:29 -0300282 cd-gpios = <&gpio3 9 0>;
283 status = "okay";
284};