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gerrit-public.fairphone.software / kernel / msm-4.19 / 9aa49ea3f5999a6a36823bd259892088896af140 / . / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c
blob: b5659cb688fe4fa4f9c016df68744a19bd180180 [file] [log] [blame]
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]1/*
Sujith Manoharan5b681382011-05-17 13:36:18 +0530[diff] [blame]2 * Copyright (c) 2010-2011 Atheros Communications Inc.
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]17#include <asm/unaligned.h>
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]18#include "hw.h"
19#include "ar9003_phy.h"
20#include "ar9003_eeprom.h"
21
22#define COMP_HDR_LEN 4
23#define COMP_CKSUM_LEN 2
24
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]25#define LE16(x) __constant_cpu_to_le16(x)
26#define LE32(x) __constant_cpu_to_le32(x)
27
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]28/* Local defines to distinguish between extension and control CTL's */
29#define EXT_ADDITIVE (0x8000)
30#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
31#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
32#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]33
34#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
35#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
36
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]37#define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
38
Vasanthakumar Thiagarajand0ce2d12010-12-21 01:42:43 -0800[diff] [blame]39#define EEPROM_DATA_LEN_9485 1088
40
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]41static int ar9003_hw_power_interpolate(int32_t x,
42 int32_t *px, int32_t *py, u_int16_t np);
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]43
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]44
45static const struct ar9300_eeprom ar9300_default = {
46 .eepromVersion = 2,
47 .templateVersion = 2,
Senthil Balasubramanianb503c7a2011-08-19 18:43:06 +0530[diff] [blame]48 .macAddr = {0, 2, 3, 4, 5, 6},
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]49 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
50 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
51 .baseEepHeader = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]52 .regDmn = { LE16(0), LE16(0x1f) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]53 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
54 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]55 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]56 .eepMisc = 0,
57 },
58 .rfSilent = 0,
59 .blueToothOptions = 0,
60 .deviceCap = 0,
61 .deviceType = 5, /* takes lower byte in eeprom location */
62 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
63 .params_for_tuning_caps = {0, 0},
64 .featureEnable = 0x0c,
65 /*
66 * bit0 - enable tx temp comp - disabled
67 * bit1 - enable tx volt comp - disabled
68 * bit2 - enable fastClock - enabled
69 * bit3 - enable doubling - enabled
70 * bit4 - enable internal regulator - disabled
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]71 * bit5 - enable pa predistortion - disabled
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]72 */
73 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
74 .eepromWriteEnableGpio = 3,
75 .wlanDisableGpio = 0,
76 .wlanLedGpio = 8,
77 .rxBandSelectGpio = 0xff,
78 .txrxgain = 0,
79 .swreg = 0,
80 },
81 .modalHeader2G = {
82 /* ar9300_modal_eep_header 2g */
83 /* 4 idle,t1,t2,b(4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]84 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]85 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]86 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]87
88 /*
89 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
90 * rx1, rx12, b (2 bits each)
91 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]92 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]93
94 /*
95 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
96 * for ar9280 (0xa20c/b20c 5:0)
97 */
98 .xatten1DB = {0, 0, 0},
99
100 /*
101 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
102 * for ar9280 (0xa20c/b20c 16:12
103 */
104 .xatten1Margin = {0, 0, 0},
105 .tempSlope = 36,
106 .voltSlope = 0,
107
108 /*
109 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
110 * channels in usual fbin coding format
111 */
112 .spurChans = {0, 0, 0, 0, 0},
113
114 /*
115 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
116 * if the register is per chain
117 */
118 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]119 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
120 .quick_drop = 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]121 .xpaBiasLvl = 0,
122 .txFrameToDataStart = 0x0e,
123 .txFrameToPaOn = 0x0e,
124 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
125 .antennaGain = 0,
126 .switchSettling = 0x2c,
127 .adcDesiredSize = -30,
128 .txEndToXpaOff = 0,
129 .txEndToRxOn = 0x2,
130 .txFrameToXpaOn = 0xe,
131 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]132 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
133 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]134 .xlna_bias_strength = 0,
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]135 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]136 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]137 },
138 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]139 .base_ext1 = {
140 .ant_div_control = 0,
Rajkumar Manoharan420e2b12012-09-10 17:05:11 +0530[diff] [blame]141 .future = {0, 0, 0},
142 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]143 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]144 .calFreqPier2G = {
145 FREQ2FBIN(2412, 1),
146 FREQ2FBIN(2437, 1),
147 FREQ2FBIN(2472, 1),
148 },
149 /* ar9300_cal_data_per_freq_op_loop 2g */
150 .calPierData2G = {
151 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
152 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
153 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
154 },
155 .calTarget_freqbin_Cck = {
156 FREQ2FBIN(2412, 1),
157 FREQ2FBIN(2484, 1),
158 },
159 .calTarget_freqbin_2G = {
160 FREQ2FBIN(2412, 1),
161 FREQ2FBIN(2437, 1),
162 FREQ2FBIN(2472, 1)
163 },
164 .calTarget_freqbin_2GHT20 = {
165 FREQ2FBIN(2412, 1),
166 FREQ2FBIN(2437, 1),
167 FREQ2FBIN(2472, 1)
168 },
169 .calTarget_freqbin_2GHT40 = {
170 FREQ2FBIN(2412, 1),
171 FREQ2FBIN(2437, 1),
172 FREQ2FBIN(2472, 1)
173 },
174 .calTargetPowerCck = {
175 /* 1L-5L,5S,11L,11S */
176 { {36, 36, 36, 36} },
177 { {36, 36, 36, 36} },
178 },
179 .calTargetPower2G = {
180 /* 6-24,36,48,54 */
181 { {32, 32, 28, 24} },
182 { {32, 32, 28, 24} },
183 { {32, 32, 28, 24} },
184 },
185 .calTargetPower2GHT20 = {
186 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
187 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
188 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
189 },
190 .calTargetPower2GHT40 = {
191 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
192 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
193 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
194 },
195 .ctlIndex_2G = {
196 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
197 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
198 },
199 .ctl_freqbin_2G = {
200 {
201 FREQ2FBIN(2412, 1),
202 FREQ2FBIN(2417, 1),
203 FREQ2FBIN(2457, 1),
204 FREQ2FBIN(2462, 1)
205 },
206 {
207 FREQ2FBIN(2412, 1),
208 FREQ2FBIN(2417, 1),
209 FREQ2FBIN(2462, 1),
210 0xFF,
211 },
212
213 {
214 FREQ2FBIN(2412, 1),
215 FREQ2FBIN(2417, 1),
216 FREQ2FBIN(2462, 1),
217 0xFF,
218 },
219 {
220 FREQ2FBIN(2422, 1),
221 FREQ2FBIN(2427, 1),
222 FREQ2FBIN(2447, 1),
223 FREQ2FBIN(2452, 1)
224 },
225
226 {
227 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
228 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
229 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
230 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
231 },
232
233 {
234 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
235 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
236 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
237 0,
238 },
239
240 {
241 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
242 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
243 FREQ2FBIN(2472, 1),
244 0,
245 },
246
247 {
248 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
249 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
250 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
251 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
252 },
253
254 {
255 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
256 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
257 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
258 },
259
260 {
261 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
262 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
263 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
264 0
265 },
266
267 {
268 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
269 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
270 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
271 0
272 },
273
274 {
275 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
276 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
277 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]278 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]279 }
280 },
281 .ctlPowerData_2G = {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]282 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
283 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
284 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]285
Rajkumar Manoharan15052f812011-07-29 17:38:15 +0530[diff] [blame]286 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]287 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
288 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]289
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]290 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
291 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
292 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]293
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]294 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
295 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
296 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]297 },
298 .modalHeader5G = {
299 /* 4 idle,t1,t2,b (4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]300 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]301 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]302 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]303 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
304 .antCtrlChain = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]305 LE16(0x000), LE16(0x000), LE16(0x000),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]306 },
307 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
308 .xatten1DB = {0, 0, 0},
309
310 /*
311 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
312 * for merlin (0xa20c/b20c 16:12
313 */
314 .xatten1Margin = {0, 0, 0},
315 .tempSlope = 68,
316 .voltSlope = 0,
317 /* spurChans spur channels in usual fbin coding format */
318 .spurChans = {0, 0, 0, 0, 0},
319 /* noiseFloorThreshCh Check if the register is per chain */
320 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]321 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
322 .quick_drop = 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]323 .xpaBiasLvl = 0,
324 .txFrameToDataStart = 0x0e,
325 .txFrameToPaOn = 0x0e,
326 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
327 .antennaGain = 0,
328 .switchSettling = 0x2d,
329 .adcDesiredSize = -30,
330 .txEndToXpaOff = 0,
331 .txEndToRxOn = 0x2,
332 .txFrameToXpaOn = 0xe,
333 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]334 .papdRateMaskHt20 = LE32(0x0c80c080),
335 .papdRateMaskHt40 = LE32(0x0080c080),
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]336 .xlna_bias_strength = 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]337 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]338 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]339 },
340 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]341 .base_ext2 = {
342 .tempSlopeLow = 0,
343 .tempSlopeHigh = 0,
344 .xatten1DBLow = {0, 0, 0},
345 .xatten1MarginLow = {0, 0, 0},
346 .xatten1DBHigh = {0, 0, 0},
347 .xatten1MarginHigh = {0, 0, 0}
348 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]349 .calFreqPier5G = {
350 FREQ2FBIN(5180, 0),
351 FREQ2FBIN(5220, 0),
352 FREQ2FBIN(5320, 0),
353 FREQ2FBIN(5400, 0),
354 FREQ2FBIN(5500, 0),
355 FREQ2FBIN(5600, 0),
356 FREQ2FBIN(5725, 0),
357 FREQ2FBIN(5825, 0)
358 },
359 .calPierData5G = {
360 {
361 {0, 0, 0, 0, 0},
362 {0, 0, 0, 0, 0},
363 {0, 0, 0, 0, 0},
364 {0, 0, 0, 0, 0},
365 {0, 0, 0, 0, 0},
366 {0, 0, 0, 0, 0},
367 {0, 0, 0, 0, 0},
368 {0, 0, 0, 0, 0},
369 },
370 {
371 {0, 0, 0, 0, 0},
372 {0, 0, 0, 0, 0},
373 {0, 0, 0, 0, 0},
374 {0, 0, 0, 0, 0},
375 {0, 0, 0, 0, 0},
376 {0, 0, 0, 0, 0},
377 {0, 0, 0, 0, 0},
378 {0, 0, 0, 0, 0},
379 },
380 {
381 {0, 0, 0, 0, 0},
382 {0, 0, 0, 0, 0},
383 {0, 0, 0, 0, 0},
384 {0, 0, 0, 0, 0},
385 {0, 0, 0, 0, 0},
386 {0, 0, 0, 0, 0},
387 {0, 0, 0, 0, 0},
388 {0, 0, 0, 0, 0},
389 },
390
391 },
392 .calTarget_freqbin_5G = {
393 FREQ2FBIN(5180, 0),
394 FREQ2FBIN(5220, 0),
395 FREQ2FBIN(5320, 0),
396 FREQ2FBIN(5400, 0),
397 FREQ2FBIN(5500, 0),
398 FREQ2FBIN(5600, 0),
399 FREQ2FBIN(5725, 0),
400 FREQ2FBIN(5825, 0)
401 },
402 .calTarget_freqbin_5GHT20 = {
403 FREQ2FBIN(5180, 0),
404 FREQ2FBIN(5240, 0),
405 FREQ2FBIN(5320, 0),
406 FREQ2FBIN(5500, 0),
407 FREQ2FBIN(5700, 0),
408 FREQ2FBIN(5745, 0),
409 FREQ2FBIN(5725, 0),
410 FREQ2FBIN(5825, 0)
411 },
412 .calTarget_freqbin_5GHT40 = {
413 FREQ2FBIN(5180, 0),
414 FREQ2FBIN(5240, 0),
415 FREQ2FBIN(5320, 0),
416 FREQ2FBIN(5500, 0),
417 FREQ2FBIN(5700, 0),
418 FREQ2FBIN(5745, 0),
419 FREQ2FBIN(5725, 0),
420 FREQ2FBIN(5825, 0)
421 },
422 .calTargetPower5G = {
423 /* 6-24,36,48,54 */
424 { {20, 20, 20, 10} },
425 { {20, 20, 20, 10} },
426 { {20, 20, 20, 10} },
427 { {20, 20, 20, 10} },
428 { {20, 20, 20, 10} },
429 { {20, 20, 20, 10} },
430 { {20, 20, 20, 10} },
431 { {20, 20, 20, 10} },
432 },
433 .calTargetPower5GHT20 = {
434 /*
435 * 0_8_16,1-3_9-11_17-19,
436 * 4,5,6,7,12,13,14,15,20,21,22,23
437 */
438 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
439 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
440 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
441 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
442 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
443 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
444 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
445 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
446 },
447 .calTargetPower5GHT40 = {
448 /*
449 * 0_8_16,1-3_9-11_17-19,
450 * 4,5,6,7,12,13,14,15,20,21,22,23
451 */
452 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
453 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
454 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
455 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
456 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
457 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
458 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
459 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
460 },
461 .ctlIndex_5G = {
462 0x10, 0x16, 0x18, 0x40, 0x46,
463 0x48, 0x30, 0x36, 0x38
464 },
465 .ctl_freqbin_5G = {
466 {
467 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
468 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
469 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
470 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
471 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
472 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
473 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
474 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
475 },
476 {
477 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
478 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
479 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
480 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
481 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
482 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
483 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
484 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
485 },
486
487 {
488 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
489 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
490 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
491 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
492 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
493 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
494 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
495 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
496 },
497
498 {
499 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
500 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
501 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
502 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
503 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
504 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
505 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
506 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
507 },
508
509 {
510 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
511 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
512 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
513 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
514 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
515 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
516 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
517 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
518 },
519
520 {
521 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
522 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
523 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
524 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
525 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
526 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
527 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
528 /* Data[5].ctlEdges[7].bChannel */ 0xFF
529 },
530
531 {
532 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
533 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
534 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
535 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
536 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
537 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
538 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
539 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
540 },
541
542 {
543 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
544 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
545 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
546 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
547 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
548 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
549 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
550 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
551 },
552
553 {
554 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
555 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
556 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
557 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
558 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
559 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
560 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
561 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
562 }
563 },
564 .ctlPowerData_5G = {
565 {
566 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]567 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
568 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]569 }
570 },
571 {
572 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]573 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
574 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]575 }
576 },
577 {
578 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]579 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
580 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]581 }
582 },
583 {
584 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]585 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
586 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]587 }
588 },
589 {
590 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]591 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
592 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]593 }
594 },
595 {
596 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]597 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
598 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]599 }
600 },
601 {
602 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]603 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
604 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]605 }
606 },
607 {
608 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]609 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
610 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]611 }
612 },
613 {
614 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]615 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
616 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]617 }
618 },
619 }
620};
621
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]622static const struct ar9300_eeprom ar9300_x113 = {
623 .eepromVersion = 2,
624 .templateVersion = 6,
625 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
626 .custData = {"x113-023-f0000"},
627 .baseEepHeader = {
628 .regDmn = { LE16(0), LE16(0x1f) },
629 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
630 .opCapFlags = {
Luis R. Rodriguez9ba7f4f2011-05-11 14:57:26 -0700[diff] [blame]631 .opFlags = AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]632 .eepMisc = 0,
633 },
634 .rfSilent = 0,
635 .blueToothOptions = 0,
636 .deviceCap = 0,
637 .deviceType = 5, /* takes lower byte in eeprom location */
638 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
639 .params_for_tuning_caps = {0, 0},
640 .featureEnable = 0x0d,
641 /*
642 * bit0 - enable tx temp comp - disabled
643 * bit1 - enable tx volt comp - disabled
644 * bit2 - enable fastClock - enabled
645 * bit3 - enable doubling - enabled
646 * bit4 - enable internal regulator - disabled
647 * bit5 - enable pa predistortion - disabled
648 */
649 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
650 .eepromWriteEnableGpio = 6,
651 .wlanDisableGpio = 0,
652 .wlanLedGpio = 8,
653 .rxBandSelectGpio = 0xff,
654 .txrxgain = 0x21,
655 .swreg = 0,
656 },
657 .modalHeader2G = {
658 /* ar9300_modal_eep_header 2g */
659 /* 4 idle,t1,t2,b(4 bits per setting) */
660 .antCtrlCommon = LE32(0x110),
661 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
662 .antCtrlCommon2 = LE32(0x44444),
663
664 /*
665 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
666 * rx1, rx12, b (2 bits each)
667 */
668 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
669
670 /*
671 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
672 * for ar9280 (0xa20c/b20c 5:0)
673 */
674 .xatten1DB = {0, 0, 0},
675
676 /*
677 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
678 * for ar9280 (0xa20c/b20c 16:12
679 */
680 .xatten1Margin = {0, 0, 0},
681 .tempSlope = 25,
682 .voltSlope = 0,
683
684 /*
685 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
686 * channels in usual fbin coding format
687 */
688 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
689
690 /*
691 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
692 * if the register is per chain
693 */
694 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]695 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
696 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]697 .xpaBiasLvl = 0,
698 .txFrameToDataStart = 0x0e,
699 .txFrameToPaOn = 0x0e,
700 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
701 .antennaGain = 0,
702 .switchSettling = 0x2c,
703 .adcDesiredSize = -30,
704 .txEndToXpaOff = 0,
705 .txEndToRxOn = 0x2,
706 .txFrameToXpaOn = 0xe,
707 .thresh62 = 28,
708 .papdRateMaskHt20 = LE32(0x0c80c080),
709 .papdRateMaskHt40 = LE32(0x0080c080),
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]710 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]711 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]712 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]713 },
714 },
715 .base_ext1 = {
716 .ant_div_control = 0,
Rajkumar Manoharan420e2b12012-09-10 17:05:11 +0530[diff] [blame]717 .future = {0, 0, 0},
718 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]719 },
720 .calFreqPier2G = {
721 FREQ2FBIN(2412, 1),
722 FREQ2FBIN(2437, 1),
723 FREQ2FBIN(2472, 1),
724 },
725 /* ar9300_cal_data_per_freq_op_loop 2g */
726 .calPierData2G = {
727 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
728 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
729 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
730 },
731 .calTarget_freqbin_Cck = {
732 FREQ2FBIN(2412, 1),
733 FREQ2FBIN(2472, 1),
734 },
735 .calTarget_freqbin_2G = {
736 FREQ2FBIN(2412, 1),
737 FREQ2FBIN(2437, 1),
738 FREQ2FBIN(2472, 1)
739 },
740 .calTarget_freqbin_2GHT20 = {
741 FREQ2FBIN(2412, 1),
742 FREQ2FBIN(2437, 1),
743 FREQ2FBIN(2472, 1)
744 },
745 .calTarget_freqbin_2GHT40 = {
746 FREQ2FBIN(2412, 1),
747 FREQ2FBIN(2437, 1),
748 FREQ2FBIN(2472, 1)
749 },
750 .calTargetPowerCck = {
751 /* 1L-5L,5S,11L,11S */
752 { {34, 34, 34, 34} },
753 { {34, 34, 34, 34} },
754 },
755 .calTargetPower2G = {
756 /* 6-24,36,48,54 */
757 { {34, 34, 32, 32} },
758 { {34, 34, 32, 32} },
759 { {34, 34, 32, 32} },
760 },
761 .calTargetPower2GHT20 = {
762 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
763 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
764 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
765 },
766 .calTargetPower2GHT40 = {
767 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
768 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
769 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
770 },
771 .ctlIndex_2G = {
772 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
773 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
774 },
775 .ctl_freqbin_2G = {
776 {
777 FREQ2FBIN(2412, 1),
778 FREQ2FBIN(2417, 1),
779 FREQ2FBIN(2457, 1),
780 FREQ2FBIN(2462, 1)
781 },
782 {
783 FREQ2FBIN(2412, 1),
784 FREQ2FBIN(2417, 1),
785 FREQ2FBIN(2462, 1),
786 0xFF,
787 },
788
789 {
790 FREQ2FBIN(2412, 1),
791 FREQ2FBIN(2417, 1),
792 FREQ2FBIN(2462, 1),
793 0xFF,
794 },
795 {
796 FREQ2FBIN(2422, 1),
797 FREQ2FBIN(2427, 1),
798 FREQ2FBIN(2447, 1),
799 FREQ2FBIN(2452, 1)
800 },
801
802 {
803 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
804 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
805 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
806 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
807 },
808
809 {
810 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
811 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
812 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
813 0,
814 },
815
816 {
817 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
818 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
819 FREQ2FBIN(2472, 1),
820 0,
821 },
822
823 {
824 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
825 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
826 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
827 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
828 },
829
830 {
831 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
832 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
833 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
834 },
835
836 {
837 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
838 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
839 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
840 0
841 },
842
843 {
844 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
845 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
846 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
847 0
848 },
849
850 {
851 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
852 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
853 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
854 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
855 }
856 },
857 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]858 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
859 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
860 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]861
Rajkumar Manoharan15052f812011-07-29 17:38:15 +0530[diff] [blame]862 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]863 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
864 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]865
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]866 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
867 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
868 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]869
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]870 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
871 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
872 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]873 },
874 .modalHeader5G = {
875 /* 4 idle,t1,t2,b (4 bits per setting) */
876 .antCtrlCommon = LE32(0x220),
877 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
878 .antCtrlCommon2 = LE32(0x11111),
879 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
880 .antCtrlChain = {
881 LE16(0x150), LE16(0x150), LE16(0x150),
882 },
883 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
884 .xatten1DB = {0, 0, 0},
885
886 /*
887 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
888 * for merlin (0xa20c/b20c 16:12
889 */
890 .xatten1Margin = {0, 0, 0},
891 .tempSlope = 68,
892 .voltSlope = 0,
893 /* spurChans spur channels in usual fbin coding format */
894 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
895 /* noiseFloorThreshCh Check if the register is per chain */
896 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]897 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
898 .quick_drop = 0,
Senthil Balasubramanianbe0e6aa2011-05-12 16:24:28 +0530[diff] [blame]899 .xpaBiasLvl = 0xf,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]900 .txFrameToDataStart = 0x0e,
901 .txFrameToPaOn = 0x0e,
902 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
903 .antennaGain = 0,
904 .switchSettling = 0x2d,
905 .adcDesiredSize = -30,
906 .txEndToXpaOff = 0,
907 .txEndToRxOn = 0x2,
908 .txFrameToXpaOn = 0xe,
909 .thresh62 = 28,
910 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
911 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]912 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]913 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]914 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]915 },
916 },
917 .base_ext2 = {
918 .tempSlopeLow = 72,
919 .tempSlopeHigh = 105,
920 .xatten1DBLow = {0, 0, 0},
921 .xatten1MarginLow = {0, 0, 0},
922 .xatten1DBHigh = {0, 0, 0},
923 .xatten1MarginHigh = {0, 0, 0}
924 },
925 .calFreqPier5G = {
926 FREQ2FBIN(5180, 0),
927 FREQ2FBIN(5240, 0),
928 FREQ2FBIN(5320, 0),
929 FREQ2FBIN(5400, 0),
930 FREQ2FBIN(5500, 0),
931 FREQ2FBIN(5600, 0),
932 FREQ2FBIN(5745, 0),
933 FREQ2FBIN(5785, 0)
934 },
935 .calPierData5G = {
936 {
937 {0, 0, 0, 0, 0},
938 {0, 0, 0, 0, 0},
939 {0, 0, 0, 0, 0},
940 {0, 0, 0, 0, 0},
941 {0, 0, 0, 0, 0},
942 {0, 0, 0, 0, 0},
943 {0, 0, 0, 0, 0},
944 {0, 0, 0, 0, 0},
945 },
946 {
947 {0, 0, 0, 0, 0},
948 {0, 0, 0, 0, 0},
949 {0, 0, 0, 0, 0},
950 {0, 0, 0, 0, 0},
951 {0, 0, 0, 0, 0},
952 {0, 0, 0, 0, 0},
953 {0, 0, 0, 0, 0},
954 {0, 0, 0, 0, 0},
955 },
956 {
957 {0, 0, 0, 0, 0},
958 {0, 0, 0, 0, 0},
959 {0, 0, 0, 0, 0},
960 {0, 0, 0, 0, 0},
961 {0, 0, 0, 0, 0},
962 {0, 0, 0, 0, 0},
963 {0, 0, 0, 0, 0},
964 {0, 0, 0, 0, 0},
965 },
966
967 },
968 .calTarget_freqbin_5G = {
969 FREQ2FBIN(5180, 0),
970 FREQ2FBIN(5220, 0),
971 FREQ2FBIN(5320, 0),
972 FREQ2FBIN(5400, 0),
973 FREQ2FBIN(5500, 0),
974 FREQ2FBIN(5600, 0),
975 FREQ2FBIN(5745, 0),
976 FREQ2FBIN(5785, 0)
977 },
978 .calTarget_freqbin_5GHT20 = {
979 FREQ2FBIN(5180, 0),
980 FREQ2FBIN(5240, 0),
981 FREQ2FBIN(5320, 0),
982 FREQ2FBIN(5400, 0),
983 FREQ2FBIN(5500, 0),
984 FREQ2FBIN(5700, 0),
985 FREQ2FBIN(5745, 0),
986 FREQ2FBIN(5825, 0)
987 },
988 .calTarget_freqbin_5GHT40 = {
989 FREQ2FBIN(5190, 0),
990 FREQ2FBIN(5230, 0),
991 FREQ2FBIN(5320, 0),
992 FREQ2FBIN(5410, 0),
993 FREQ2FBIN(5510, 0),
994 FREQ2FBIN(5670, 0),
995 FREQ2FBIN(5755, 0),
996 FREQ2FBIN(5825, 0)
997 },
998 .calTargetPower5G = {
999 /* 6-24,36,48,54 */
1000 { {42, 40, 40, 34} },
1001 { {42, 40, 40, 34} },
1002 { {42, 40, 40, 34} },
1003 { {42, 40, 40, 34} },
1004 { {42, 40, 40, 34} },
1005 { {42, 40, 40, 34} },
1006 { {42, 40, 40, 34} },
1007 { {42, 40, 40, 34} },
1008 },
1009 .calTargetPower5GHT20 = {
1010 /*
1011 * 0_8_16,1-3_9-11_17-19,
1012 * 4,5,6,7,12,13,14,15,20,21,22,23
1013 */
1014 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1015 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1016 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1017 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1018 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1019 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1020 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1021 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1022 },
1023 .calTargetPower5GHT40 = {
1024 /*
1025 * 0_8_16,1-3_9-11_17-19,
1026 * 4,5,6,7,12,13,14,15,20,21,22,23
1027 */
1028 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1029 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1030 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1031 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1032 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1033 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1034 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1035 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1036 },
1037 .ctlIndex_5G = {
1038 0x10, 0x16, 0x18, 0x40, 0x46,
1039 0x48, 0x30, 0x36, 0x38
1040 },
1041 .ctl_freqbin_5G = {
1042 {
1043 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1044 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1045 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1046 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1047 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1048 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1049 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1050 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1051 },
1052 {
1053 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1054 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1055 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1056 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1057 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1058 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1059 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1060 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1061 },
1062
1063 {
1064 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1065 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1066 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1067 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1068 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1069 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1070 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1071 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1072 },
1073
1074 {
1075 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1076 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1077 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1078 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1079 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1080 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1081 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1082 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1083 },
1084
1085 {
1086 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1087 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1088 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1089 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1090 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1091 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1092 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1093 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1094 },
1095
1096 {
1097 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1098 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1099 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1100 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1101 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1102 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1103 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1104 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1105 },
1106
1107 {
1108 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1109 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1110 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1111 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1112 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1113 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1114 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1115 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1116 },
1117
1118 {
1119 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1120 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1121 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1122 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1123 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1124 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1125 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1126 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1127 },
1128
1129 {
1130 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1131 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1132 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1133 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1134 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1135 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1136 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1137 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1138 }
1139 },
1140 .ctlPowerData_5G = {
1141 {
1142 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1143 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1144 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1145 }
1146 },
1147 {
1148 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1149 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1150 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1151 }
1152 },
1153 {
1154 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1155 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1156 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1157 }
1158 },
1159 {
1160 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1161 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1162 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1163 }
1164 },
1165 {
1166 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1167 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1168 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1169 }
1170 },
1171 {
1172 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1173 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1174 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1175 }
1176 },
1177 {
1178 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1179 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1180 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1181 }
1182 },
1183 {
1184 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1185 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1186 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1187 }
1188 },
1189 {
1190 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1191 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1192 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1193 }
1194 },
1195 }
1196};
1197
1198
1199static const struct ar9300_eeprom ar9300_h112 = {
1200 .eepromVersion = 2,
1201 .templateVersion = 3,
1202 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1203 .custData = {"h112-241-f0000"},
1204 .baseEepHeader = {
1205 .regDmn = { LE16(0), LE16(0x1f) },
1206 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1207 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]1208 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1209 .eepMisc = 0,
1210 },
1211 .rfSilent = 0,
1212 .blueToothOptions = 0,
1213 .deviceCap = 0,
1214 .deviceType = 5, /* takes lower byte in eeprom location */
1215 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1216 .params_for_tuning_caps = {0, 0},
1217 .featureEnable = 0x0d,
1218 /*
1219 * bit0 - enable tx temp comp - disabled
1220 * bit1 - enable tx volt comp - disabled
1221 * bit2 - enable fastClock - enabled
1222 * bit3 - enable doubling - enabled
1223 * bit4 - enable internal regulator - disabled
1224 * bit5 - enable pa predistortion - disabled
1225 */
1226 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1227 .eepromWriteEnableGpio = 6,
1228 .wlanDisableGpio = 0,
1229 .wlanLedGpio = 8,
1230 .rxBandSelectGpio = 0xff,
1231 .txrxgain = 0x10,
1232 .swreg = 0,
1233 },
1234 .modalHeader2G = {
1235 /* ar9300_modal_eep_header 2g */
1236 /* 4 idle,t1,t2,b(4 bits per setting) */
1237 .antCtrlCommon = LE32(0x110),
1238 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1239 .antCtrlCommon2 = LE32(0x44444),
1240
1241 /*
1242 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1243 * rx1, rx12, b (2 bits each)
1244 */
1245 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1246
1247 /*
1248 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1249 * for ar9280 (0xa20c/b20c 5:0)
1250 */
1251 .xatten1DB = {0, 0, 0},
1252
1253 /*
1254 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1255 * for ar9280 (0xa20c/b20c 16:12
1256 */
1257 .xatten1Margin = {0, 0, 0},
1258 .tempSlope = 25,
1259 .voltSlope = 0,
1260
1261 /*
1262 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1263 * channels in usual fbin coding format
1264 */
1265 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1266
1267 /*
1268 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1269 * if the register is per chain
1270 */
1271 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]1272 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1273 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1274 .xpaBiasLvl = 0,
1275 .txFrameToDataStart = 0x0e,
1276 .txFrameToPaOn = 0x0e,
1277 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1278 .antennaGain = 0,
1279 .switchSettling = 0x2c,
1280 .adcDesiredSize = -30,
1281 .txEndToXpaOff = 0,
1282 .txEndToRxOn = 0x2,
1283 .txFrameToXpaOn = 0xe,
1284 .thresh62 = 28,
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]1285 .papdRateMaskHt20 = LE32(0x0c80c080),
1286 .papdRateMaskHt40 = LE32(0x0080c080),
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]1287 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1288 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]1289 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1290 },
1291 },
1292 .base_ext1 = {
1293 .ant_div_control = 0,
Rajkumar Manoharan420e2b12012-09-10 17:05:11 +0530[diff] [blame]1294 .future = {0, 0, 0},
1295 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1296 },
1297 .calFreqPier2G = {
1298 FREQ2FBIN(2412, 1),
1299 FREQ2FBIN(2437, 1),
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]1300 FREQ2FBIN(2462, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1301 },
1302 /* ar9300_cal_data_per_freq_op_loop 2g */
1303 .calPierData2G = {
1304 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1305 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1306 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1307 },
1308 .calTarget_freqbin_Cck = {
1309 FREQ2FBIN(2412, 1),
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]1310 FREQ2FBIN(2472, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1311 },
1312 .calTarget_freqbin_2G = {
1313 FREQ2FBIN(2412, 1),
1314 FREQ2FBIN(2437, 1),
1315 FREQ2FBIN(2472, 1)
1316 },
1317 .calTarget_freqbin_2GHT20 = {
1318 FREQ2FBIN(2412, 1),
1319 FREQ2FBIN(2437, 1),
1320 FREQ2FBIN(2472, 1)
1321 },
1322 .calTarget_freqbin_2GHT40 = {
1323 FREQ2FBIN(2412, 1),
1324 FREQ2FBIN(2437, 1),
1325 FREQ2FBIN(2472, 1)
1326 },
1327 .calTargetPowerCck = {
1328 /* 1L-5L,5S,11L,11S */
1329 { {34, 34, 34, 34} },
1330 { {34, 34, 34, 34} },
1331 },
1332 .calTargetPower2G = {
1333 /* 6-24,36,48,54 */
1334 { {34, 34, 32, 32} },
1335 { {34, 34, 32, 32} },
1336 { {34, 34, 32, 32} },
1337 },
1338 .calTargetPower2GHT20 = {
1339 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1340 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1341 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1342 },
1343 .calTargetPower2GHT40 = {
1344 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1345 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1346 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1347 },
1348 .ctlIndex_2G = {
1349 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1350 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1351 },
1352 .ctl_freqbin_2G = {
1353 {
1354 FREQ2FBIN(2412, 1),
1355 FREQ2FBIN(2417, 1),
1356 FREQ2FBIN(2457, 1),
1357 FREQ2FBIN(2462, 1)
1358 },
1359 {
1360 FREQ2FBIN(2412, 1),
1361 FREQ2FBIN(2417, 1),
1362 FREQ2FBIN(2462, 1),
1363 0xFF,
1364 },
1365
1366 {
1367 FREQ2FBIN(2412, 1),
1368 FREQ2FBIN(2417, 1),
1369 FREQ2FBIN(2462, 1),
1370 0xFF,
1371 },
1372 {
1373 FREQ2FBIN(2422, 1),
1374 FREQ2FBIN(2427, 1),
1375 FREQ2FBIN(2447, 1),
1376 FREQ2FBIN(2452, 1)
1377 },
1378
1379 {
1380 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1381 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1382 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1383 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1384 },
1385
1386 {
1387 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1388 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1389 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1390 0,
1391 },
1392
1393 {
1394 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1395 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1396 FREQ2FBIN(2472, 1),
1397 0,
1398 },
1399
1400 {
1401 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1402 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1403 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1404 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1405 },
1406
1407 {
1408 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1409 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1410 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1411 },
1412
1413 {
1414 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1415 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1416 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1417 0
1418 },
1419
1420 {
1421 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1422 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1423 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1424 0
1425 },
1426
1427 {
1428 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1429 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1430 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1431 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1432 }
1433 },
1434 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1435 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1436 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1437 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1438
Mohammed Shafi Shajakhan81dc6762011-06-17 11:07:32 +0530[diff] [blame]1439 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1440 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1441 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1442
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1443 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1444 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1445 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1446
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1447 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1448 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1449 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1450 },
1451 .modalHeader5G = {
1452 /* 4 idle,t1,t2,b (4 bits per setting) */
1453 .antCtrlCommon = LE32(0x220),
1454 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1455 .antCtrlCommon2 = LE32(0x44444),
1456 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1457 .antCtrlChain = {
1458 LE16(0x150), LE16(0x150), LE16(0x150),
1459 },
1460 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1461 .xatten1DB = {0, 0, 0},
1462
1463 /*
1464 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1465 * for merlin (0xa20c/b20c 16:12
1466 */
1467 .xatten1Margin = {0, 0, 0},
1468 .tempSlope = 45,
1469 .voltSlope = 0,
1470 /* spurChans spur channels in usual fbin coding format */
1471 .spurChans = {0, 0, 0, 0, 0},
1472 /* noiseFloorThreshCh Check if the register is per chain */
1473 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]1474 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1475 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1476 .xpaBiasLvl = 0,
1477 .txFrameToDataStart = 0x0e,
1478 .txFrameToPaOn = 0x0e,
1479 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1480 .antennaGain = 0,
1481 .switchSettling = 0x2d,
1482 .adcDesiredSize = -30,
1483 .txEndToXpaOff = 0,
1484 .txEndToRxOn = 0x2,
1485 .txFrameToXpaOn = 0xe,
1486 .thresh62 = 28,
1487 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1488 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]1489 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1490 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]1491 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1492 },
1493 },
1494 .base_ext2 = {
1495 .tempSlopeLow = 40,
1496 .tempSlopeHigh = 50,
1497 .xatten1DBLow = {0, 0, 0},
1498 .xatten1MarginLow = {0, 0, 0},
1499 .xatten1DBHigh = {0, 0, 0},
1500 .xatten1MarginHigh = {0, 0, 0}
1501 },
1502 .calFreqPier5G = {
1503 FREQ2FBIN(5180, 0),
1504 FREQ2FBIN(5220, 0),
1505 FREQ2FBIN(5320, 0),
1506 FREQ2FBIN(5400, 0),
1507 FREQ2FBIN(5500, 0),
1508 FREQ2FBIN(5600, 0),
1509 FREQ2FBIN(5700, 0),
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]1510 FREQ2FBIN(5785, 0)
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1511 },
1512 .calPierData5G = {
1513 {
1514 {0, 0, 0, 0, 0},
1515 {0, 0, 0, 0, 0},
1516 {0, 0, 0, 0, 0},
1517 {0, 0, 0, 0, 0},
1518 {0, 0, 0, 0, 0},
1519 {0, 0, 0, 0, 0},
1520 {0, 0, 0, 0, 0},
1521 {0, 0, 0, 0, 0},
1522 },
1523 {
1524 {0, 0, 0, 0, 0},
1525 {0, 0, 0, 0, 0},
1526 {0, 0, 0, 0, 0},
1527 {0, 0, 0, 0, 0},
1528 {0, 0, 0, 0, 0},
1529 {0, 0, 0, 0, 0},
1530 {0, 0, 0, 0, 0},
1531 {0, 0, 0, 0, 0},
1532 },
1533 {
1534 {0, 0, 0, 0, 0},
1535 {0, 0, 0, 0, 0},
1536 {0, 0, 0, 0, 0},
1537 {0, 0, 0, 0, 0},
1538 {0, 0, 0, 0, 0},
1539 {0, 0, 0, 0, 0},
1540 {0, 0, 0, 0, 0},
1541 {0, 0, 0, 0, 0},
1542 },
1543
1544 },
1545 .calTarget_freqbin_5G = {
1546 FREQ2FBIN(5180, 0),
1547 FREQ2FBIN(5240, 0),
1548 FREQ2FBIN(5320, 0),
1549 FREQ2FBIN(5400, 0),
1550 FREQ2FBIN(5500, 0),
1551 FREQ2FBIN(5600, 0),
1552 FREQ2FBIN(5700, 0),
1553 FREQ2FBIN(5825, 0)
1554 },
1555 .calTarget_freqbin_5GHT20 = {
1556 FREQ2FBIN(5180, 0),
1557 FREQ2FBIN(5240, 0),
1558 FREQ2FBIN(5320, 0),
1559 FREQ2FBIN(5400, 0),
1560 FREQ2FBIN(5500, 0),
1561 FREQ2FBIN(5700, 0),
1562 FREQ2FBIN(5745, 0),
1563 FREQ2FBIN(5825, 0)
1564 },
1565 .calTarget_freqbin_5GHT40 = {
1566 FREQ2FBIN(5180, 0),
1567 FREQ2FBIN(5240, 0),
1568 FREQ2FBIN(5320, 0),
1569 FREQ2FBIN(5400, 0),
1570 FREQ2FBIN(5500, 0),
1571 FREQ2FBIN(5700, 0),
1572 FREQ2FBIN(5745, 0),
1573 FREQ2FBIN(5825, 0)
1574 },
1575 .calTargetPower5G = {
1576 /* 6-24,36,48,54 */
1577 { {30, 30, 28, 24} },
1578 { {30, 30, 28, 24} },
1579 { {30, 30, 28, 24} },
1580 { {30, 30, 28, 24} },
1581 { {30, 30, 28, 24} },
1582 { {30, 30, 28, 24} },
1583 { {30, 30, 28, 24} },
1584 { {30, 30, 28, 24} },
1585 },
1586 .calTargetPower5GHT20 = {
1587 /*
1588 * 0_8_16,1-3_9-11_17-19,
1589 * 4,5,6,7,12,13,14,15,20,21,22,23
1590 */
1591 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1592 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1593 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1594 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1595 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1596 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1597 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1598 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1599 },
1600 .calTargetPower5GHT40 = {
1601 /*
1602 * 0_8_16,1-3_9-11_17-19,
1603 * 4,5,6,7,12,13,14,15,20,21,22,23
1604 */
1605 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1606 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1607 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1608 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1609 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1610 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1611 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1612 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1613 },
1614 .ctlIndex_5G = {
1615 0x10, 0x16, 0x18, 0x40, 0x46,
1616 0x48, 0x30, 0x36, 0x38
1617 },
1618 .ctl_freqbin_5G = {
1619 {
1620 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1621 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1622 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1623 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1624 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1625 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1626 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1627 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1628 },
1629 {
1630 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1631 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1632 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1633 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1634 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1635 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1636 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1637 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1638 },
1639
1640 {
1641 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1642 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1643 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1644 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1645 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1646 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1647 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1648 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1649 },
1650
1651 {
1652 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1653 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1654 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1655 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1656 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1657 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1658 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1659 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1660 },
1661
1662 {
1663 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1664 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1665 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1666 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1667 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1668 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1669 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1670 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1671 },
1672
1673 {
1674 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1675 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1676 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1677 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1678 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1679 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1680 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1681 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1682 },
1683
1684 {
1685 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1686 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1687 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1688 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1689 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1690 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1691 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1692 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1693 },
1694
1695 {
1696 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1697 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1698 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1699 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1700 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1701 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1702 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1703 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1704 },
1705
1706 {
1707 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1708 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1709 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1710 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1711 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1712 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1713 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1714 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1715 }
1716 },
1717 .ctlPowerData_5G = {
1718 {
1719 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1720 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1721 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1722 }
1723 },
1724 {
1725 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1726 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1727 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1728 }
1729 },
1730 {
1731 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1732 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1733 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1734 }
1735 },
1736 {
1737 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1738 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1739 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1740 }
1741 },
1742 {
1743 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1744 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1745 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1746 }
1747 },
1748 {
1749 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1750 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1751 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1752 }
1753 },
1754 {
1755 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1756 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1757 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1758 }
1759 },
1760 {
1761 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1762 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1763 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1764 }
1765 },
1766 {
1767 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1768 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1769 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1770 }
1771 },
1772 }
1773};
1774
1775
1776static const struct ar9300_eeprom ar9300_x112 = {
1777 .eepromVersion = 2,
1778 .templateVersion = 5,
1779 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1780 .custData = {"x112-041-f0000"},
1781 .baseEepHeader = {
1782 .regDmn = { LE16(0), LE16(0x1f) },
1783 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1784 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]1785 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1786 .eepMisc = 0,
1787 },
1788 .rfSilent = 0,
1789 .blueToothOptions = 0,
1790 .deviceCap = 0,
1791 .deviceType = 5, /* takes lower byte in eeprom location */
1792 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1793 .params_for_tuning_caps = {0, 0},
1794 .featureEnable = 0x0d,
1795 /*
1796 * bit0 - enable tx temp comp - disabled
1797 * bit1 - enable tx volt comp - disabled
1798 * bit2 - enable fastclock - enabled
1799 * bit3 - enable doubling - enabled
1800 * bit4 - enable internal regulator - disabled
1801 * bit5 - enable pa predistortion - disabled
1802 */
1803 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1804 .eepromWriteEnableGpio = 6,
1805 .wlanDisableGpio = 0,
1806 .wlanLedGpio = 8,
1807 .rxBandSelectGpio = 0xff,
1808 .txrxgain = 0x0,
1809 .swreg = 0,
1810 },
1811 .modalHeader2G = {
1812 /* ar9300_modal_eep_header 2g */
1813 /* 4 idle,t1,t2,b(4 bits per setting) */
1814 .antCtrlCommon = LE32(0x110),
1815 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1816 .antCtrlCommon2 = LE32(0x22222),
1817
1818 /*
1819 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1820 * rx1, rx12, b (2 bits each)
1821 */
1822 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1823
1824 /*
1825 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1826 * for ar9280 (0xa20c/b20c 5:0)
1827 */
1828 .xatten1DB = {0x1b, 0x1b, 0x1b},
1829
1830 /*
1831 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1832 * for ar9280 (0xa20c/b20c 16:12
1833 */
1834 .xatten1Margin = {0x15, 0x15, 0x15},
1835 .tempSlope = 50,
1836 .voltSlope = 0,
1837
1838 /*
1839 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1840 * channels in usual fbin coding format
1841 */
1842 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1843
1844 /*
1845 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1846 * if the register is per chain
1847 */
1848 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]1849 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1850 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1851 .xpaBiasLvl = 0,
1852 .txFrameToDataStart = 0x0e,
1853 .txFrameToPaOn = 0x0e,
1854 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1855 .antennaGain = 0,
1856 .switchSettling = 0x2c,
1857 .adcDesiredSize = -30,
1858 .txEndToXpaOff = 0,
1859 .txEndToRxOn = 0x2,
1860 .txFrameToXpaOn = 0xe,
1861 .thresh62 = 28,
1862 .papdRateMaskHt20 = LE32(0x0c80c080),
1863 .papdRateMaskHt40 = LE32(0x0080c080),
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]1864 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1865 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]1866 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1867 },
1868 },
1869 .base_ext1 = {
1870 .ant_div_control = 0,
Rajkumar Manoharan420e2b12012-09-10 17:05:11 +0530[diff] [blame]1871 .future = {0, 0, 0},
1872 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1873 },
1874 .calFreqPier2G = {
1875 FREQ2FBIN(2412, 1),
1876 FREQ2FBIN(2437, 1),
1877 FREQ2FBIN(2472, 1),
1878 },
1879 /* ar9300_cal_data_per_freq_op_loop 2g */
1880 .calPierData2G = {
1881 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1882 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1883 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1884 },
1885 .calTarget_freqbin_Cck = {
1886 FREQ2FBIN(2412, 1),
1887 FREQ2FBIN(2472, 1),
1888 },
1889 .calTarget_freqbin_2G = {
1890 FREQ2FBIN(2412, 1),
1891 FREQ2FBIN(2437, 1),
1892 FREQ2FBIN(2472, 1)
1893 },
1894 .calTarget_freqbin_2GHT20 = {
1895 FREQ2FBIN(2412, 1),
1896 FREQ2FBIN(2437, 1),
1897 FREQ2FBIN(2472, 1)
1898 },
1899 .calTarget_freqbin_2GHT40 = {
1900 FREQ2FBIN(2412, 1),
1901 FREQ2FBIN(2437, 1),
1902 FREQ2FBIN(2472, 1)
1903 },
1904 .calTargetPowerCck = {
1905 /* 1L-5L,5S,11L,11s */
1906 { {38, 38, 38, 38} },
1907 { {38, 38, 38, 38} },
1908 },
1909 .calTargetPower2G = {
1910 /* 6-24,36,48,54 */
1911 { {38, 38, 36, 34} },
1912 { {38, 38, 36, 34} },
1913 { {38, 38, 34, 32} },
1914 },
1915 .calTargetPower2GHT20 = {
1916 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1917 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1918 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1919 },
1920 .calTargetPower2GHT40 = {
1921 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1922 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1923 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1924 },
1925 .ctlIndex_2G = {
1926 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1927 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1928 },
1929 .ctl_freqbin_2G = {
1930 {
1931 FREQ2FBIN(2412, 1),
1932 FREQ2FBIN(2417, 1),
1933 FREQ2FBIN(2457, 1),
1934 FREQ2FBIN(2462, 1)
1935 },
1936 {
1937 FREQ2FBIN(2412, 1),
1938 FREQ2FBIN(2417, 1),
1939 FREQ2FBIN(2462, 1),
1940 0xFF,
1941 },
1942
1943 {
1944 FREQ2FBIN(2412, 1),
1945 FREQ2FBIN(2417, 1),
1946 FREQ2FBIN(2462, 1),
1947 0xFF,
1948 },
1949 {
1950 FREQ2FBIN(2422, 1),
1951 FREQ2FBIN(2427, 1),
1952 FREQ2FBIN(2447, 1),
1953 FREQ2FBIN(2452, 1)
1954 },
1955
1956 {
1957 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1958 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1959 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1960 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1961 },
1962
1963 {
1964 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1965 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1966 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1967 0,
1968 },
1969
1970 {
1971 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1972 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1973 FREQ2FBIN(2472, 1),
1974 0,
1975 },
1976
1977 {
1978 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1979 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1980 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1981 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1982 },
1983
1984 {
1985 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1986 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1987 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1988 },
1989
1990 {
1991 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1992 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1993 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1994 0
1995 },
1996
1997 {
1998 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1999 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2000 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2001 0
2002 },
2003
2004 {
2005 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2006 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2007 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2008 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2009 }
2010 },
2011 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2012 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2013 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2014 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2015
Rajkumar Manoharan15052f812011-07-29 17:38:15 +0530[diff] [blame]2016 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2017 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2018 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2019
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2020 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2021 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2022 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2023
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2024 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2025 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2026 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2027 },
2028 .modalHeader5G = {
2029 /* 4 idle,t1,t2,b (4 bits per setting) */
2030 .antCtrlCommon = LE32(0x110),
2031 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2032 .antCtrlCommon2 = LE32(0x22222),
2033 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2034 .antCtrlChain = {
2035 LE16(0x0), LE16(0x0), LE16(0x0),
2036 },
2037 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2038 .xatten1DB = {0x13, 0x19, 0x17},
2039
2040 /*
2041 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2042 * for merlin (0xa20c/b20c 16:12
2043 */
2044 .xatten1Margin = {0x19, 0x19, 0x19},
2045 .tempSlope = 70,
2046 .voltSlope = 15,
2047 /* spurChans spur channels in usual fbin coding format */
2048 .spurChans = {0, 0, 0, 0, 0},
2049 /* noiseFloorThreshch check if the register is per chain */
2050 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]2051 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2052 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2053 .xpaBiasLvl = 0,
2054 .txFrameToDataStart = 0x0e,
2055 .txFrameToPaOn = 0x0e,
2056 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2057 .antennaGain = 0,
2058 .switchSettling = 0x2d,
2059 .adcDesiredSize = -30,
2060 .txEndToXpaOff = 0,
2061 .txEndToRxOn = 0x2,
2062 .txFrameToXpaOn = 0xe,
2063 .thresh62 = 28,
2064 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2065 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]2066 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2067 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]2068 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2069 },
2070 },
2071 .base_ext2 = {
2072 .tempSlopeLow = 72,
2073 .tempSlopeHigh = 105,
2074 .xatten1DBLow = {0x10, 0x14, 0x10},
2075 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2076 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2077 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2078 },
2079 .calFreqPier5G = {
2080 FREQ2FBIN(5180, 0),
2081 FREQ2FBIN(5220, 0),
2082 FREQ2FBIN(5320, 0),
2083 FREQ2FBIN(5400, 0),
2084 FREQ2FBIN(5500, 0),
2085 FREQ2FBIN(5600, 0),
2086 FREQ2FBIN(5700, 0),
2087 FREQ2FBIN(5785, 0)
2088 },
2089 .calPierData5G = {
2090 {
2091 {0, 0, 0, 0, 0},
2092 {0, 0, 0, 0, 0},
2093 {0, 0, 0, 0, 0},
2094 {0, 0, 0, 0, 0},
2095 {0, 0, 0, 0, 0},
2096 {0, 0, 0, 0, 0},
2097 {0, 0, 0, 0, 0},
2098 {0, 0, 0, 0, 0},
2099 },
2100 {
2101 {0, 0, 0, 0, 0},
2102 {0, 0, 0, 0, 0},
2103 {0, 0, 0, 0, 0},
2104 {0, 0, 0, 0, 0},
2105 {0, 0, 0, 0, 0},
2106 {0, 0, 0, 0, 0},
2107 {0, 0, 0, 0, 0},
2108 {0, 0, 0, 0, 0},
2109 },
2110 {
2111 {0, 0, 0, 0, 0},
2112 {0, 0, 0, 0, 0},
2113 {0, 0, 0, 0, 0},
2114 {0, 0, 0, 0, 0},
2115 {0, 0, 0, 0, 0},
2116 {0, 0, 0, 0, 0},
2117 {0, 0, 0, 0, 0},
2118 {0, 0, 0, 0, 0},
2119 },
2120
2121 },
2122 .calTarget_freqbin_5G = {
2123 FREQ2FBIN(5180, 0),
2124 FREQ2FBIN(5220, 0),
2125 FREQ2FBIN(5320, 0),
2126 FREQ2FBIN(5400, 0),
2127 FREQ2FBIN(5500, 0),
2128 FREQ2FBIN(5600, 0),
2129 FREQ2FBIN(5725, 0),
2130 FREQ2FBIN(5825, 0)
2131 },
2132 .calTarget_freqbin_5GHT20 = {
2133 FREQ2FBIN(5180, 0),
2134 FREQ2FBIN(5220, 0),
2135 FREQ2FBIN(5320, 0),
2136 FREQ2FBIN(5400, 0),
2137 FREQ2FBIN(5500, 0),
2138 FREQ2FBIN(5600, 0),
2139 FREQ2FBIN(5725, 0),
2140 FREQ2FBIN(5825, 0)
2141 },
2142 .calTarget_freqbin_5GHT40 = {
2143 FREQ2FBIN(5180, 0),
2144 FREQ2FBIN(5220, 0),
2145 FREQ2FBIN(5320, 0),
2146 FREQ2FBIN(5400, 0),
2147 FREQ2FBIN(5500, 0),
2148 FREQ2FBIN(5600, 0),
2149 FREQ2FBIN(5725, 0),
2150 FREQ2FBIN(5825, 0)
2151 },
2152 .calTargetPower5G = {
2153 /* 6-24,36,48,54 */
2154 { {32, 32, 28, 26} },
2155 { {32, 32, 28, 26} },
2156 { {32, 32, 28, 26} },
2157 { {32, 32, 26, 24} },
2158 { {32, 32, 26, 24} },
2159 { {32, 32, 24, 22} },
2160 { {30, 30, 24, 22} },
2161 { {30, 30, 24, 22} },
2162 },
2163 .calTargetPower5GHT20 = {
2164 /*
2165 * 0_8_16,1-3_9-11_17-19,
2166 * 4,5,6,7,12,13,14,15,20,21,22,23
2167 */
2168 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2169 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2170 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2171 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2172 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2173 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2174 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2175 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2176 },
2177 .calTargetPower5GHT40 = {
2178 /*
2179 * 0_8_16,1-3_9-11_17-19,
2180 * 4,5,6,7,12,13,14,15,20,21,22,23
2181 */
2182 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2183 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2184 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2185 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2186 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2187 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2188 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2189 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2190 },
2191 .ctlIndex_5G = {
2192 0x10, 0x16, 0x18, 0x40, 0x46,
2193 0x48, 0x30, 0x36, 0x38
2194 },
2195 .ctl_freqbin_5G = {
2196 {
2197 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2198 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2199 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2200 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2201 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2202 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2203 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2204 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2205 },
2206 {
2207 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2208 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2209 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2210 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2211 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2212 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2213 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2214 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2215 },
2216
2217 {
2218 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2219 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2220 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2221 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2222 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2223 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2224 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2225 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2226 },
2227
2228 {
2229 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2230 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2231 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2232 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2233 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2234 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2235 /* Data[3].ctledges[6].bchannel */ 0xFF,
2236 /* Data[3].ctledges[7].bchannel */ 0xFF,
2237 },
2238
2239 {
2240 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2241 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2242 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2243 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2244 /* Data[4].ctledges[4].bchannel */ 0xFF,
2245 /* Data[4].ctledges[5].bchannel */ 0xFF,
2246 /* Data[4].ctledges[6].bchannel */ 0xFF,
2247 /* Data[4].ctledges[7].bchannel */ 0xFF,
2248 },
2249
2250 {
2251 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2252 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2253 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2254 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2255 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2256 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2257 /* Data[5].ctledges[6].bchannel */ 0xFF,
2258 /* Data[5].ctledges[7].bchannel */ 0xFF
2259 },
2260
2261 {
2262 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2263 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2264 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2265 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2266 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2267 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2268 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2269 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2270 },
2271
2272 {
2273 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2274 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2275 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2276 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2277 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2278 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2279 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2280 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2281 },
2282
2283 {
2284 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2285 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2286 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2287 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2288 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2289 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2290 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2291 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2292 }
2293 },
2294 .ctlPowerData_5G = {
2295 {
2296 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2297 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2298 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2299 }
2300 },
2301 {
2302 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2303 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2304 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2305 }
2306 },
2307 {
2308 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2309 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2310 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2311 }
2312 },
2313 {
2314 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2315 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2316 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2317 }
2318 },
2319 {
2320 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2321 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2322 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2323 }
2324 },
2325 {
2326 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2327 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2328 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2329 }
2330 },
2331 {
2332 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2333 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2334 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2335 }
2336 },
2337 {
2338 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2339 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2340 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2341 }
2342 },
2343 {
2344 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2345 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2346 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2347 }
2348 },
2349 }
2350};
2351
2352static const struct ar9300_eeprom ar9300_h116 = {
2353 .eepromVersion = 2,
2354 .templateVersion = 4,
2355 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2356 .custData = {"h116-041-f0000"},
2357 .baseEepHeader = {
2358 .regDmn = { LE16(0), LE16(0x1f) },
2359 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2360 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]2361 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2362 .eepMisc = 0,
2363 },
2364 .rfSilent = 0,
2365 .blueToothOptions = 0,
2366 .deviceCap = 0,
2367 .deviceType = 5, /* takes lower byte in eeprom location */
2368 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2369 .params_for_tuning_caps = {0, 0},
2370 .featureEnable = 0x0d,
2371 /*
2372 * bit0 - enable tx temp comp - disabled
2373 * bit1 - enable tx volt comp - disabled
2374 * bit2 - enable fastClock - enabled
2375 * bit3 - enable doubling - enabled
2376 * bit4 - enable internal regulator - disabled
2377 * bit5 - enable pa predistortion - disabled
2378 */
2379 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2380 .eepromWriteEnableGpio = 6,
2381 .wlanDisableGpio = 0,
2382 .wlanLedGpio = 8,
2383 .rxBandSelectGpio = 0xff,
2384 .txrxgain = 0x10,
2385 .swreg = 0,
2386 },
2387 .modalHeader2G = {
2388 /* ar9300_modal_eep_header 2g */
2389 /* 4 idle,t1,t2,b(4 bits per setting) */
2390 .antCtrlCommon = LE32(0x110),
2391 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2392 .antCtrlCommon2 = LE32(0x44444),
2393
2394 /*
2395 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2396 * rx1, rx12, b (2 bits each)
2397 */
2398 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2399
2400 /*
2401 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2402 * for ar9280 (0xa20c/b20c 5:0)
2403 */
2404 .xatten1DB = {0x1f, 0x1f, 0x1f},
2405
2406 /*
2407 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2408 * for ar9280 (0xa20c/b20c 16:12
2409 */
2410 .xatten1Margin = {0x12, 0x12, 0x12},
2411 .tempSlope = 25,
2412 .voltSlope = 0,
2413
2414 /*
2415 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2416 * channels in usual fbin coding format
2417 */
2418 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2419
2420 /*
2421 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2422 * if the register is per chain
2423 */
2424 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]2425 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2426 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2427 .xpaBiasLvl = 0,
2428 .txFrameToDataStart = 0x0e,
2429 .txFrameToPaOn = 0x0e,
2430 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2431 .antennaGain = 0,
2432 .switchSettling = 0x2c,
2433 .adcDesiredSize = -30,
2434 .txEndToXpaOff = 0,
2435 .txEndToRxOn = 0x2,
2436 .txFrameToXpaOn = 0xe,
2437 .thresh62 = 28,
2438 .papdRateMaskHt20 = LE32(0x0c80C080),
2439 .papdRateMaskHt40 = LE32(0x0080C080),
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]2440 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2441 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]2442 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2443 },
2444 },
2445 .base_ext1 = {
2446 .ant_div_control = 0,
Rajkumar Manoharan420e2b12012-09-10 17:05:11 +0530[diff] [blame]2447 .future = {0, 0, 0},
2448 .tempslopextension = {0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2449 },
2450 .calFreqPier2G = {
2451 FREQ2FBIN(2412, 1),
2452 FREQ2FBIN(2437, 1),
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]2453 FREQ2FBIN(2462, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2454 },
2455 /* ar9300_cal_data_per_freq_op_loop 2g */
2456 .calPierData2G = {
2457 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2458 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2459 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2460 },
2461 .calTarget_freqbin_Cck = {
2462 FREQ2FBIN(2412, 1),
2463 FREQ2FBIN(2472, 1),
2464 },
2465 .calTarget_freqbin_2G = {
2466 FREQ2FBIN(2412, 1),
2467 FREQ2FBIN(2437, 1),
2468 FREQ2FBIN(2472, 1)
2469 },
2470 .calTarget_freqbin_2GHT20 = {
2471 FREQ2FBIN(2412, 1),
2472 FREQ2FBIN(2437, 1),
2473 FREQ2FBIN(2472, 1)
2474 },
2475 .calTarget_freqbin_2GHT40 = {
2476 FREQ2FBIN(2412, 1),
2477 FREQ2FBIN(2437, 1),
2478 FREQ2FBIN(2472, 1)
2479 },
2480 .calTargetPowerCck = {
2481 /* 1L-5L,5S,11L,11S */
2482 { {34, 34, 34, 34} },
2483 { {34, 34, 34, 34} },
2484 },
2485 .calTargetPower2G = {
2486 /* 6-24,36,48,54 */
2487 { {34, 34, 32, 32} },
2488 { {34, 34, 32, 32} },
2489 { {34, 34, 32, 32} },
2490 },
2491 .calTargetPower2GHT20 = {
2492 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2493 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2494 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2495 },
2496 .calTargetPower2GHT40 = {
2497 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2498 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2499 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2500 },
2501 .ctlIndex_2G = {
2502 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2503 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2504 },
2505 .ctl_freqbin_2G = {
2506 {
2507 FREQ2FBIN(2412, 1),
2508 FREQ2FBIN(2417, 1),
2509 FREQ2FBIN(2457, 1),
2510 FREQ2FBIN(2462, 1)
2511 },
2512 {
2513 FREQ2FBIN(2412, 1),
2514 FREQ2FBIN(2417, 1),
2515 FREQ2FBIN(2462, 1),
2516 0xFF,
2517 },
2518
2519 {
2520 FREQ2FBIN(2412, 1),
2521 FREQ2FBIN(2417, 1),
2522 FREQ2FBIN(2462, 1),
2523 0xFF,
2524 },
2525 {
2526 FREQ2FBIN(2422, 1),
2527 FREQ2FBIN(2427, 1),
2528 FREQ2FBIN(2447, 1),
2529 FREQ2FBIN(2452, 1)
2530 },
2531
2532 {
2533 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2534 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2535 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2536 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2537 },
2538
2539 {
2540 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2541 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2542 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2543 0,
2544 },
2545
2546 {
2547 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2548 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2549 FREQ2FBIN(2472, 1),
2550 0,
2551 },
2552
2553 {
2554 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2555 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2556 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2557 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2558 },
2559
2560 {
2561 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2562 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2563 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2564 },
2565
2566 {
2567 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2568 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2569 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2570 0
2571 },
2572
2573 {
2574 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2575 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2576 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2577 0
2578 },
2579
2580 {
2581 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2582 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2583 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2584 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2585 }
2586 },
2587 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2588 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2589 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2590 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2591
Mohammed Shafi Shajakhan81dc6762011-06-17 11:07:32 +0530[diff] [blame]2592 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2593 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2594 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2595
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2596 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2597 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2598 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2599
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2600 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2601 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2602 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2603 },
2604 .modalHeader5G = {
2605 /* 4 idle,t1,t2,b (4 bits per setting) */
2606 .antCtrlCommon = LE32(0x220),
2607 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2608 .antCtrlCommon2 = LE32(0x44444),
2609 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2610 .antCtrlChain = {
2611 LE16(0x150), LE16(0x150), LE16(0x150),
2612 },
2613 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2614 .xatten1DB = {0x19, 0x19, 0x19},
2615
2616 /*
2617 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2618 * for merlin (0xa20c/b20c 16:12
2619 */
2620 .xatten1Margin = {0x14, 0x14, 0x14},
2621 .tempSlope = 70,
2622 .voltSlope = 0,
2623 /* spurChans spur channels in usual fbin coding format */
2624 .spurChans = {0, 0, 0, 0, 0},
2625 /* noiseFloorThreshCh Check if the register is per chain */
2626 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]2627 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2628 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2629 .xpaBiasLvl = 0,
2630 .txFrameToDataStart = 0x0e,
2631 .txFrameToPaOn = 0x0e,
2632 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2633 .antennaGain = 0,
2634 .switchSettling = 0x2d,
2635 .adcDesiredSize = -30,
2636 .txEndToXpaOff = 0,
2637 .txEndToRxOn = 0x2,
2638 .txFrameToXpaOn = 0xe,
2639 .thresh62 = 28,
2640 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2641 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]2642 .xlna_bias_strength = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2643 .futureModal = {
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]2644 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2645 },
2646 },
2647 .base_ext2 = {
2648 .tempSlopeLow = 35,
2649 .tempSlopeHigh = 50,
2650 .xatten1DBLow = {0, 0, 0},
2651 .xatten1MarginLow = {0, 0, 0},
2652 .xatten1DBHigh = {0, 0, 0},
2653 .xatten1MarginHigh = {0, 0, 0}
2654 },
2655 .calFreqPier5G = {
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]2656 FREQ2FBIN(5160, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2657 FREQ2FBIN(5220, 0),
2658 FREQ2FBIN(5320, 0),
2659 FREQ2FBIN(5400, 0),
2660 FREQ2FBIN(5500, 0),
2661 FREQ2FBIN(5600, 0),
2662 FREQ2FBIN(5700, 0),
2663 FREQ2FBIN(5785, 0)
2664 },
2665 .calPierData5G = {
2666 {
2667 {0, 0, 0, 0, 0},
2668 {0, 0, 0, 0, 0},
2669 {0, 0, 0, 0, 0},
2670 {0, 0, 0, 0, 0},
2671 {0, 0, 0, 0, 0},
2672 {0, 0, 0, 0, 0},
2673 {0, 0, 0, 0, 0},
2674 {0, 0, 0, 0, 0},
2675 },
2676 {
2677 {0, 0, 0, 0, 0},
2678 {0, 0, 0, 0, 0},
2679 {0, 0, 0, 0, 0},
2680 {0, 0, 0, 0, 0},
2681 {0, 0, 0, 0, 0},
2682 {0, 0, 0, 0, 0},
2683 {0, 0, 0, 0, 0},
2684 {0, 0, 0, 0, 0},
2685 },
2686 {
2687 {0, 0, 0, 0, 0},
2688 {0, 0, 0, 0, 0},
2689 {0, 0, 0, 0, 0},
2690 {0, 0, 0, 0, 0},
2691 {0, 0, 0, 0, 0},
2692 {0, 0, 0, 0, 0},
2693 {0, 0, 0, 0, 0},
2694 {0, 0, 0, 0, 0},
2695 },
2696
2697 },
2698 .calTarget_freqbin_5G = {
2699 FREQ2FBIN(5180, 0),
2700 FREQ2FBIN(5240, 0),
2701 FREQ2FBIN(5320, 0),
2702 FREQ2FBIN(5400, 0),
2703 FREQ2FBIN(5500, 0),
2704 FREQ2FBIN(5600, 0),
2705 FREQ2FBIN(5700, 0),
2706 FREQ2FBIN(5825, 0)
2707 },
2708 .calTarget_freqbin_5GHT20 = {
2709 FREQ2FBIN(5180, 0),
2710 FREQ2FBIN(5240, 0),
2711 FREQ2FBIN(5320, 0),
2712 FREQ2FBIN(5400, 0),
2713 FREQ2FBIN(5500, 0),
2714 FREQ2FBIN(5700, 0),
2715 FREQ2FBIN(5745, 0),
2716 FREQ2FBIN(5825, 0)
2717 },
2718 .calTarget_freqbin_5GHT40 = {
2719 FREQ2FBIN(5180, 0),
2720 FREQ2FBIN(5240, 0),
2721 FREQ2FBIN(5320, 0),
2722 FREQ2FBIN(5400, 0),
2723 FREQ2FBIN(5500, 0),
2724 FREQ2FBIN(5700, 0),
2725 FREQ2FBIN(5745, 0),
2726 FREQ2FBIN(5825, 0)
2727 },
2728 .calTargetPower5G = {
2729 /* 6-24,36,48,54 */
2730 { {30, 30, 28, 24} },
2731 { {30, 30, 28, 24} },
2732 { {30, 30, 28, 24} },
2733 { {30, 30, 28, 24} },
2734 { {30, 30, 28, 24} },
2735 { {30, 30, 28, 24} },
2736 { {30, 30, 28, 24} },
2737 { {30, 30, 28, 24} },
2738 },
2739 .calTargetPower5GHT20 = {
2740 /*
2741 * 0_8_16,1-3_9-11_17-19,
2742 * 4,5,6,7,12,13,14,15,20,21,22,23
2743 */
2744 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2745 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2746 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2747 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2748 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2749 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2750 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2751 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2752 },
2753 .calTargetPower5GHT40 = {
2754 /*
2755 * 0_8_16,1-3_9-11_17-19,
2756 * 4,5,6,7,12,13,14,15,20,21,22,23
2757 */
2758 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2759 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2760 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2761 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2762 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2763 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2764 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2765 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2766 },
2767 .ctlIndex_5G = {
2768 0x10, 0x16, 0x18, 0x40, 0x46,
2769 0x48, 0x30, 0x36, 0x38
2770 },
2771 .ctl_freqbin_5G = {
2772 {
2773 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2774 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2775 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2776 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2777 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2778 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2779 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2780 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2781 },
2782 {
2783 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2784 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2785 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2786 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2787 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2788 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2789 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2790 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2791 },
2792
2793 {
2794 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2795 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2796 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2797 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2798 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2799 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2800 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2801 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2802 },
2803
2804 {
2805 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2806 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2807 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2808 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2809 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2810 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2811 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2812 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2813 },
2814
2815 {
2816 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2817 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2818 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2819 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2820 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2821 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2822 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2823 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2824 },
2825
2826 {
2827 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2828 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2829 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2830 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2831 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2832 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2833 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2834 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2835 },
2836
2837 {
2838 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2839 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2840 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2841 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2842 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2843 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2844 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2845 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2846 },
2847
2848 {
2849 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2850 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2851 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2852 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2853 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2854 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2855 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2856 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2857 },
2858
2859 {
2860 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2861 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2862 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2863 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2864 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2865 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2866 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2867 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2868 }
2869 },
2870 .ctlPowerData_5G = {
2871 {
2872 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2873 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2874 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2875 }
2876 },
2877 {
2878 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2879 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2880 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2881 }
2882 },
2883 {
2884 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2885 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2886 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2887 }
2888 },
2889 {
2890 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2891 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2892 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2893 }
2894 },
2895 {
2896 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2897 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2898 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2899 }
2900 },
2901 {
2902 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2903 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2904 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2905 }
2906 },
2907 {
2908 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2909 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2910 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2911 }
2912 },
2913 {
2914 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2915 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2916 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2917 }
2918 },
2919 {
2920 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2921 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2922 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2923 }
2924 },
2925 }
2926};
2927
2928
2929static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2930 &ar9300_default,
2931 &ar9300_x112,
2932 &ar9300_h116,
2933 &ar9300_h112,
2934 &ar9300_x113,
2935};
2936
2937static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2938{
2939#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2940 int it;
2941
2942 for (it = 0; it < N_LOOP; it++)
2943 if (ar9300_eep_templates[it]->templateVersion == id)
2944 return ar9300_eep_templates[it];
2945 return NULL;
2946#undef N_LOOP
2947}
2948
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2949static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2950{
2951 return 0;
2952}
2953
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]2954static int interpolate(int x, int xa, int xb, int ya, int yb)
2955{
2956 int bf, factor, plus;
2957
2958 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2959 factor = bf / 2;
2960 plus = bf % 2;
2961 return ya + factor + plus;
2962}
2963
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2964static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2965 enum eeprom_param param)
2966{
2967 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2968 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2969
2970 switch (param) {
2971 case EEP_MAC_LSW:
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]2972 return get_unaligned_be16(eep->macAddr);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2973 case EEP_MAC_MID:
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]2974 return get_unaligned_be16(eep->macAddr + 2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2975 case EEP_MAC_MSW:
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]2976 return get_unaligned_be16(eep->macAddr + 4);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2977 case EEP_REG_0:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]2978 return le16_to_cpu(pBase->regDmn[0]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2979 case EEP_OP_CAP:
2980 return pBase->deviceCap;
2981 case EEP_OP_MODE:
2982 return pBase->opCapFlags.opFlags;
2983 case EEP_RF_SILENT:
2984 return pBase->rfSilent;
2985 case EEP_TX_MASK:
2986 return (pBase->txrxMask >> 4) & 0xf;
2987 case EEP_RX_MASK:
2988 return pBase->txrxMask & 0xf;
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]2989 case EEP_PAPRD:
2990 return !!(pBase->featureEnable & BIT(5));
Mohammed Shafi Shajakhanea066d52010-11-23 20:42:27 +0530[diff] [blame]2991 case EEP_CHAIN_MASK_REDUCE:
2992 return (pBase->miscConfiguration >> 0x3) & 0x1;
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]2993 case EEP_ANT_DIV_CTL1:
Rajkumar Manoharan5479de62011-07-17 11:43:02 +0530[diff] [blame]2994 return eep->base_ext1.ant_div_control;
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame]2995 case EEP_ANTENNA_GAIN_5G:
2996 return eep->modalHeader5G.antennaGain;
2997 case EEP_ANTENNA_GAIN_2G:
2998 return eep->modalHeader2G.antennaGain;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2999 default:
3000 return 0;
3001 }
3002}
3003
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3004static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3005 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3006{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3007 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3008
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3009 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3010 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3011
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3012 *buffer = (val >> (8 * (address % 2))) & 0xff;
3013 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3014}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3015
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3016static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3017 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3018{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3019 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3020
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3021 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3022 return false;
3023
3024 buffer[0] = val >> 8;
3025 buffer[1] = val & 0xff;
3026
3027 return true;
3028}
3029
3030static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3031 int count)
3032{
3033 struct ath_common *common = ath9k_hw_common(ah);
3034 int i;
3035
3036 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3037 ath_dbg(common, EEPROM, "eeprom address not in range\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3038 return false;
3039 }
3040
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3041 /*
3042 * Since we're reading the bytes in reverse order from a little-endian
3043 * word stream, an even address means we only use the lower half of
3044 * the 16-bit word at that address
3045 */
3046 if (address % 2 == 0) {
3047 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3048 goto error;
3049
3050 count--;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3051 }
3052
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3053 for (i = 0; i < count / 2; i++) {
3054 if (!ar9300_eeprom_read_word(common, address, buffer))
3055 goto error;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3056
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3057 address -= 2;
3058 buffer += 2;
3059 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3060
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3061 if (count % 2)
3062 if (!ar9300_eeprom_read_byte(common, address, buffer))
3063 goto error;
3064
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3065 return true;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3066
3067error:
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3068 ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n",
3069 address);
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3070 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3071}
3072
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3073static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3074{
3075 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3076
3077 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3078 AR9300_OTP_STATUS_VALID, 1000))
3079 return false;
3080
3081 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3082 return true;
3083}
3084
3085static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3086 int count)
3087{
3088 u32 data;
3089 int i;
3090
3091 for (i = 0; i < count; i++) {
3092 int offset = 8 * ((address - i) % 4);
3093 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3094 return false;
3095
3096 buffer[i] = (data >> offset) & 0xff;
3097 }
3098
3099 return true;
3100}
3101
3102
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3103static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3104 int *length, int *major, int *minor)
3105{
3106 unsigned long value[4];
3107
3108 value[0] = best[0];
3109 value[1] = best[1];
3110 value[2] = best[2];
3111 value[3] = best[3];
3112 *code = ((value[0] >> 5) & 0x0007);
3113 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3114 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3115 *major = (value[2] & 0x000f);
3116 *minor = (value[3] & 0x00ff);
3117}
3118
3119static u16 ar9300_comp_cksum(u8 *data, int dsize)
3120{
3121 int it, checksum = 0;
3122
3123 for (it = 0; it < dsize; it++) {
3124 checksum += data[it];
3125 checksum &= 0xffff;
3126 }
3127
3128 return checksum;
3129}
3130
3131static bool ar9300_uncompress_block(struct ath_hw *ah,
3132 u8 *mptr,
3133 int mdataSize,
3134 u8 *block,
3135 int size)
3136{
3137 int it;
3138 int spot;
3139 int offset;
3140 int length;
3141 struct ath_common *common = ath9k_hw_common(ah);
3142
3143 spot = 0;
3144
3145 for (it = 0; it < size; it += (length+2)) {
3146 offset = block[it];
3147 offset &= 0xff;
3148 spot += offset;
3149 length = block[it+1];
3150 length &= 0xff;
3151
Luis R. Rodriguez803288e2010-08-30 19:26:32 -0400[diff] [blame]3152 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3153 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3154 "Restore at %d: spot=%d offset=%d length=%d\n",
3155 it, spot, offset, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3156 memcpy(&mptr[spot], &block[it+2], length);
3157 spot += length;
3158 } else if (length > 0) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3159 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3160 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3161 it, spot, offset, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3162 return false;
3163 }
3164 }
3165 return true;
3166}
3167
3168static int ar9300_compress_decision(struct ath_hw *ah,
3169 int it,
3170 int code,
3171 int reference,
3172 u8 *mptr,
3173 u8 *word, int length, int mdata_size)
3174{
3175 struct ath_common *common = ath9k_hw_common(ah);
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3176 const struct ar9300_eeprom *eep = NULL;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3177
3178 switch (code) {
3179 case _CompressNone:
3180 if (length != mdata_size) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3181 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3182 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3183 mdata_size, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3184 return -1;
3185 }
Joe Perches2c208892012-06-04 12:44:17 +0000[diff] [blame]3186 memcpy(mptr, word + COMP_HDR_LEN, length);
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3187 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3188 "restored eeprom %d: uncompressed, length %d\n",
3189 it, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3190 break;
3191 case _CompressBlock:
3192 if (reference == 0) {
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3193 } else {
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3194 eep = ar9003_eeprom_struct_find_by_id(reference);
3195 if (eep == NULL) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3196 ath_dbg(common, EEPROM,
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]3197 "can't find reference eeprom struct %d\n",
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3198 reference);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3199 return -1;
3200 }
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3201 memcpy(mptr, eep, mdata_size);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3202 }
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3203 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3204 "restore eeprom %d: block, reference %d, length %d\n",
3205 it, reference, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3206 ar9300_uncompress_block(ah, mptr, mdata_size,
Joe Perches2c208892012-06-04 12:44:17 +0000[diff] [blame]3207 (word + COMP_HDR_LEN), length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3208 break;
3209 default:
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3210 ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3211 return -1;
3212 }
3213 return 0;
3214}
3215
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3216typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3217 int count);
3218
3219static bool ar9300_check_header(void *data)
3220{
3221 u32 *word = data;
3222 return !(*word == 0 || *word == ~0);
3223}
3224
3225static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3226 int base_addr)
3227{
3228 u8 header[4];
3229
3230 if (!read(ah, base_addr, header, 4))
3231 return false;
3232
3233 return ar9300_check_header(header);
3234}
3235
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3236static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3237 int mdata_size)
3238{
3239 struct ath_common *common = ath9k_hw_common(ah);
3240 u16 *data = (u16 *) mptr;
3241 int i;
3242
3243 for (i = 0; i < mdata_size / 2; i++, data++)
3244 ath9k_hw_nvram_read(common, i, data);
3245
3246 return 0;
3247}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3248/*
3249 * Read the configuration data from the eeprom.
3250 * The data can be put in any specified memory buffer.
3251 *
3252 * Returns -1 on error.
3253 * Returns address of next memory location on success.
3254 */
3255static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3256 u8 *mptr, int mdata_size)
3257{
3258#define MDEFAULT 15
3259#define MSTATE 100
3260 int cptr;
3261 u8 *word;
3262 int code;
3263 int reference, length, major, minor;
3264 int osize;
3265 int it;
3266 u16 checksum, mchecksum;
3267 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkau01967362012-07-15 19:53:29 +0200[diff] [blame]3268 struct ar9300_eeprom *eep;
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3269 eeprom_read_op read;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3270
Felix Fietkau01967362012-07-15 19:53:29 +0200[diff] [blame]3271 if (ath9k_hw_use_flash(ah)) {
3272 u8 txrx;
3273
3274 ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3275
3276 /* check if eeprom contains valid data */
3277 eep = (struct ar9300_eeprom *) mptr;
3278 txrx = eep->baseEepHeader.txrxMask;
3279 if (txrx != 0 && txrx != 0xff)
3280 return 0;
3281 }
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3282
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3283 word = kzalloc(2048, GFP_KERNEL);
3284 if (!word)
Larry Finger1ba45b92011-08-27 13:56:00 -0500[diff] [blame]3285 return -ENOMEM;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3286
3287 memcpy(mptr, &ar9300_default, mdata_size);
3288
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3289 read = ar9300_read_eeprom;
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3290 if (AR_SREV_9485(ah))
3291 cptr = AR9300_BASE_ADDR_4K;
Gabor Juhos5b5c0332011-06-21 11:23:38 +0200[diff] [blame]3292 else if (AR_SREV_9330(ah))
3293 cptr = AR9300_BASE_ADDR_512;
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3294 else
3295 cptr = AR9300_BASE_ADDR;
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3296 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3297 cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3298 if (ar9300_check_eeprom_header(ah, read, cptr))
3299 goto found;
3300
3301 cptr = AR9300_BASE_ADDR_512;
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3302 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3303 cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3304 if (ar9300_check_eeprom_header(ah, read, cptr))
3305 goto found;
3306
3307 read = ar9300_read_otp;
3308 cptr = AR9300_BASE_ADDR;
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3309 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3310 if (ar9300_check_eeprom_header(ah, read, cptr))
3311 goto found;
3312
3313 cptr = AR9300_BASE_ADDR_512;
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3314 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3315 if (ar9300_check_eeprom_header(ah, read, cptr))
3316 goto found;
3317
3318 goto fail;
3319
3320found:
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3321 ath_dbg(common, EEPROM, "Found valid EEPROM data\n");
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3322
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3323 for (it = 0; it < MSTATE; it++) {
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3324 if (!read(ah, cptr, word, COMP_HDR_LEN))
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3325 goto fail;
3326
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3327 if (!ar9300_check_header(word))
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3328 break;
3329
3330 ar9300_comp_hdr_unpack(word, &code, &reference,
3331 &length, &major, &minor);
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3332 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3333 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3334 cptr, code, reference, length, major, minor);
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3335 if ((!AR_SREV_9485(ah) && length >= 1024) ||
Vasanthakumar Thiagarajand0ce2d12010-12-21 01:42:43 -0800[diff] [blame]3336 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3337 ath_dbg(common, EEPROM, "Skipping bad header\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3338 cptr -= COMP_HDR_LEN;
3339 continue;
3340 }
3341
3342 osize = length;
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3343 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3344 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]3345 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3346 ath_dbg(common, EEPROM, "checksum %x %x\n",
3347 checksum, mchecksum);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3348 if (checksum == mchecksum) {
3349 ar9300_compress_decision(ah, it, code, reference, mptr,
3350 word, length, mdata_size);
3351 } else {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3352 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3353 "skipping block with bad checksum\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3354 }
3355 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3356 }
3357
3358 kfree(word);
3359 return cptr;
3360
3361fail:
3362 kfree(word);
3363 return -1;
3364}
3365
3366/*
3367 * Restore the configuration structure by reading the eeprom.
3368 * This function destroys any existing in-memory structure
3369 * content.
3370 */
3371static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3372{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3373 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3374
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3375 if (ar9300_eeprom_restore_internal(ah, mptr,
3376 sizeof(struct ar9300_eeprom)) < 0)
3377 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3378
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3379 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3380}
3381
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3382#if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3383static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3384 struct ar9300_modal_eep_header *modal_hdr)
3385{
3386 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3387 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3388 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3389 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3390 PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3391 PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3392 PR_EEP("Switch Settle", modal_hdr->switchSettling);
3393 PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3394 PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3395 PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3396 PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3397 PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3398 PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3399 PR_EEP("Temp Slope", modal_hdr->tempSlope);
3400 PR_EEP("Volt Slope", modal_hdr->voltSlope);
3401 PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3402 PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3403 PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3404 PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3405 PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3406 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3407 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3408 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3409 PR_EEP("Quick Drop", modal_hdr->quick_drop);
Rajkumar Manoharan202bff02011-11-08 14:19:33 +0530[diff] [blame]3410 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3411 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3412 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3413 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3414 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3415 PR_EEP("txClip", modal_hdr->txClip);
3416 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3417
3418 return len;
3419}
3420
3421static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3422 u8 *buf, u32 len, u32 size)
3423{
3424 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3425 struct ar9300_base_eep_hdr *pBase;
3426
3427 if (!dump_base_hdr) {
3428 len += snprintf(buf + len, size - len,
3429 "%20s :\n", "2GHz modal Header");
Mohammed Shafi Shajakhand25360b2012-05-15 15:24:47 +0530[diff] [blame]3430 len = ar9003_dump_modal_eeprom(buf, len, size,
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3431 &eep->modalHeader2G);
3432 len += snprintf(buf + len, size - len,
3433 "%20s :\n", "5GHz modal Header");
Mohammed Shafi Shajakhand25360b2012-05-15 15:24:47 +0530[diff] [blame]3434 len = ar9003_dump_modal_eeprom(buf, len, size,
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3435 &eep->modalHeader5G);
3436 goto out;
3437 }
3438
3439 pBase = &eep->baseEepHeader;
3440
3441 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3442 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3443 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3444 PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3445 PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3446 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3447 AR5416_OPFLAGS_11A));
3448 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3449 AR5416_OPFLAGS_11G));
3450 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3451 AR5416_OPFLAGS_N_2G_HT20));
3452 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3453 AR5416_OPFLAGS_N_2G_HT40));
3454 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3455 AR5416_OPFLAGS_N_5G_HT20));
3456 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3457 AR5416_OPFLAGS_N_5G_HT40));
3458 PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3459 PR_EEP("RF Silent", pBase->rfSilent);
3460 PR_EEP("BT option", pBase->blueToothOptions);
3461 PR_EEP("Device Cap", pBase->deviceCap);
3462 PR_EEP("Device Type", pBase->deviceType);
3463 PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3464 PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3465 PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3466 PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3467 PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3468 PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3469 PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3470 PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3471 PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3472 PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3473 PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3474 PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3475 PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3476 PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3477 PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3478 PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3479 PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3480 PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3481 PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3482
3483 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3484 ah->eeprom.ar9300_eep.macAddr);
3485out:
3486 if (len > size)
3487 len = size;
3488
3489 return len;
3490}
3491#else
3492static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3493 u8 *buf, u32 len, u32 size)
3494{
3495 return 0;
3496}
3497#endif
3498
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3499/* XXX: review hardware docs */
3500static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3501{
3502 return ah->eeprom.ar9300_eep.eepromVersion;
3503}
3504
3505/* XXX: could be read from the eepromVersion, not sure yet */
3506static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3507{
3508 return 0;
3509}
3510
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3511static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,
3512 bool is2ghz)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3513{
3514 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3515
3516 if (is2ghz)
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3517 return &eep->modalHeader2G;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3518 else
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3519 return &eep->modalHeader5G;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3520}
3521
3522static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3523{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3524 int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3525
Gabor Juhosdc9aa5f2011-06-21 11:23:39 +0200[diff] [blame]3526 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3527 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
Sujith Manoharana4a29542012-09-10 09:20:03 +0530[diff] [blame]3528 else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3529 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3530 else {
3531 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
Rajkumar Manoharan165af962011-05-09 19:11:26 +0530[diff] [blame]3532 REG_RMW_FIELD(ah, AR_CH0_THERM,
3533 AR_CH0_THERM_XPABIASLVL_MSB,
3534 bias >> 2);
3535 REG_RMW_FIELD(ah, AR_CH0_THERM,
3536 AR_CH0_THERM_XPASHORT2GND, 1);
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3537 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3538}
3539
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3540static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3541{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3542 return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3543}
3544
3545
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3546static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3547{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3548 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3549}
3550
3551static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3552{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3553 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3554}
3555
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3556static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3557 bool is2ghz)
3558{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3559 __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain];
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3560 return le16_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3561}
3562
3563static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3564{
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3565 int chain;
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3566 u32 regval;
3567 u32 ant_div_ctl1;
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3568 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3569 AR_PHY_SWITCH_CHAIN_0,
3570 AR_PHY_SWITCH_CHAIN_1,
3571 AR_PHY_SWITCH_CHAIN_2,
3572 };
3573
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3574 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3575
Sujith Manoharana4a29542012-09-10 09:20:03 +0530[diff] [blame]3576 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3577 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]3578 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
Gabor Juhos2d00de42012-07-03 19:13:26 +0200[diff] [blame]3579 } else if (AR_SREV_9550(ah)) {
3580 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3581 AR_SWITCH_TABLE_COM_AR9550_ALL, value);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3582 } else
3583 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3584 AR_SWITCH_TABLE_COM_ALL, value);
3585
3586
3587 /*
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]3588 * AR9462 defines new switch table for BT/WLAN,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3589 * here's new field name in XXX.ref for both 2G and 5G.
3590 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3591 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX
3592 * SWITCH_TABLE_COM_SPDT_WLAN_RX
3593 *
3594 * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX
3595 * SWITCH_TABLE_COM_SPDT_WLAN_TX
3596 *
3597 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3598 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3599 */
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]3600 if (AR_SREV_9462_20_OR_LATER(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3601 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3602 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3603 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
Rajkumar Manoharan9dc08ec2012-06-04 16:28:20 +0530[diff] [blame]3604 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3605 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3606
3607 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3608 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3609
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3610 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3611 if ((ah->rxchainmask & BIT(chain)) ||
3612 (ah->txchainmask & BIT(chain))) {
3613 value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3614 is2ghz);
3615 REG_RMW_FIELD(ah, switch_chain_reg[chain],
3616 AR_SWITCH_TABLE_ALL, value);
3617 }
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3618 }
3619
Sujith Manoharana4a29542012-09-10 09:20:03 +0530[diff] [blame]3620 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3621 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3622 /*
3623 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3624 * are the fields present
3625 */
3626 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3627 regval &= (~AR_ANT_DIV_CTRL_ALL);
3628 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3629 /* enable_lnadiv */
Sujith Manoharan9aa49ea2012-09-11 10:46:38 +0530[diff] [blame^]3630 regval &= (~AR_PHY_ANT_DIV_LNADIV);
3631 regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3632 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3633
3634 /*enable fast_div */
3635 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3636 regval &= (~AR_FAST_DIV_ENABLE);
Sujith Manoharan9aa49ea2012-09-11 10:46:38 +0530[diff] [blame^]3637 regval |= ((value >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3638 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
Sujith Manoharan9aa49ea2012-09-11 10:46:38 +0530[diff] [blame^]3639 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3640 /* check whether antenna diversity is enabled */
3641 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3642 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3643 /*
3644 * clear bits 25-30 main_lnaconf, alt_lnaconf,
3645 * main_tb, alt_tb
3646 */
Sujith Manoharan9aa49ea2012-09-11 10:46:38 +0530[diff] [blame^]3647 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
3648 AR_PHY_ANT_DIV_ALT_LNACONF |
3649 AR_PHY_ANT_DIV_ALT_GAINTB |
3650 AR_PHY_ANT_DIV_MAIN_GAINTB));
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3651 /* by default use LNA1 for the main antenna */
Sujith Manoharan9aa49ea2012-09-11 10:46:38 +0530[diff] [blame^]3652 regval |= (AR_PHY_ANT_DIV_LNA1 <<
3653 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
3654 regval |= (AR_PHY_ANT_DIV_LNA2 <<
3655 AR_PHY_ANT_DIV_ALT_LNACONF_S);
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3656 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3657 }
3658
3659
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3660 }
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3661
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3662}
3663
3664static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3665{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3666 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3667 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3668 int drive_strength;
3669 unsigned long reg;
3670
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3671 drive_strength = pBase->miscConfiguration & BIT(0);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3672 if (!drive_strength)
3673 return;
3674
3675 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3676 reg &= ~0x00ffffc0;
3677 reg |= 0x5 << 21;
3678 reg |= 0x5 << 18;
3679 reg |= 0x5 << 15;
3680 reg |= 0x5 << 12;
3681 reg |= 0x5 << 9;
3682 reg |= 0x5 << 6;
3683 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3684
3685 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3686 reg &= ~0xffffffe0;
3687 reg |= 0x5 << 29;
3688 reg |= 0x5 << 26;
3689 reg |= 0x5 << 23;
3690 reg |= 0x5 << 20;
3691 reg |= 0x5 << 17;
3692 reg |= 0x5 << 14;
3693 reg |= 0x5 << 11;
3694 reg |= 0x5 << 8;
3695 reg |= 0x5 << 5;
3696 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3697
3698 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3699 reg &= ~0xff800000;
3700 reg |= 0x5 << 29;
3701 reg |= 0x5 << 26;
3702 reg |= 0x5 << 23;
3703 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3704}
3705
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3706static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3707 struct ath9k_channel *chan)
3708{
3709 int f[3], t[3];
3710 u16 value;
3711 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3712
3713 if (chain >= 0 && chain < 3) {
3714 if (IS_CHAN_2GHZ(chan))
3715 return eep->modalHeader2G.xatten1DB[chain];
3716 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3717 t[0] = eep->base_ext2.xatten1DBLow[chain];
3718 f[0] = 5180;
3719 t[1] = eep->modalHeader5G.xatten1DB[chain];
3720 f[1] = 5500;
3721 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3722 f[2] = 5785;
3723 value = ar9003_hw_power_interpolate((s32) chan->channel,
3724 f, t, 3);
3725 return value;
3726 } else
3727 return eep->modalHeader5G.xatten1DB[chain];
3728 }
3729
3730 return 0;
3731}
3732
3733
3734static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3735 struct ath9k_channel *chan)
3736{
3737 int f[3], t[3];
3738 u16 value;
3739 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3740
3741 if (chain >= 0 && chain < 3) {
3742 if (IS_CHAN_2GHZ(chan))
3743 return eep->modalHeader2G.xatten1Margin[chain];
3744 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3745 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3746 f[0] = 5180;
3747 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3748 f[1] = 5500;
3749 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3750 f[2] = 5785;
3751 value = ar9003_hw_power_interpolate((s32) chan->channel,
3752 f, t, 3);
3753 return value;
3754 } else
3755 return eep->modalHeader5G.xatten1Margin[chain];
3756 }
3757
3758 return 0;
3759}
3760
3761static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3762{
3763 int i;
3764 u16 value;
3765 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3766 AR_PHY_EXT_ATTEN_CTL_1,
3767 AR_PHY_EXT_ATTEN_CTL_2,
3768 };
3769
3770 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3771 for (i = 0; i < 3; i++) {
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3772 if (ah->txchainmask & BIT(i)) {
3773 value = ar9003_hw_atten_chain_get(ah, i, chan);
3774 REG_RMW_FIELD(ah, ext_atten_reg[i],
3775 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3776
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3777 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3778 REG_RMW_FIELD(ah, ext_atten_reg[i],
3779 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3780 value);
3781 }
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3782 }
3783}
3784
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3785static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3786{
3787 int timeout = 100;
3788
3789 while (pmu_set != REG_READ(ah, pmu_reg)) {
3790 if (timeout-- == 0)
3791 return false;
3792 REG_WRITE(ah, pmu_reg, pmu_set);
3793 udelay(10);
3794 }
3795
3796 return true;
3797}
3798
Felix Fietkaubfc441a2012-05-24 14:32:22 +0200[diff] [blame]3799void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3800{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3801 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3802 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3803 u32 reg_val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3804
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3805 if (pBase->featureEnable & BIT(4)) {
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3806 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3807 int reg_pmu_set;
3808
3809 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3810 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3811 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3812 return;
3813
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3814 if (AR_SREV_9330(ah)) {
3815 if (ah->is_clk_25mhz) {
3816 reg_pmu_set = (3 << 1) | (8 << 4) |
3817 (3 << 8) | (1 << 14) |
3818 (6 << 17) | (1 << 20) |
3819 (3 << 24);
3820 } else {
3821 reg_pmu_set = (4 << 1) | (7 << 4) |
3822 (3 << 8) | (1 << 14) |
3823 (6 << 17) | (1 << 20) |
3824 (3 << 24);
3825 }
3826 } else {
3827 reg_pmu_set = (5 << 1) | (7 << 4) |
Rajkumar Manoharan1fa707a2011-07-29 17:38:17 +0530[diff] [blame]3828 (2 << 8) | (2 << 14) |
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3829 (6 << 17) | (1 << 20) |
3830 (3 << 24) | (1 << 28);
3831 }
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3832
3833 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3834 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3835 return;
3836
3837 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3838 | (4 << 26);
3839 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3840 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3841 return;
3842
3843 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3844 | (1 << 21);
3845 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3846 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3847 return;
Sujith Manoharana4a29542012-09-10 09:20:03 +0530[diff] [blame]3848 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3849 reg_val = le32_to_cpu(pBase->swreg);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3850 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3851 } else {
3852 /* Internal regulator is ON. Write swreg register. */
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3853 reg_val = le32_to_cpu(pBase->swreg);
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3854 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3855 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3856 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3857 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3858 /* Set REG_CONTROL1.SWREG_PROGRAM */
3859 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3860 REG_READ(ah,
3861 AR_RTC_REG_CONTROL1) |
3862 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3863 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3864 } else {
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3865 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3866 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3867 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3868 AR_PHY_PMU2_PGM))
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3869 udelay(10);
3870
3871 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3872 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3873 AR_PHY_PMU1_PWD))
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3874 udelay(10);
3875 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3876 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3877 AR_PHY_PMU2_PGM))
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3878 udelay(10);
Sujith Manoharana4a29542012-09-10 09:20:03 +0530[diff] [blame]3879 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3880 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3881 else {
3882 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3883 AR_RTC_FORCE_SWREG_PRD;
3884 REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3885 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3886 }
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3887
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3888}
3889
Vasanthakumar Thiagarajandd040f72010-12-06 04:27:52 -0800[diff] [blame]3890static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3891{
3892 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3893 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3894
Felix Fietkau08a4a1a2012-07-15 19:53:40 +0200[diff] [blame]3895 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3896 return;
3897
Vasanthakumar Thiagarajandd040f72010-12-06 04:27:52 -0800[diff] [blame]3898 if (eep->baseEepHeader.featureEnable & 0x40) {
3899 tuning_caps_param &= 0x7f;
3900 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3901 tuning_caps_param);
3902 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3903 tuning_caps_param);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3904 }
3905}
3906
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3907static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3908{
3909 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3910 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3911 int quick_drop;
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3912 s32 t[3], f[3] = {5180, 5500, 5785};
3913
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3914 if (!(pBase->miscConfiguration & BIT(1)))
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3915 return;
3916
3917 if (freq < 4000)
3918 quick_drop = eep->modalHeader2G.quick_drop;
3919 else {
3920 t[0] = eep->base_ext1.quick_drop_low;
3921 t[1] = eep->modalHeader5G.quick_drop;
3922 t[2] = eep->base_ext1.quick_drop_high;
3923 quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
3924 }
3925 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
3926}
3927
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3928static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
Rajkumar Manoharan202bff02011-11-08 14:19:33 +0530[diff] [blame]3929{
Rajkumar Manoharan202bff02011-11-08 14:19:33 +0530[diff] [blame]3930 u32 value;
3931
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3932 value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff;
Rajkumar Manoharan202bff02011-11-08 14:19:33 +0530[diff] [blame]3933
3934 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3935 AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
3936 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3937 AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
3938}
3939
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3940static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
Felix Fietkau89be49e2012-07-15 19:53:37 +0200[diff] [blame]3941{
3942 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3943 u8 xpa_ctl;
3944
3945 if (!(eep->baseEepHeader.featureEnable & 0x80))
3946 return;
3947
3948 if (!AR_SREV_9300(ah) && !AR_SREV_9340(ah) && !AR_SREV_9580(ah))
3949 return;
3950
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3951 xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
3952 if (is2ghz)
Felix Fietkau89be49e2012-07-15 19:53:37 +0200[diff] [blame]3953 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3954 AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl);
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]3955 else
Felix Fietkau89be49e2012-07-15 19:53:37 +0200[diff] [blame]3956 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3957 AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
Felix Fietkau89be49e2012-07-15 19:53:37 +0200[diff] [blame]3958}
3959
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]3960static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
3961{
3962 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3963 u8 bias;
3964
3965 if (!(eep->baseEepHeader.featureEnable & 0x40))
3966 return;
3967
3968 if (!AR_SREV_9300(ah))
3969 return;
3970
3971 bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
3972 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3973 bias & 0x3);
3974 bias >>= 2;
3975 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3976 bias & 0x3);
3977 bias >>= 2;
3978 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
3979 bias & 0x3);
3980}
3981
Rajkumar Manoharan02eba422012-09-07 12:15:15 +0530[diff] [blame]3982static int ar9003_hw_get_thermometer(struct ath_hw *ah)
3983{
3984 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3985 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3986 int thermometer = (pBase->miscConfiguration >> 1) & 0x3;
3987
3988 return --thermometer;
3989}
3990
3991static void ar9003_hw_thermometer_apply(struct ath_hw *ah)
3992{
3993 int thermometer = ar9003_hw_get_thermometer(ah);
3994 u8 therm_on = (thermometer < 0) ? 0 : 1;
3995
3996 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4,
3997 AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
3998 if (ah->caps.tx_chainmask & BIT(1))
3999 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4,
4000 AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
4001 if (ah->caps.tx_chainmask & BIT(2))
4002 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
4003 AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR, therm_on);
4004
4005 therm_on = (thermometer < 0) ? 0 : (thermometer == 0);
4006 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4,
4007 AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4008 if (ah->caps.tx_chainmask & BIT(1)) {
4009 therm_on = (thermometer < 0) ? 0 : (thermometer == 1);
4010 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4,
4011 AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4012 }
4013 if (ah->caps.tx_chainmask & BIT(2)) {
4014 therm_on = (thermometer < 0) ? 0 : (thermometer == 2);
4015 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4,
4016 AR_PHY_65NM_CH0_RXTX4_THERM_ON, therm_on);
4017 }
4018}
4019
Rajkumar Manoharan80fe43f2012-09-07 12:15:16 +0530[diff] [blame]4020static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah)
4021{
4022 u32 data, ko, kg;
4023
4024 if (!AR_SREV_9462_20(ah))
4025 return;
4026 ar9300_otp_read_word(ah, 1, &data);
4027 ko = data & 0xff;
4028 kg = (data >> 8) & 0xff;
4029 if (ko || kg) {
4030 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3,
4031 AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET, ko);
4032 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3,
4033 AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN,
4034 kg + 256);
4035 }
4036}
4037
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4038static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
4039 struct ath9k_channel *chan)
4040{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]4041 bool is2ghz = IS_CHAN_2GHZ(chan);
4042 ar9003_hw_xpa_timing_control_apply(ah, is2ghz);
4043 ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
4044 ar9003_hw_ant_ctrl_apply(ah, is2ghz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4045 ar9003_hw_drive_strength_apply(ah);
Felix Fietkau3e2ea542012-07-15 19:53:39 +0200[diff] [blame]4046 ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]4047 ar9003_hw_atten_apply(ah, chan);
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]4048 ar9003_hw_quick_drop_apply(ah, chan->channel);
Gabor Juhos2e2c9cc2012-07-03 19:13:30 +0200[diff] [blame]4049 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
Vasanthakumar Thiagarajan3594bea2011-04-19 19:29:12 +0530[diff] [blame]4050 ar9003_hw_internal_regulator_apply(ah);
Felix Fietkau08a4a1a2012-07-15 19:53:40 +0200[diff] [blame]4051 ar9003_hw_apply_tuning_caps(ah);
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]4052 ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
Rajkumar Manoharan02eba422012-09-07 12:15:15 +0530[diff] [blame]4053 ar9003_hw_thermometer_apply(ah);
Rajkumar Manoharan80fe43f2012-09-07 12:15:16 +0530[diff] [blame]4054 ar9003_hw_thermo_cal_apply(ah);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4055}
4056
4057static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
4058 struct ath9k_channel *chan)
4059{
4060}
4061
4062/*
4063 * Returns the interpolated y value corresponding to the specified x value
4064 * from the np ordered pairs of data (px,py).
4065 * The pairs do not have to be in any order.
4066 * If the specified x value is less than any of the px,
4067 * the returned y value is equal to the py for the lowest px.
4068 * If the specified x value is greater than any of the px,
4069 * the returned y value is equal to the py for the highest px.
4070 */
4071static int ar9003_hw_power_interpolate(int32_t x,
4072 int32_t *px, int32_t *py, u_int16_t np)
4073{
4074 int ip = 0;
4075 int lx = 0, ly = 0, lhave = 0;
4076 int hx = 0, hy = 0, hhave = 0;
4077 int dx = 0;
4078 int y = 0;
4079
4080 lhave = 0;
4081 hhave = 0;
4082
4083 /* identify best lower and higher x calibration measurement */
4084 for (ip = 0; ip < np; ip++) {
4085 dx = x - px[ip];
4086
4087 /* this measurement is higher than our desired x */
4088 if (dx <= 0) {
4089 if (!hhave || dx > (x - hx)) {
4090 /* new best higher x measurement */
4091 hx = px[ip];
4092 hy = py[ip];
4093 hhave = 1;
4094 }
4095 }
4096 /* this measurement is lower than our desired x */
4097 if (dx >= 0) {
4098 if (!lhave || dx < (x - lx)) {
4099 /* new best lower x measurement */
4100 lx = px[ip];
4101 ly = py[ip];
4102 lhave = 1;
4103 }
4104 }
4105 }
4106
4107 /* the low x is good */
4108 if (lhave) {
4109 /* so is the high x */
4110 if (hhave) {
4111 /* they're the same, so just pick one */
4112 if (hx == lx)
4113 y = ly;
4114 else /* interpolate */
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4115 y = interpolate(x, lx, hx, ly, hy);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4116 } else /* only low is good, use it */
4117 y = ly;
4118 } else if (hhave) /* only high is good, use it */
4119 y = hy;
4120 else /* nothing is good,this should never happen unless np=0, ???? */
4121 y = -(1 << 30);
4122 return y;
4123}
4124
4125static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4126 u16 rateIndex, u16 freq, bool is2GHz)
4127{
4128 u16 numPiers, i;
4129 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4130 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4131 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4132 struct cal_tgt_pow_legacy *pEepromTargetPwr;
4133 u8 *pFreqBin;
4134
4135 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]4136 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4137 pEepromTargetPwr = eep->calTargetPower2G;
4138 pFreqBin = eep->calTarget_freqbin_2G;
4139 } else {
4140 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4141 pEepromTargetPwr = eep->calTargetPower5G;
4142 pFreqBin = eep->calTarget_freqbin_5G;
4143 }
4144
4145 /*
4146 * create array of channels and targetpower from
4147 * targetpower piers stored on eeprom
4148 */
4149 for (i = 0; i < numPiers; i++) {
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame]4150 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4151 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4152 }
4153
4154 /* interpolate to get target power for given frequency */
4155 return (u8) ar9003_hw_power_interpolate((s32) freq,
4156 freqArray,
4157 targetPowerArray, numPiers);
4158}
4159
4160static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4161 u16 rateIndex,
4162 u16 freq, bool is2GHz)
4163{
4164 u16 numPiers, i;
4165 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4166 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4167 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4168 struct cal_tgt_pow_ht *pEepromTargetPwr;
4169 u8 *pFreqBin;
4170
4171 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]4172 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4173 pEepromTargetPwr = eep->calTargetPower2GHT20;
4174 pFreqBin = eep->calTarget_freqbin_2GHT20;
4175 } else {
4176 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4177 pEepromTargetPwr = eep->calTargetPower5GHT20;
4178 pFreqBin = eep->calTarget_freqbin_5GHT20;
4179 }
4180
4181 /*
4182 * create array of channels and targetpower
4183 * from targetpower piers stored on eeprom
4184 */
4185 for (i = 0; i < numPiers; i++) {
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame]4186 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4187 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4188 }
4189
4190 /* interpolate to get target power for given frequency */
4191 return (u8) ar9003_hw_power_interpolate((s32) freq,
4192 freqArray,
4193 targetPowerArray, numPiers);
4194}
4195
4196static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4197 u16 rateIndex,
4198 u16 freq, bool is2GHz)
4199{
4200 u16 numPiers, i;
4201 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4202 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4203 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4204 struct cal_tgt_pow_ht *pEepromTargetPwr;
4205 u8 *pFreqBin;
4206
4207 if (is2GHz) {
4208 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4209 pEepromTargetPwr = eep->calTargetPower2GHT40;
4210 pFreqBin = eep->calTarget_freqbin_2GHT40;
4211 } else {
4212 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4213 pEepromTargetPwr = eep->calTargetPower5GHT40;
4214 pFreqBin = eep->calTarget_freqbin_5GHT40;
4215 }
4216
4217 /*
4218 * create array of channels and targetpower from
4219 * targetpower piers stored on eeprom
4220 */
4221 for (i = 0; i < numPiers; i++) {
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame]4222 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4223 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4224 }
4225
4226 /* interpolate to get target power for given frequency */
4227 return (u8) ar9003_hw_power_interpolate((s32) freq,
4228 freqArray,
4229 targetPowerArray, numPiers);
4230}
4231
4232static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4233 u16 rateIndex, u16 freq)
4234{
4235 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4236 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4237 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4238 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4239 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4240 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4241
4242 /*
4243 * create array of channels and targetpower from
4244 * targetpower piers stored on eeprom
4245 */
4246 for (i = 0; i < numPiers; i++) {
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame]4247 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4248 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4249 }
4250
4251 /* interpolate to get target power for given frequency */
4252 return (u8) ar9003_hw_power_interpolate((s32) freq,
4253 freqArray,
4254 targetPowerArray, numPiers);
4255}
4256
4257/* Set tx power registers to array of values passed in */
4258static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4259{
4260#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
4261 /* make sure forced gain is not set */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4262 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4263
4264 /* Write the OFDM power per rate set */
4265
4266 /* 6 (LSB), 9, 12, 18 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4267 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4268 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4269 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4270 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4271 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4272
4273 /* 24 (LSB), 36, 48, 54 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4274 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4275 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4276 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4277 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4278 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4279
4280 /* Write the CCK power per rate set */
4281
4282 /* 1L (LSB), reserved, 2L, 2S (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4283 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4284 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4285 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4286 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
4287 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4288
4289 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4290 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4291 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4292 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4293 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4294 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4295 );
4296
Luis R. Rodriguezcf3a03b2011-05-04 14:01:26 -0700[diff] [blame]4297 /* Write the power for duplicated frames - HT40 */
4298
4299 /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
Alex Hacker8d7763b2011-08-03 17:41:54 +0600[diff] [blame]4300 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
Luis R. Rodriguezcf3a03b2011-05-04 14:01:26 -0700[diff] [blame]4301 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4302 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4303 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4304 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4305 );
4306
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4307 /* Write the HT20 power per rate set */
4308
4309 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4310 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4311 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4312 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4313 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4314 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4315 );
4316
4317 /* 6 (LSB), 7, 12, 13 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4318 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4319 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4320 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4321 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4322 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4323 );
4324
4325 /* 14 (LSB), 15, 20, 21 */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4326 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4327 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4328 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4329 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4330 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4331 );
4332
4333 /* Mixed HT20 and HT40 rates */
4334
4335 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4336 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4337 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4338 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4339 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4340 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4341 );
4342
4343 /*
4344 * Write the HT40 power per rate set
4345 * correct PAR difference between HT40 and HT20/LEGACY
4346 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4347 */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4348 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4349 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4350 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4351 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4352 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4353 );
4354
4355 /* 6 (LSB), 7, 12, 13 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4356 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4357 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4358 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4359 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4360 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4361 );
4362
4363 /* 14 (LSB), 15, 20, 21 */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4364 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4365 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4366 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4367 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4368 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4369 );
4370
4371 return 0;
4372#undef POW_SM
4373}
4374
Gabor Juhos75acd5a2012-04-18 22:23:38 +0200[diff] [blame]4375static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,
4376 u8 *targetPowerValT2,
4377 bool is2GHz)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4378{
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4379 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4380 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4381 is2GHz);
4382 targetPowerValT2[ALL_TARGET_LEGACY_36] =
4383 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4384 is2GHz);
4385 targetPowerValT2[ALL_TARGET_LEGACY_48] =
4386 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4387 is2GHz);
4388 targetPowerValT2[ALL_TARGET_LEGACY_54] =
4389 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4390 is2GHz);
Gabor Juhos75acd5a2012-04-18 22:23:38 +0200[diff] [blame]4391}
4392
4393static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,
4394 u8 *targetPowerValT2)
4395{
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4396 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4397 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4398 freq);
4399 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4400 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4401 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4402 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4403 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4404 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
Gabor Juhos75acd5a2012-04-18 22:23:38 +0200[diff] [blame]4405}
4406
4407static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,
4408 u8 *targetPowerValT2, bool is2GHz)
4409{
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4410 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4411 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4412 is2GHz);
4413 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4414 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4415 freq, is2GHz);
4416 targetPowerValT2[ALL_TARGET_HT20_4] =
4417 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4418 is2GHz);
4419 targetPowerValT2[ALL_TARGET_HT20_5] =
4420 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4421 is2GHz);
4422 targetPowerValT2[ALL_TARGET_HT20_6] =
4423 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4424 is2GHz);
4425 targetPowerValT2[ALL_TARGET_HT20_7] =
4426 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4427 is2GHz);
4428 targetPowerValT2[ALL_TARGET_HT20_12] =
4429 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4430 is2GHz);
4431 targetPowerValT2[ALL_TARGET_HT20_13] =
4432 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4433 is2GHz);
4434 targetPowerValT2[ALL_TARGET_HT20_14] =
4435 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4436 is2GHz);
4437 targetPowerValT2[ALL_TARGET_HT20_15] =
4438 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4439 is2GHz);
4440 targetPowerValT2[ALL_TARGET_HT20_20] =
4441 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4442 is2GHz);
4443 targetPowerValT2[ALL_TARGET_HT20_21] =
4444 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4445 is2GHz);
4446 targetPowerValT2[ALL_TARGET_HT20_22] =
4447 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4448 is2GHz);
4449 targetPowerValT2[ALL_TARGET_HT20_23] =
4450 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4451 is2GHz);
Gabor Juhos75acd5a2012-04-18 22:23:38 +0200[diff] [blame]4452}
4453
4454static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,
4455 u16 freq,
4456 u8 *targetPowerValT2,
4457 bool is2GHz)
4458{
4459 /* XXX: hard code for now, need to get from eeprom struct */
4460 u8 ht40PowerIncForPdadc = 0;
4461
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4462 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4463 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4464 is2GHz) + ht40PowerIncForPdadc;
4465 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4466 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4467 freq,
4468 is2GHz) + ht40PowerIncForPdadc;
4469 targetPowerValT2[ALL_TARGET_HT40_4] =
4470 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4471 is2GHz) + ht40PowerIncForPdadc;
4472 targetPowerValT2[ALL_TARGET_HT40_5] =
4473 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4474 is2GHz) + ht40PowerIncForPdadc;
4475 targetPowerValT2[ALL_TARGET_HT40_6] =
4476 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4477 is2GHz) + ht40PowerIncForPdadc;
4478 targetPowerValT2[ALL_TARGET_HT40_7] =
4479 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4480 is2GHz) + ht40PowerIncForPdadc;
4481 targetPowerValT2[ALL_TARGET_HT40_12] =
4482 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4483 is2GHz) + ht40PowerIncForPdadc;
4484 targetPowerValT2[ALL_TARGET_HT40_13] =
4485 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4486 is2GHz) + ht40PowerIncForPdadc;
4487 targetPowerValT2[ALL_TARGET_HT40_14] =
4488 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4489 is2GHz) + ht40PowerIncForPdadc;
4490 targetPowerValT2[ALL_TARGET_HT40_15] =
4491 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4492 is2GHz) + ht40PowerIncForPdadc;
4493 targetPowerValT2[ALL_TARGET_HT40_20] =
4494 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4495 is2GHz) + ht40PowerIncForPdadc;
4496 targetPowerValT2[ALL_TARGET_HT40_21] =
4497 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4498 is2GHz) + ht40PowerIncForPdadc;
4499 targetPowerValT2[ALL_TARGET_HT40_22] =
4500 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4501 is2GHz) + ht40PowerIncForPdadc;
4502 targetPowerValT2[ALL_TARGET_HT40_23] =
4503 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4504 is2GHz) + ht40PowerIncForPdadc;
Gabor Juhos75acd5a2012-04-18 22:23:38 +0200[diff] [blame]4505}
4506
4507static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,
4508 struct ath9k_channel *chan,
4509 u8 *targetPowerValT2)
4510{
4511 bool is2GHz = IS_CHAN_2GHZ(chan);
4512 unsigned int i = 0;
4513 struct ath_common *common = ath9k_hw_common(ah);
4514 u16 freq = chan->channel;
4515
4516 if (is2GHz)
4517 ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2);
4518
4519 ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz);
4520 ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz);
4521
4522 if (IS_CHAN_HT40(chan))
4523 ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2,
4524 is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4525
Joe Perchesa1cbc7a2010-12-02 19:12:38 -0800[diff] [blame]4526 for (i = 0; i < ar9300RateSize; i++) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4527 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
4528 i, targetPowerValT2[i]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4529 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4530}
4531
4532static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4533 int mode,
4534 int ipier,
4535 int ichain,
4536 int *pfrequency,
4537 int *pcorrection,
4538 int *ptemperature, int *pvoltage)
4539{
4540 u8 *pCalPier;
4541 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4542 int is2GHz;
4543 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4544 struct ath_common *common = ath9k_hw_common(ah);
4545
4546 if (ichain >= AR9300_MAX_CHAINS) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4547 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4548 "Invalid chain index, must be less than %d\n",
4549 AR9300_MAX_CHAINS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4550 return -1;
4551 }
4552
4553 if (mode) { /* 5GHz */
4554 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4555 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4556 "Invalid 5GHz cal pier index, must be less than %d\n",
4557 AR9300_NUM_5G_CAL_PIERS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4558 return -1;
4559 }
4560 pCalPier = &(eep->calFreqPier5G[ipier]);
4561 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4562 is2GHz = 0;
4563 } else {
4564 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4565 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4566 "Invalid 2GHz cal pier index, must be less than %d\n",
4567 AR9300_NUM_2G_CAL_PIERS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4568 return -1;
4569 }
4570
4571 pCalPier = &(eep->calFreqPier2G[ipier]);
4572 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4573 is2GHz = 1;
4574 }
4575
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame]4576 *pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4577 *pcorrection = pCalPierStruct->refPower;
4578 *ptemperature = pCalPierStruct->tempMeas;
4579 *pvoltage = pCalPierStruct->voltMeas;
4580
4581 return 0;
4582}
4583
4584static int ar9003_hw_power_control_override(struct ath_hw *ah,
4585 int frequency,
4586 int *correction,
4587 int *voltage, int *temperature)
4588{
4589 int tempSlope = 0;
4590 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Rajkumar Manoharan420e2b12012-09-10 17:05:11 +0530[diff] [blame]4591 int f[8], t[8], i;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4592
4593 REG_RMW(ah, AR_PHY_TPC_11_B0,
4594 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4595 AR_PHY_TPC_OLPC_GAIN_DELTA);
Vasanthakumar Thiagarajan5f139eb2010-12-06 04:27:53 -0800[diff] [blame]4596 if (ah->caps.tx_chainmask & BIT(1))
4597 REG_RMW(ah, AR_PHY_TPC_11_B1,
4598 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4599 AR_PHY_TPC_OLPC_GAIN_DELTA);
4600 if (ah->caps.tx_chainmask & BIT(2))
4601 REG_RMW(ah, AR_PHY_TPC_11_B2,
4602 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4603 AR_PHY_TPC_OLPC_GAIN_DELTA);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4604
4605 /* enable open loop power control on chip */
4606 REG_RMW(ah, AR_PHY_TPC_6_B0,
4607 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4608 AR_PHY_TPC_6_ERROR_EST_MODE);
Vasanthakumar Thiagarajan5f139eb2010-12-06 04:27:53 -0800[diff] [blame]4609 if (ah->caps.tx_chainmask & BIT(1))
4610 REG_RMW(ah, AR_PHY_TPC_6_B1,
4611 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4612 AR_PHY_TPC_6_ERROR_EST_MODE);
4613 if (ah->caps.tx_chainmask & BIT(2))
4614 REG_RMW(ah, AR_PHY_TPC_6_B2,
4615 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4616 AR_PHY_TPC_6_ERROR_EST_MODE);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4617
4618 /*
4619 * enable temperature compensation
4620 * Need to use register names
4621 */
4622 if (frequency < 4000)
4623 tempSlope = eep->modalHeader2G.tempSlope;
Rajkumar Manoharan420e2b12012-09-10 17:05:11 +0530[diff] [blame]4624 else if ((eep->baseEepHeader.miscConfiguration & 0x20) != 0) {
4625 for (i = 0; i < 8; i++) {
4626 t[i] = eep->base_ext1.tempslopextension[i];
4627 f[i] = FBIN2FREQ(eep->calFreqPier5G[i], 0);
4628 }
4629 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4630 f, t, 8);
4631 } else if (eep->base_ext2.tempSlopeLow != 0) {
Vasanthakumar Thiagarajan15cbbc42010-11-10 05:03:13 -0800[diff] [blame]4632 t[0] = eep->base_ext2.tempSlopeLow;
4633 f[0] = 5180;
4634 t[1] = eep->modalHeader5G.tempSlope;
4635 f[1] = 5500;
4636 t[2] = eep->base_ext2.tempSlopeHigh;
4637 f[2] = 5785;
4638 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4639 f, t, 3);
4640 } else
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4641 tempSlope = eep->modalHeader5G.tempSlope;
4642
4643 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]4644
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]4645 if (AR_SREV_9462_20(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]4646 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4647 AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4648
4649
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4650 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4651 temperature[0]);
4652
4653 return 0;
4654}
4655
4656/* Apply the recorded correction values. */
4657static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4658{
4659 int ichain, ipier, npier;
4660 int mode;
4661 int lfrequency[AR9300_MAX_CHAINS],
4662 lcorrection[AR9300_MAX_CHAINS],
4663 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4664 int hfrequency[AR9300_MAX_CHAINS],
4665 hcorrection[AR9300_MAX_CHAINS],
4666 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4667 int fdiff;
4668 int correction[AR9300_MAX_CHAINS],
4669 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4670 int pfrequency, pcorrection, ptemperature, pvoltage;
4671 struct ath_common *common = ath9k_hw_common(ah);
4672
4673 mode = (frequency >= 4000);
4674 if (mode)
4675 npier = AR9300_NUM_5G_CAL_PIERS;
4676 else
4677 npier = AR9300_NUM_2G_CAL_PIERS;
4678
4679 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4680 lfrequency[ichain] = 0;
4681 hfrequency[ichain] = 100000;
4682 }
4683 /* identify best lower and higher frequency calibration measurement */
4684 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4685 for (ipier = 0; ipier < npier; ipier++) {
4686 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4687 &pfrequency, &pcorrection,
4688 &ptemperature, &pvoltage)) {
4689 fdiff = frequency - pfrequency;
4690
4691 /*
4692 * this measurement is higher than
4693 * our desired frequency
4694 */
4695 if (fdiff <= 0) {
4696 if (hfrequency[ichain] <= 0 ||
4697 hfrequency[ichain] >= 100000 ||
4698 fdiff >
4699 (frequency - hfrequency[ichain])) {
4700 /*
4701 * new best higher
4702 * frequency measurement
4703 */
4704 hfrequency[ichain] = pfrequency;
4705 hcorrection[ichain] =
4706 pcorrection;
4707 htemperature[ichain] =
4708 ptemperature;
4709 hvoltage[ichain] = pvoltage;
4710 }
4711 }
4712 if (fdiff >= 0) {
4713 if (lfrequency[ichain] <= 0
4714 || fdiff <
4715 (frequency - lfrequency[ichain])) {
4716 /*
4717 * new best lower
4718 * frequency measurement
4719 */
4720 lfrequency[ichain] = pfrequency;
4721 lcorrection[ichain] =
4722 pcorrection;
4723 ltemperature[ichain] =
4724 ptemperature;
4725 lvoltage[ichain] = pvoltage;
4726 }
4727 }
4728 }
4729 }
4730 }
4731
4732 /* interpolate */
4733 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4734 ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n",
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4735 ichain, frequency, lfrequency[ichain],
4736 lcorrection[ichain], hfrequency[ichain],
4737 hcorrection[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4738 /* they're the same, so just pick one */
4739 if (hfrequency[ichain] == lfrequency[ichain]) {
4740 correction[ichain] = lcorrection[ichain];
4741 voltage[ichain] = lvoltage[ichain];
4742 temperature[ichain] = ltemperature[ichain];
4743 }
4744 /* the low frequency is good */
4745 else if (frequency - lfrequency[ichain] < 1000) {
4746 /* so is the high frequency, interpolate */
4747 if (hfrequency[ichain] - frequency < 1000) {
4748
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4749 correction[ichain] = interpolate(frequency,
4750 lfrequency[ichain],
4751 hfrequency[ichain],
4752 lcorrection[ichain],
4753 hcorrection[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4754
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4755 temperature[ichain] = interpolate(frequency,
4756 lfrequency[ichain],
4757 hfrequency[ichain],
4758 ltemperature[ichain],
4759 htemperature[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4760
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4761 voltage[ichain] = interpolate(frequency,
4762 lfrequency[ichain],
4763 hfrequency[ichain],
4764 lvoltage[ichain],
4765 hvoltage[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4766 }
4767 /* only low is good, use it */
4768 else {
4769 correction[ichain] = lcorrection[ichain];
4770 temperature[ichain] = ltemperature[ichain];
4771 voltage[ichain] = lvoltage[ichain];
4772 }
4773 }
4774 /* only high is good, use it */
4775 else if (hfrequency[ichain] - frequency < 1000) {
4776 correction[ichain] = hcorrection[ichain];
4777 temperature[ichain] = htemperature[ichain];
4778 voltage[ichain] = hvoltage[ichain];
4779 } else { /* nothing is good, presume 0???? */
4780 correction[ichain] = 0;
4781 temperature[ichain] = 0;
4782 voltage[ichain] = 0;
4783 }
4784 }
4785
4786 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4787 temperature);
4788
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4789 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4790 "for frequency=%d, calibration correction = %d %d %d\n",
4791 frequency, correction[0], correction[1], correction[2]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4792
4793 return 0;
4794}
4795
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4796static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4797 int idx,
4798 int edge,
4799 bool is2GHz)
4800{
4801 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4802 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4803
4804 if (is2GHz)
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4805 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4806 else
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4807 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4808}
4809
4810static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4811 int idx,
4812 unsigned int edge,
4813 u16 freq,
4814 bool is2GHz)
4815{
4816 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4817 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4818
4819 u8 *ctl_freqbin = is2GHz ?
4820 &eep->ctl_freqbin_2G[idx][0] :
4821 &eep->ctl_freqbin_5G[idx][0];
4822
4823 if (is2GHz) {
4824 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4825 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4826 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4827 } else {
4828 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4829 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4830 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4831 }
4832
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4833 return MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4834}
4835
4836/*
4837 * Find the maximum conformance test limit for the given channel and CTL info
4838 */
4839static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4840 u16 freq, int idx, bool is2GHz)
4841{
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4842 u16 twiceMaxEdgePower = MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4843 u8 *ctl_freqbin = is2GHz ?
4844 &eep->ctl_freqbin_2G[idx][0] :
4845 &eep->ctl_freqbin_5G[idx][0];
4846 u16 num_edges = is2GHz ?
4847 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4848 unsigned int edge;
4849
4850 /* Get the edge power */
4851 for (edge = 0;
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4852 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4853 edge++) {
4854 /*
4855 * If there's an exact channel match or an inband flag set
4856 * on the lower channel use the given rdEdgePower
4857 */
4858 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4859 twiceMaxEdgePower =
4860 ar9003_hw_get_direct_edge_power(eep, idx,
4861 edge, is2GHz);
4862 break;
4863 } else if ((edge > 0) &&
4864 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4865 is2GHz))) {
4866 twiceMaxEdgePower =
4867 ar9003_hw_get_indirect_edge_power(eep, idx,
4868 edge, freq,
4869 is2GHz);
4870 /*
4871 * Leave loop - no more affecting edges possible in
4872 * this monotonic increasing list
4873 */
4874 break;
4875 }
4876 }
4877 return twiceMaxEdgePower;
4878}
4879
4880static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4881 struct ath9k_channel *chan,
4882 u8 *pPwrArray, u16 cfgCtl,
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame]4883 u8 antenna_reduction,
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4884 u16 powerLimit)
4885{
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4886 struct ath_common *common = ath9k_hw_common(ah);
4887 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
Rajkumar Manoharana261f0e2011-11-22 18:52:00 +0530[diff] [blame]4888 u16 twiceMaxEdgePower;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4889 int i;
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame]4890 u16 scaledPower = 0, minCtlPower;
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4891 static const u16 ctlModesFor11a[] = {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4892 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4893 };
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4894 static const u16 ctlModesFor11g[] = {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4895 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4896 CTL_11G_EXT, CTL_2GHT40
4897 };
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4898 u16 numCtlModes;
4899 const u16 *pCtlMode;
4900 u16 ctlMode, freq;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4901 struct chan_centers centers;
4902 u8 *ctlIndex;
4903 u8 ctlNum;
4904 u16 twiceMinEdgePower;
4905 bool is2ghz = IS_CHAN_2GHZ(chan);
4906
4907 ath9k_hw_get_channel_centers(ah, chan, &centers);
Gabor Juhosea6f7922012-04-14 22:01:58 +0200[diff] [blame]4908 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
4909 antenna_reduction);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4910
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4911 if (is2ghz) {
4912 /* Setup for CTL modes */
4913 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4914 numCtlModes =
4915 ARRAY_SIZE(ctlModesFor11g) -
4916 SUB_NUM_CTL_MODES_AT_2G_40;
4917 pCtlMode = ctlModesFor11g;
4918 if (IS_CHAN_HT40(chan))
4919 /* All 2G CTL's */
4920 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4921 } else {
4922 /* Setup for CTL modes */
4923 /* CTL_11A, CTL_5GHT20 */
4924 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4925 SUB_NUM_CTL_MODES_AT_5G_40;
4926 pCtlMode = ctlModesFor11a;
4927 if (IS_CHAN_HT40(chan))
4928 /* All 5G CTL's */
4929 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4930 }
4931
4932 /*
4933 * For MIMO, need to apply regulatory caps individually across
4934 * dynamically running modes: CCK, OFDM, HT20, HT40
4935 *
4936 * The outer loop walks through each possible applicable runtime mode.
4937 * The inner loop walks through each ctlIndex entry in EEPROM.
4938 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4939 */
4940 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4941 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4942 (pCtlMode[ctlMode] == CTL_2GHT40);
4943 if (isHt40CtlMode)
4944 freq = centers.synth_center;
4945 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4946 freq = centers.ext_center;
4947 else
4948 freq = centers.ctl_center;
4949
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4950 ath_dbg(common, REGULATORY,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4951 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4952 ctlMode, numCtlModes, isHt40CtlMode,
4953 (pCtlMode[ctlMode] & EXT_ADDITIVE));
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4954
4955 /* walk through each CTL index stored in EEPROM */
4956 if (is2ghz) {
4957 ctlIndex = pEepData->ctlIndex_2G;
4958 ctlNum = AR9300_NUM_CTLS_2G;
4959 } else {
4960 ctlIndex = pEepData->ctlIndex_5G;
4961 ctlNum = AR9300_NUM_CTLS_5G;
4962 }
4963
Rajkumar Manoharana261f0e2011-11-22 18:52:00 +0530[diff] [blame]4964 twiceMaxEdgePower = MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4965 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4966 ath_dbg(common, REGULATORY,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4967 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4968 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4969 chan->channel);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4970
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]4971 /*
4972 * compare test group from regulatory
4973 * channel list with test mode from pCtlMode
4974 * list
4975 */
4976 if ((((cfgCtl & ~CTL_MODE_M) |
4977 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4978 ctlIndex[i]) ||
4979 (((cfgCtl & ~CTL_MODE_M) |
4980 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4981 ((ctlIndex[i] & CTL_MODE_M) |
4982 SD_NO_CTL))) {
4983 twiceMinEdgePower =
4984 ar9003_hw_get_max_edge_power(pEepData,
4985 freq, i,
4986 is2ghz);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4987
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]4988 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4989 /*
4990 * Find the minimum of all CTL
4991 * edge powers that apply to
4992 * this channel
4993 */
4994 twiceMaxEdgePower =
4995 min(twiceMaxEdgePower,
4996 twiceMinEdgePower);
4997 else {
4998 /* specific */
4999 twiceMaxEdgePower = twiceMinEdgePower;
5000 break;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5001 }
5002 }
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5003 }
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5004
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5005 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5006
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5007 ath_dbg(common, REGULATORY,
5008 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
5009 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
5010 scaledPower, minCtlPower);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5011
Gabor Juhos2a0b50c2012-08-02 16:00:52 +0200[diff] [blame]5012 /* Apply ctl mode to correct target power set */
5013 switch (pCtlMode[ctlMode]) {
5014 case CTL_11B:
5015 for (i = ALL_TARGET_LEGACY_1L_5L;
5016 i <= ALL_TARGET_LEGACY_11S; i++)
5017 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5018 minCtlPower);
5019 break;
5020 case CTL_11A:
5021 case CTL_11G:
5022 for (i = ALL_TARGET_LEGACY_6_24;
5023 i <= ALL_TARGET_LEGACY_54; i++)
5024 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5025 minCtlPower);
5026 break;
5027 case CTL_5GHT20:
5028 case CTL_2GHT20:
5029 for (i = ALL_TARGET_HT20_0_8_16;
5030 i <= ALL_TARGET_HT20_23; i++)
5031 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5032 minCtlPower);
5033 break;
5034 case CTL_5GHT40:
5035 case CTL_2GHT40:
5036 for (i = ALL_TARGET_HT40_0_8_16;
5037 i <= ALL_TARGET_HT40_23; i++)
5038 pPwrArray[i] = (u8)min((u16)pPwrArray[i],
5039 minCtlPower);
5040 break;
5041 default:
5042 break;
5043 }
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5044 } /* end ctl mode checking */
5045}
5046
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -0800[diff] [blame]5047static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
5048{
5049 u8 mod_idx = mcs_idx % 8;
5050
5051 if (mod_idx <= 3)
5052 return mod_idx ? (base_pwridx + 1) : base_pwridx;
5053 else
5054 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
5055}
5056
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5057static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
5058 struct ath9k_channel *chan, u16 cfgCtl,
5059 u8 twiceAntennaReduction,
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5060 u8 powerLimit, bool test)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5061{
Felix Fietkau6b7b6cf2010-10-20 02:09:44 +0200[diff] [blame]5062 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5063 struct ath_common *common = ath9k_hw_common(ah);
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5064 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]5065 struct ar9300_modal_eep_header *modal_hdr;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5066 u8 targetPowerValT2[ar9300RateSize];
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5067 u8 target_power_val_t2_eep[ar9300RateSize];
5068 unsigned int i = 0, paprd_scale_factor = 0;
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -0800[diff] [blame]5069 u8 pwr_idx, min_pwridx = 0;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5070
Gabor Juhos75acd5a2012-04-18 22:23:38 +0200[diff] [blame]5071 memset(targetPowerValT2, 0 , sizeof(targetPowerValT2));
5072
5073 /*
5074 * Get target powers from EEPROM - our baseline for TX Power
5075 */
5076 ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2);
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5077
5078 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5079 if (IS_CHAN_2GHZ(chan))
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]5080 modal_hdr = &eep->modalHeader2G;
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5081 else
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]5082 modal_hdr = &eep->modalHeader5G;
5083
5084 ah->paprd_ratemask =
5085 le32_to_cpu(modal_hdr->papdRateMaskHt20) &
5086 AR9300_PAPRD_RATE_MASK;
5087
5088 ah->paprd_ratemask_ht40 =
5089 le32_to_cpu(modal_hdr->papdRateMaskHt40) &
5090 AR9300_PAPRD_RATE_MASK;
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5091
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -0800[diff] [blame]5092 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5093 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5094 ALL_TARGET_HT20_0_8_16;
5095
5096 if (!ah->paprd_table_write_done) {
5097 memcpy(target_power_val_t2_eep, targetPowerValT2,
5098 sizeof(targetPowerValT2));
5099 for (i = 0; i < 24; i++) {
5100 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5101 if (ah->paprd_ratemask & (1 << i)) {
5102 if (targetPowerValT2[pwr_idx] &&
5103 targetPowerValT2[pwr_idx] ==
5104 target_power_val_t2_eep[pwr_idx])
5105 targetPowerValT2[pwr_idx] -=
5106 paprd_scale_factor;
5107 }
5108 }
5109 }
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5110 memcpy(target_power_val_t2_eep, targetPowerValT2,
5111 sizeof(targetPowerValT2));
5112 }
5113
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5114 ar9003_hw_set_power_per_rate_table(ah, chan,
5115 targetPowerValT2, cfgCtl,
5116 twiceAntennaReduction,
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5117 powerLimit);
5118
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5119 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5120 for (i = 0; i < ar9300RateSize; i++) {
5121 if ((ah->paprd_ratemask & (1 << i)) &&
5122 (abs(targetPowerValT2[i] -
5123 target_power_val_t2_eep[i]) >
5124 paprd_scale_factor)) {
5125 ah->paprd_ratemask &= ~(1 << i);
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]5126 ath_dbg(common, EEPROM,
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5127 "paprd disabled for mcs %d\n", i);
5128 }
5129 }
5130 }
5131
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5132 regulatory->max_power_level = 0;
5133 for (i = 0; i < ar9300RateSize; i++) {
5134 if (targetPowerValT2[i] > regulatory->max_power_level)
5135 regulatory->max_power_level = targetPowerValT2[i];
5136 }
5137
Rajkumar Manoharan8915f982011-11-10 15:14:57 +0530[diff] [blame]5138 ath9k_hw_update_regulatory_maxpower(ah);
5139
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5140 if (test)
5141 return;
5142
5143 for (i = 0; i < ar9300RateSize; i++) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]5144 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
5145 i, targetPowerValT2[i]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5146 }
5147
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5148 /* Write target power array to registers */
5149 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5150 ar9003_hw_calibration_apply(ah, chan->channel);
Felix Fietkau1bf38662010-12-13 08:40:54 +0100[diff] [blame]5151
5152 if (IS_CHAN_2GHZ(chan)) {
5153 if (IS_CHAN_HT40(chan))
5154 i = ALL_TARGET_HT40_0_8_16;
5155 else
5156 i = ALL_TARGET_HT20_0_8_16;
5157 } else {
5158 if (IS_CHAN_HT40(chan))
5159 i = ALL_TARGET_HT40_7;
5160 else
5161 i = ALL_TARGET_HT20_7;
5162 }
5163 ah->paprd_target_power = targetPowerValT2[i];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5164}
5165
5166static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5167 u16 i, bool is2GHz)
5168{
5169 return AR_NO_SPUR;
5170}
5171
Luis R. Rodriguezc14a85d2010-04-15 17:39:21 -0400[diff] [blame]5172s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5173{
5174 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5175
5176 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5177}
5178
5179s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5180{
5181 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5182
5183 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5184}
5185
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]5186u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz)
Vasanthakumar Thiagarajan272ceba2010-12-06 04:27:46 -0800[diff] [blame]5187{
Felix Fietkau0aefc592012-07-15 19:53:38 +0200[diff] [blame]5188 return ar9003_modal_header(ah, is2ghz)->spurChans;
Vasanthakumar Thiagarajan272ceba2010-12-06 04:27:46 -0800[diff] [blame]5189}
5190
Vasanthakumar Thiagarajan8698bca2010-12-15 07:30:51 -0800[diff] [blame]5191unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5192 struct ath9k_channel *chan)
5193{
5194 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5195
5196 if (IS_CHAN_2GHZ(chan))
5197 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5198 AR9300_PAPRD_SCALE_1);
5199 else {
5200 if (chan->channel >= 5700)
5201 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5202 AR9300_PAPRD_SCALE_1);
5203 else if (chan->channel >= 5400)
5204 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5205 AR9300_PAPRD_SCALE_2);
5206 else
5207 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5208 AR9300_PAPRD_SCALE_1);
5209 }
5210}
5211
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5212const struct eeprom_ops eep_ar9300_ops = {
5213 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5214 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5215 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]5216 .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5217 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5218 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5219 .set_board_values = ath9k_hw_ar9300_set_board_values,
5220 .set_addac = ath9k_hw_ar9300_set_addac,
5221 .set_txpower = ath9k_hw_ar9300_set_txpower,
5222 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5223};