Luca Weiss | 9b02244 | 2023-04-14 14:47:36 +0200 | [diff] [blame^] | 1 | #include <dt-bindings/gpio/gpio.h> |
| 2 | #include <dt-bindings/iio/qcom,spmi-vadc.h> |
| 3 | #include <dt-bindings/input/input.h> |
| 4 | #include "bengal-audio-overlay.dtsi" |
| 5 | #include "bengal-thermal-overlay.dtsi" |
| 6 | #include "bengal-sde-display.dtsi" |
| 7 | #include "camera/bengal-camera-sensor-idp.dtsi" |
| 8 | |
| 9 | &qupv3_se1_i2c { |
| 10 | status = "ok"; |
| 11 | #include "smb1355.dtsi" |
| 12 | }; |
| 13 | |
| 14 | &qupv3_se4_2uart { |
| 15 | status = "ok"; |
| 16 | }; |
| 17 | |
| 18 | &pm6125_vadc { |
| 19 | pinctrl-0 = <&camera_therm_default &emmc_therm_default &rf_pa1_therm_default>; |
| 20 | |
| 21 | rf_pa1_therm { |
| 22 | reg = <ADC_GPIO4_PU2>; |
| 23 | label = "rf_pa1_therm"; |
| 24 | qcom,ratiometric; |
| 25 | qcom,hw-settle-time = <200>; |
| 26 | qcom,pre-scaling = <1 1>; |
| 27 | }; |
| 28 | }; |
| 29 | |
| 30 | &pm6125_adc_tm { |
| 31 | io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>, |
| 32 | <&pm6125_vadc ADC_AMUX_THM2_PU2>, |
| 33 | <&pm6125_vadc ADC_XO_THERM_PU2>, |
| 34 | <&pm6125_vadc ADC_GPIO4_PU2>; |
| 35 | |
| 36 | rf_pa1_therm { |
| 37 | reg = <ADC_GPIO4_PU2>; |
| 38 | qcom,ratiometric; |
| 39 | qcom,hw-settle-time = <200>; |
| 40 | }; |
| 41 | }; |
| 42 | |
| 43 | &thermal_zones { |
| 44 | rf-pa1-therm-usr { |
| 45 | polling-delay-passive = <0>; |
| 46 | polling-delay = <0>; |
| 47 | thermal-governor = "user_space"; |
| 48 | thermal-sensors = <&pm6125_adc_tm ADC_GPIO4_PU2>; |
| 49 | wake-capable-sensor; |
| 50 | trips { |
| 51 | active-config0 { |
| 52 | temperature = <125000>; |
| 53 | hysteresis = <1000>; |
| 54 | type = "passive"; |
| 55 | }; |
| 56 | }; |
| 57 | }; |
| 58 | }; |
| 59 | |
| 60 | &pm6125_gpios { |
| 61 | |
| 62 | rf_pa1_therm { |
| 63 | rf_pa1_therm_default: rf_pa1_therm_default { |
| 64 | pins = "gpio7"; |
| 65 | bias-high-impedance; |
| 66 | }; |
| 67 | }; |
| 68 | |
| 69 | key_vol_up { |
| 70 | key_vol_up_default: key_vol_up_default { |
| 71 | pins = "gpio5"; |
| 72 | function = "normal"; |
| 73 | input-enable; |
| 74 | bias-pull-up; |
| 75 | power-source = <0>; |
| 76 | }; |
| 77 | }; |
| 78 | }; |
| 79 | |
| 80 | &soc { |
| 81 | gpio_keys { |
| 82 | compatible = "gpio-keys"; |
| 83 | label = "gpio-keys"; |
| 84 | |
| 85 | pinctrl-names = "default"; |
| 86 | pinctrl-0 = <&key_vol_up_default>; |
| 87 | |
| 88 | vol_up { |
| 89 | label = "volume_up"; |
| 90 | gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; |
| 91 | linux,input-type = <1>; |
| 92 | linux,code = <KEY_VOLUMEUP>; |
| 93 | linux,can-disable; |
| 94 | debounce-interval = <15>; |
| 95 | gpio-key,wakeup; |
| 96 | }; |
| 97 | }; |
| 98 | }; |
| 99 | |
| 100 | &qupv3_se1_i2c { |
| 101 | status = "ok"; |
| 102 | #address-cells = <1>; |
| 103 | #size-cells = <0>; |
| 104 | nq@28 { |
| 105 | compatible = "qcom,nq-nci"; |
| 106 | reg = <0x28>; |
| 107 | qcom,nq-irq = <&tlmm 70 0x00>; |
| 108 | qcom,nq-ven = <&tlmm 69 0x00>; |
| 109 | qcom,nq-firm = <&tlmm 31 0x00>; |
| 110 | qcom,nq-clkreq = <&tlmm 86 0x00>; |
| 111 | interrupt-parent = <&tlmm>; |
| 112 | interrupts = <70 0>; |
| 113 | interrupt-names = "nfc_irq"; |
| 114 | pinctrl-names = "nfc_active", "nfc_suspend"; |
| 115 | pinctrl-0 = <&nfc_int_active &nfc_enable_active |
| 116 | &nfc_clk_req_active>; |
| 117 | pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend |
| 118 | &nfc_clk_req_suspend>; |
| 119 | }; |
| 120 | }; |
| 121 | |
| 122 | &tlmm { |
| 123 | smb_int_default: smb_int_default { |
| 124 | mux { |
| 125 | pins = "gpio105"; |
| 126 | function = "gpio"; |
| 127 | }; |
| 128 | |
| 129 | config { |
| 130 | pins = "gpio105"; |
| 131 | bias-pull-up; |
| 132 | input-enable; |
| 133 | }; |
| 134 | }; |
| 135 | }; |
| 136 | |
| 137 | &sdhc_1 { |
| 138 | vdd-supply = <&L24A>; |
| 139 | qcom,vdd-voltage-level = <2960000 2960000>; |
| 140 | qcom,vdd-current-level = <0 570000>; |
| 141 | |
| 142 | vdd-io-supply = <&L11A>; |
| 143 | qcom,vdd-io-always-on; |
| 144 | qcom,vdd-io-lpm-sup; |
| 145 | qcom,vdd-io-voltage-level = <1800000 1800000>; |
| 146 | qcom,vdd-io-current-level = <0 325000>; |
| 147 | |
| 148 | pinctrl-names = "active", "sleep"; |
| 149 | pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on |
| 150 | &sdc1_rclk_on>; |
| 151 | pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off |
| 152 | &sdc1_rclk_off>; |
| 153 | |
| 154 | status = "ok"; |
| 155 | }; |
| 156 | |
| 157 | &sdhc_2 { |
| 158 | vdd-supply = <&L22A>; |
| 159 | qcom,vdd-voltage-level = <2960000 2960000>; |
| 160 | qcom,vdd-current-level = <0 800000>; |
| 161 | |
| 162 | vdd-io-supply = <&L5A>; |
| 163 | qcom,vdd-io-voltage-level = <1800000 2960000>; |
| 164 | qcom,vdd-io-current-level = <0 22000>; |
| 165 | |
| 166 | vdd-io-bias-supply = <&L7A>; |
| 167 | qcom,vdd-io-bias-voltage-level = <1256000 1256000>; |
| 168 | qcom,vdd-io-bias-current-level = <0 6000>; |
| 169 | |
| 170 | pinctrl-names = "active", "sleep"; |
| 171 | pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; |
| 172 | pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; |
| 173 | |
| 174 | cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; |
| 175 | |
| 176 | status = "ok"; |
| 177 | }; |
| 178 | |
| 179 | &ufsphy_mem { |
| 180 | compatible = "qcom,ufs-phy-qmp-v3-660"; |
| 181 | |
| 182 | vdda-phy-supply = <&L4A>; /* 0.9v */ |
| 183 | vdda-pll-supply = <&L12A>; /* 1.8v */ |
| 184 | vdda-phy-max-microamp = <51400>; |
| 185 | vdda-pll-max-microamp = <14200>; |
| 186 | |
| 187 | status = "ok"; |
| 188 | }; |
| 189 | |
| 190 | &ufshc_mem { |
| 191 | vdd-hba-supply = <&gcc_ufs_phy_gdsc>; |
| 192 | vdd-hba-fixed-regulator; |
| 193 | vcc-supply = <&L24A>; |
| 194 | vcc-voltage-level = <2950000 2960000>; |
| 195 | vccq2-supply = <&L11A>; |
| 196 | vcc-max-microamp = <600000>; |
| 197 | vccq2-max-microamp = <600000>; |
| 198 | vccq2-pwr-collapse-sup; |
| 199 | |
| 200 | qcom,vddp-ref-clk-supply = <&L18A>; |
| 201 | qcom,vddp-ref-clk-max-microamp = <100>; |
| 202 | qcom,vddp-ref-clk-min-uV = <1232000>; |
| 203 | qcom,vddp-ref-clk-max-uV = <1232000>; |
| 204 | |
| 205 | status = "ok"; |
| 206 | }; |
| 207 | |
| 208 | &pm6125_pwm { |
| 209 | status = "ok"; |
| 210 | }; |
| 211 | |
| 212 | &dsi_td4330_truly_v2_video { |
| 213 | qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; |
| 214 | qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; |
| 215 | pwms = <&pm6125_pwm 0 0>; |
| 216 | qcom,bl-pmic-pwm-period-usecs = <100>; |
| 217 | qcom,mdss-dsi-bl-min-level = <1>; |
| 218 | qcom,mdss-dsi-bl-max-level = <4095>; |
| 219 | qcom,platform-reset-gpio = <&tlmm 82 0>; |
| 220 | }; |
| 221 | |
| 222 | &dsi_td4330_truly_v2_cmd { |
| 223 | qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; |
| 224 | qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; |
| 225 | pwms = <&pm6125_pwm 0 0>; |
| 226 | qcom,bl-pmic-pwm-period-usecs = <100>; |
| 227 | qcom,mdss-dsi-bl-min-level = <1>; |
| 228 | qcom,mdss-dsi-bl-max-level = <4095>; |
| 229 | qcom,platform-te-gpio = <&tlmm 81 0>; |
| 230 | qcom,platform-reset-gpio = <&tlmm 82 0>; |
| 231 | }; |
| 232 | |
| 233 | &dsi_nt36525_truly_video { |
| 234 | qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; |
| 235 | qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm"; |
| 236 | pwms = <&pm6125_pwm 0 0>; |
| 237 | qcom,bl-pmic-pwm-period-usecs = <100>; |
| 238 | qcom,mdss-dsi-bl-min-level = <1>; |
| 239 | qcom,mdss-dsi-bl-max-level = <4095>; |
| 240 | qcom,platform-reset-gpio = <&tlmm 82 0>; |
| 241 | }; |
| 242 | |
| 243 | &dsi_r66451_amoled_hd_90hz_video { |
| 244 | qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; |
| 245 | qcom,mdss-dsi-bl-min-level = <1>; |
| 246 | qcom,mdss-dsi-bl-max-level = <4095>; |
| 247 | qcom,platform-reset-gpio = <&tlmm 82 0>; |
| 248 | qcom,platform-en-gpio = <&tlmm 83 0>; |
| 249 | }; |
| 250 | |
| 251 | &dsi_r66451_amoled_hd_90hz_cmd { |
| 252 | qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; |
| 253 | qcom,mdss-dsi-bl-min-level = <1>; |
| 254 | qcom,mdss-dsi-bl-max-level = <4095>; |
| 255 | qcom,platform-te-gpio = <&tlmm 81 0>; |
| 256 | qcom,platform-reset-gpio = <&tlmm 82 0>; |
| 257 | qcom,platform-en-gpio = <&tlmm 83 0>; |
| 258 | }; |
| 259 | |
| 260 | &sde_dsi { |
| 261 | qcom,dsi-default-panel = <&dsi_td4330_truly_v2_video>; |
| 262 | }; |
| 263 | |
| 264 | &tlmm { |
| 265 | touch_vdd_default: touch_vdd_default { |
| 266 | mux { |
| 267 | pins = "gpio84"; |
| 268 | function = "gpio"; |
| 269 | }; |
| 270 | |
| 271 | config { |
| 272 | pins = "gpio84"; |
| 273 | drive-strength = <8>; |
| 274 | bias-disable = <0>; |
| 275 | output-high; |
| 276 | }; |
| 277 | }; |
| 278 | }; |
| 279 | |
| 280 | &soc { |
| 281 | touch_vdd: touch_vdd { |
| 282 | compatible = "regulator-fixed"; |
| 283 | regulator-name = "touch_vdd"; |
| 284 | regulator-min-microvolt = <3300000>; |
| 285 | regulator-max-microvolt = <3300000>; |
| 286 | gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>; |
| 287 | enable-active-high; |
| 288 | pinctrl-names = "default"; |
| 289 | pinctrl-0 = <&touch_vdd_default>; |
| 290 | }; |
| 291 | }; |
| 292 | |
| 293 | &qupv3_se2_i2c { |
| 294 | status = "okay"; |
| 295 | qcom,i2c-touch-active="synaptics,tcm-i2c"; |
| 296 | |
| 297 | synaptics_tcm@20 { |
| 298 | compatible = "synaptics,tcm-i2c"; |
| 299 | reg = <0x20>; |
| 300 | interrupt-parent = <&tlmm>; |
| 301 | interrupts = <80 0x2008>; |
| 302 | pinctrl-names = "pmx_ts_active","pmx_ts_suspend", |
| 303 | "pmx_ts_release"; |
| 304 | pinctrl-0 = <&ts_int_active &ts_reset_active>; |
| 305 | pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; |
| 306 | pinctrl-2 = <&ts_release>; |
| 307 | synaptics,irq-gpio = <&tlmm 80 0x2008>; |
| 308 | synaptics,irq-on-state = <0>; |
| 309 | synaptics,reset-gpio = <&tlmm 71 0x00>; |
| 310 | synaptics,reset-on-state = <0>; |
| 311 | synaptics,reset-active-ms = <20>; |
| 312 | synaptics,reset-delay-ms = <200>; |
| 313 | synaptics,power-delay-ms = <200>; |
| 314 | synaptics,ubl-i2c-addr = <0x20>; |
| 315 | synaptics,extend_report; |
| 316 | synaptics,firmware-name = "synaptics_firmware_k.img"; |
| 317 | |
| 318 | panel = <&dsi_td4330_truly_v2_video &dsi_td4330_truly_v2_cmd>; |
| 319 | }; |
| 320 | |
| 321 | novatek@62 { |
| 322 | compatible = "novatek,NVT-ts"; |
| 323 | reg = <0x62>; |
| 324 | status = "ok"; |
| 325 | |
| 326 | interrupt-parent = <&tlmm>; |
| 327 | interrupts = <80 0x2008>; |
| 328 | pinctrl-names = "pmx_ts_active","pmx_ts_suspend", |
| 329 | "pmx_ts_release"; |
| 330 | pinctrl-0 = <&ts_int_active &ts_reset_active>; |
| 331 | pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; |
| 332 | pinctrl-2 = <&ts_release>; |
| 333 | |
| 334 | novatek,reset-gpio = <&tlmm 71 0x00>; |
| 335 | novatek,irq-gpio = <&tlmm 80 0x2008>; |
| 336 | |
| 337 | panel = <&dsi_nt36525_truly_video>; |
| 338 | }; |
| 339 | |
| 340 | focaltech@38 { |
| 341 | compatible = "focaltech,fts_ts"; |
| 342 | reg = <0x38>; |
| 343 | interrupt-parent = <&tlmm>; |
| 344 | interrupts = <80 0x2008>; |
| 345 | focaltech,reset-gpio = <&tlmm 71 0x00>; |
| 346 | focaltech,irq-gpio = <&tlmm 80 0x2008>; |
| 347 | focaltech,max-touch-number = <5>; |
| 348 | focaltech,display-coords = <0 0 1080 2340>; |
| 349 | |
| 350 | vdd-supply = <&touch_vdd>; |
| 351 | |
| 352 | pinctrl-names = "pmx_ts_active","pmx_ts_suspend", |
| 353 | "pmx_ts_release"; |
| 354 | pinctrl-0 = <&ts_int_active &ts_reset_active>; |
| 355 | pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; |
| 356 | pinctrl-2 = <&ts_release>; |
| 357 | |
| 358 | panel = <&dsi_r66451_amoled_hd_90hz_video |
| 359 | &dsi_r66451_amoled_hd_90hz_cmd>; |
| 360 | }; |
| 361 | }; |