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gerrit-public.fairphone.software / kernel / msm-4.19 / 9b0224459fa8ee7c60d16a0b710ebf039da9f365 / . / arch / arm64 / boot / dts / vendor / qcom / camera / khaje-camera.dtsi
blob: fa73692e23df18ca47e523a76b9de6b85a63651e [file] [log] [blame]
Luca Weiss9b022442023-04-14 14:47:36 +0200[diff] [blame^]1#include <dt-bindings/msm/msm-camera.h>
2
3&soc {
4 qcom,cam-req-mgr {
5 compatible = "qcom,cam-req-mgr";
6 status = "ok";
7 };
8
9 cam_csiphy0: qcom,csiphy0 {
10 cell-index = <0>;
11 compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
12 reg = <0x05C52000 0x2000>;
13 reg-names = "csiphy";
14 reg-cam-base = <0x52000>;
15 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
16 interrupt-names = "csiphy";
17 regulator-names = "gdscr", "mipi-csi-vdd1",
18 "mipi-csi-vdd2";
19 gdscr-supply = <&gcc_camss_top_gdsc>;
20 mipi-csi-vdd1-supply = <&L4A>;
21 mipi-csi-vdd2-supply = <&L18A>;
22 rgltr-cntrl-support;
23 rgltr-min-voltage = <0 880000 1200000>;
24 rgltr-max-voltage = <0 1050000 1300000>;
25 rgltr-load-current = <0 0 15900 9000>;
26 clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
27 <&gcc GCC_CAMSS_CPHY_0_CLK>,
28 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>,
29 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>;
30 clock-names = "cphy_rx_clk_src",
31 "csiphy0_clk",
32 "csi0phytimer_clk_src",
33 "csi0phytimer_clk";
34 src-clock-name = "csi0phytimer_clk_src";
35 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
36 clock-rates =
37 <19200000 0 19200000 0>,
38 <256000000 0 300000000 0>,
39 <384000000 0 300000000 0>,
40 <384000000 0 30000000 0>;
41 qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
42 status = "ok";
43 };
44
45 cam_csiphy1: qcom,csiphy1 {
46 cell-index = <1>;
47 compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
48 reg = <0x05C54000 0x2000>;
49 reg-names = "csiphy";
50 reg-cam-base = <0x54000>;
51 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
52 interrupt-names = "csiphy";
53 regulator-names = "gdscr", "mipi-csi-vdd1",
54 "mipi-csi-vdd2";
55 gdscr-supply = <&gcc_camss_top_gdsc>;
56 mipi-csi-vdd1-supply = <&L4A>;
57 mipi-csi-vdd2-supply = <&L18A>;
58 rgltr-cntrl-support;
59 rgltr-min-voltage = <0 880000 1200000>;
60 rgltr-max-voltage = <0 1050000 1300000>;
61 rgltr-load-current = <0 0 15900 9000>;
62 clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
63 <&gcc GCC_CAMSS_CPHY_1_CLK>,
64 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>,
65 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>;
66 clock-names = "cphy_rx_clk_src",
67 "csiphy1_clk",
68 "csi1phytimer_clk_src",
69 "csi1phytimer_clk";
70 src-clock-name = "csi1phytimer_clk_src";
71 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
72 clock-rates =
73 <19200000 0 19200000 0>,
74 <256000000 0 300000000 0>,
75 <384000000 0 300000000 0>,
76 <384000000 0 30000000 0>;
77 qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
78 status = "ok";
79 };
80
81 cam_csiphy2: qcom,csiphy2 {
82 cell-index = <2>;
83 compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
84 reg = <0x05C56000 0x2000>;
85 reg-names = "csiphy";
86 reg-cam-base = <0x56000>;
87 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
88 interrupt-names = "csiphy";
89 regulator-names = "gdscr", "mipi-csi-vdd1",
90 "mipi-csi-vdd2";
91 gdscr-supply = <&gcc_camss_top_gdsc>;
92 mipi-csi-vdd1-supply = <&L4A>;
93 mipi-csi-vdd2-supply = <&L18A>;
94 rgltr-cntrl-support;
95 rgltr-min-voltage = <0 880000 1200000>;
96 rgltr-max-voltage = <0 1050000 1300000>;
97 rgltr-load-current = <0 0 15900 9000>;
98 clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
99 <&gcc GCC_CAMSS_CPHY_2_CLK>,
100 <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK_SRC>,
101 <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK>;
102 clock-names = "cphy_rx_clk_src",
103 "csiphy2_clk",
104 "csi2phytimer_clk_src",
105 "csi2phytimer_clk";
106 src-clock-name = "csi2phytimer_clk_src";
107 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
108 clock-rates =
109 <19200000 0 19200000 0>,
110 <256000000 0 300000000 0>,
111 <384000000 0 300000000 0>,
112 <384000000 0 30000000 0>;
113 qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
114 status = "ok";
115 };
116
117 cam_cci0: qcom,cci0 {
118 cell-index = <0>;
119 compatible = "qcom,cci-v1.2", "qcom,cci";
120 #address-cells = <1>;
121 #size-cells = <0>;
122 reg = <0x05C1B000 0x1000>;
123 reg-names = "cci";
124 reg-cam-base = <0x1B000>;
125 interrupt-names = "cci";
126 interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
127 status = "ok";
128 gdscr-supply = <&gcc_camss_top_gdsc>;
129 regulator-names = "gdscr";
130 clocks = <&gcc GCC_CAMSS_CCI_0_CLK>,
131 <&gcc GCC_CAMSS_CCI_CLK_SRC>;
132 clock-names = "cci_0_clk",
133 "cci_0_clk_src";
134 src-clock-name = "cci_0_clk_src";
135 clock-cntl-level = "svs";
136 clock-rates = <0 37500000>;
137 pinctrl-names = "cam_default", "cam_suspend";
138 pinctrl-0 = <&cci0_active &cci1_active>;
139 pinctrl-1 = <&cci0_suspend &cci1_suspend>;
140 gpios = <&tlmm 22 0>,
141 <&tlmm 23 0>,
142 <&tlmm 29 0>,
143 <&tlmm 30 0>;
144 gpio-req-tbl-num = <0 1 2 3>;
145 gpio-req-tbl-flags = <1 1 1 1>;
146 gpio-req-tbl-label = "CCI_I2C_DATA0",
147 "CCI_I2C_CLK0",
148 "CCI_I2C_DATA1",
149 "CCI_I2C_CLK1";
150
151 i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
152 hw-thigh = <201>;
153 hw-tlow = <174>;
154 hw-tsu-sto = <204>;
155 hw-tsu-sta = <231>;
156 hw-thd-dat = <22>;
157 hw-thd-sta = <162>;
158 hw-tbuf = <227>;
159 hw-scl-stretch-en = <0>;
160 hw-trdhld = <6>;
161 hw-tsp = <3>;
162 cci-clk-src = <37500000>;
163 status = "ok";
164 };
165
166 i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
167 hw-thigh = <38>;
168 hw-tlow = <56>;
169 hw-tsu-sto = <40>;
170 hw-tsu-sta = <40>;
171 hw-thd-dat = <22>;
172 hw-thd-sta = <35>;
173 hw-tbuf = <62>;
174 hw-scl-stretch-en = <0>;
175 hw-trdhld = <6>;
176 hw-tsp = <3>;
177 cci-clk-src = <37500000>;
178 status = "ok";
179 };
180
181 i2c_freq_custom_cci0: qcom,i2c_custom_mode {
182 hw-thigh = <38>;
183 hw-tlow = <56>;
184 hw-tsu-sto = <40>;
185 hw-tsu-sta = <40>;
186 hw-thd-dat = <22>;
187 hw-thd-sta = <35>;
188 hw-tbuf = <62>;
189 hw-scl-stretch-en = <1>;
190 hw-trdhld = <6>;
191 hw-tsp = <3>;
192 cci-clk-src = <37500000>;
193 status = "ok";
194 };
195
196 i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
197 hw-thigh = <16>;
198 hw-tlow = <22>;
199 hw-tsu-sto = <17>;
200 hw-tsu-sta = <18>;
201 hw-thd-dat = <16>;
202 hw-thd-sta = <15>;
203 hw-tbuf = <24>;
204 hw-scl-stretch-en = <0>;
205 hw-trdhld = <3>;
206 hw-tsp = <3>;
207 cci-clk-src = <37500000>;
208 status = "ok";
209 };
210 };
211
212 qcom,cam_smmu {
213 compatible = "qcom,msm-cam-smmu";
214 status = "ok";
215
216 msm_cam_smmu_tfe {
217 compatible = "qcom,msm-cam-smmu-cb";
218 iommus = <&apps_smmu 0x400 0x000>;
219 qcom,iommu-faults = "fatal";
220 qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
221 label = "tfe";
222 tfe_iova_mem_map: iova-mem-map {
223 /* IO region is approximately 3.4 GB */
224 iova-mem-region-io {
225 iova-region-name = "io";
226 iova-region-start = <0x7400000>;
227 iova-region-len = <0xd8c00000>;
228 iova-region-id = <0x3>;
229 status = "ok";
230 };
231 };
232 };
233
234 msm_cam_smmu_ope {
235 compatible = "qcom,msm-cam-smmu-cb";
236 iommus = <&apps_smmu 0x820 0x000>,
237 <&apps_smmu 0x840 0x000>;
238 qcom,iommu-faults = "fatal";
239 multiple-client-devices;
240 qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
241 label = "ope", "ope-cdm0";
242 ope_iova_mem_map: iova-mem-map {
243 /* IO region is approximately 3.4 GB */
244 iova-mem-region-io {
245 iova-region-name = "io";
246 iova-region-start = <0x7400000>;
247 iova-region-len = <0xd8c00000>;
248 iova-region-id = <0x3>;
249 status = "ok";
250 };
251 };
252 };
253
254 msm_cam_smmu_cpas_cdm {
255 compatible = "qcom,msm-cam-smmu-cb";
256 iommus = <&apps_smmu 0x800 0x000>;
257 label = "cpas-cdm0";
258 qcom,iommu-faults = "fatal";
259 qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
260 cpas_cdm_iova_mem_map: iova-mem-map {
261 iova-mem-region-io {
262 /* IO region is approximately 3.4 GB */
263 iova-region-name = "io";
264 iova-region-start = <0x7400000>;
265 iova-region-len = <0xd8c00000>;
266 iova-region-id = <0x3>;
267 status = "ok";
268 };
269 };
270 };
271
272 msm_cam_smmu_secure {
273 compatible = "qcom,msm-cam-smmu-cb";
274 label = "cam-secure";
275 qcom,secure-cb;
276 };
277
278 };
279
280 qcom,cam-cpas@5c11000 {
281 cell-index = <0>;
282 compatible = "qcom,cam-cpas";
283 label = "cpas";
284 arch-compat = "cpas_top";
285 status = "ok";
286 reg-names = "cam_cpas_top", "cam_camnoc";
287 reg = <0x5c11000 0x1000>,
288 <0x5c13000 0x5800>;
289 reg-cam-base = <0x11000 0x13000>;
290 custom-id = <518>;
291 interrupt-names = "cpas_camnoc";
292 interrupts = <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>;
293 camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/
294 regulator-names = "camss-vdd";
295 camss-vdd-supply = <&gcc_camss_top_gdsc>;
296 clock-names =
297 "gcc_camss_ahb_clk",
298 "gcc_camss_top_ahb_clk",
299 "gcc_camss_top_ahb_clk_src",
300 "gcc_camss_axi_clk",
301 "gcc_camss_axi_clk_src",
302 "gcc_camss_nrt_axi_clk",
303 "gcc_camss_rt_axi_clk";
304 clocks =
305 <&gcc GCC_CAMERA_AHB_CLK>,
306 <&gcc GCC_CAMSS_TOP_AHB_CLK>,
307 <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>,
308 <&gcc GCC_CAMSS_AXI_CLK>,
309 <&gcc GCC_CAMSS_AXI_CLK_SRC>,
310 <&gcc GCC_CAMSS_NRT_AXI_CLK>,
311 <&gcc GCC_CAMSS_RT_AXI_CLK>;
312 src-clock-name = "gcc_camss_axi_clk_src";
313 clock-rates =
314 <0 0 0 0 0 0 0>,
315 <0 0 80000000 0 19200000 0 0>,
316 <0 0 80000000 0 150000000 0 0>,
317 <0 0 80000000 0 240000000 0 0>,
318 <0 0 80000000 0 300000000 0 0>,
319 <0 0 80000000 0 300000000 0 0>;
320 clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs",
321 "nominal", "turbo";
322 control-camnoc-axi-clk;
323 camnoc-bus-width = <32>;
324 camnoc-axi-clk-bw-margin-perc = <20>;
325 qcom,msm-bus,name = "cam_ahb";
326 qcom,msm-bus,num-cases = <7>;
327 qcom,msm-bus,num-paths = <1>;
328 qcom,msm-bus,vectors-KBps =
329 <MSM_BUS_MASTER_AMPSS_M0
330 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
331 <MSM_BUS_MASTER_AMPSS_M0
332 MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,
333 <MSM_BUS_MASTER_AMPSS_M0
334 MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,
335 <MSM_BUS_MASTER_AMPSS_M0
336 MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
337 <MSM_BUS_MASTER_AMPSS_M0
338 MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
339 <MSM_BUS_MASTER_AMPSS_M0
340 MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
341 <MSM_BUS_MASTER_AMPSS_M0
342 MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
343 vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
344 RPMH_REGULATOR_LEVEL_MIN_SVS
345 RPMH_REGULATOR_LEVEL_LOW_SVS
346 RPMH_REGULATOR_LEVEL_SVS
347 RPMH_REGULATOR_LEVEL_SVS_L1
348 RPMH_REGULATOR_LEVEL_NOM
349 RPMH_REGULATOR_LEVEL_NOM_L1
350 RPMH_REGULATOR_LEVEL_NOM_L2
351 RPMH_REGULATOR_LEVEL_TURBO
352 RPMH_REGULATOR_LEVEL_TURBO_L1>;
353 vdd-corner-ahb-mapping = "suspend", "minsvs",
354 "lowsvs", "svs", "svs_l1",
355 "nominal", "nominal", "nominal",
356 "turbo", "turbo";
357 client-id-based;
358 client-names =
359 "csiphy0", "csiphy1", "csiphy2", "cci0",
360 "cci1", "csid0", "csid1", "csid2", "tfe0",
361 "tfe1", "tfe2", "ope0", "cam-cdm-intf0",
362 "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1";
363
364 camera-bus-nodes {
365 level2-nodes {
366 level-index = <2>;
367 level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum {
368 cell-index = <0>;
369 node-name = "level2-rt0-rd-wr-sum";
370 traffic-merge-type =
371 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
372 qcom,axi-port-name = "cam_hf_0";
373 ib-bw-voting-needed;
374 qcom,axi-port-mnoc {
375 qcom,msm-bus,name =
376 "cam_hf_0_mnoc";
377 qcom,msm-bus-vector-dyn-vote;
378 qcom,msm-bus,num-cases = <2>;
379 qcom,msm-bus,num-paths = <1>;
380 qcom,msm-bus,vectors-KBps =
381 <MSM_BUS_MASTER_CAMNOC_HF
382 MSM_BUS_SLAVE_EBI_CH0 0 0>,
383 <MSM_BUS_MASTER_CAMNOC_HF
384 MSM_BUS_SLAVE_EBI_CH0 0 0>;
385 };
386 };
387
388 level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum {
389 cell-index = <1>;
390 node-name = "level2-nrt0-rd-wr-sum";
391 traffic-merge-type =
392 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
393 qcom,axi-port-name = "cam_sf_0";
394 qcom,axi-port-mnoc {
395 qcom,msm-bus,name =
396 "cam_sf_0_mnoc";
397 qcom,msm-bus-vector-dyn-vote;
398 qcom,msm-bus,num-cases = <2>;
399 qcom,msm-bus,num-paths = <1>;
400 qcom,msm-bus,vectors-KBps =
401 <MSM_BUS_MASTER_CAMNOC_SF
402 MSM_BUS_SLAVE_EBI_CH0 0 0>,
403 <MSM_BUS_MASTER_CAMNOC_SF
404 MSM_BUS_SLAVE_EBI_CH0 0 0>;
405 };
406 };
407 };
408
409 level1-nodes {
410 level-index = <1>;
411 camnoc-max-needed;
412 level1_rt0_wr: level1-rt0-wr {
413 cell-index = <2>;
414 node-name = "level1-rt0-wr";
415 parent-node = <&level2_rt0_rd_wr_sum>;
416 traffic-merge-type =
417 <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
418 };
419
420 level1_nrt0_rd_wr: level1-nrt0-rd-wr {
421 cell-index = <3>;
422 node-name = "level1-nrt0-rd-wr";
423 parent-node = <&level2_nrt0_rd_wr_sum>;
424 traffic-merge-type =
425 <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
426 };
427 };
428
429 level0-nodes {
430 level-index = <0>;
431 ope0_all_wr: ope0-all-wr {
432 cell-index = <4>;
433 node-name = "ope0-all-wr";
434 client-name = "ope0";
435 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
436 traffic-transaction-type =
437 <CAM_CPAS_TRANSACTION_WRITE>;
438 constituent-paths =
439 <CAM_CPAS_PATH_DATA_OPE_WR_VID
440 CAM_CPAS_PATH_DATA_OPE_WR_DISP
441 CAM_CPAS_PATH_DATA_OPE_WR_REF>;
442 parent-node = <&level1_nrt0_rd_wr>;
443 };
444
445 ope0_all_rd: ope0-all-rd {
446 cell-index = <5>;
447 node-name = "ope0-all-rd";
448 client-name = "ope0";
449 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
450 traffic-transaction-type =
451 <CAM_CPAS_TRANSACTION_READ>;
452 constituent-paths =
453 <CAM_CPAS_PATH_DATA_OPE_RD_IN
454 CAM_CPAS_PATH_DATA_OPE_RD_REF>;
455 parent-node = <&level1_nrt0_rd_wr>;
456 };
457
458 tfe0_all_wr: tfe0-all-wr {
459 cell-index = <6>;
460 node-name = "tfe0-all-wr";
461 client-name = "tfe0";
462 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
463 traffic-transaction-type =
464 <CAM_CPAS_TRANSACTION_WRITE>;
465 constituent-paths =
466 <CAM_CPAS_PATH_DATA_IFE_RDI0
467 CAM_CPAS_PATH_DATA_IFE_RDI1
468 CAM_CPAS_PATH_DATA_IFE_RDI2
469 CAM_CPAS_PATH_DATA_IFE_RDI3
470 CAM_CPAS_PATH_DATA_IFE_VID
471 CAM_CPAS_PATH_DATA_IFE_DISP
472 CAM_CPAS_PATH_DATA_IFE_STATS>;
473 parent-node = <&level1_rt0_wr>;
474 };
475
476 tfe1_all_wr: tfe1-all-wr {
477 cell-index = <7>;
478 node-name = "tfe1-all-wr";
479 client-name = "tfe1";
480 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
481 traffic-transaction-type =
482 <CAM_CPAS_TRANSACTION_WRITE>;
483 constituent-paths =
484 <CAM_CPAS_PATH_DATA_IFE_RDI0
485 CAM_CPAS_PATH_DATA_IFE_RDI1
486 CAM_CPAS_PATH_DATA_IFE_RDI2
487 CAM_CPAS_PATH_DATA_IFE_RDI3
488 CAM_CPAS_PATH_DATA_IFE_VID
489 CAM_CPAS_PATH_DATA_IFE_DISP
490 CAM_CPAS_PATH_DATA_IFE_STATS>;
491 parent-node = <&level1_rt0_wr>;
492 };
493
494 tfe2_all_wr: tfe2-all-wr {
495 cell-index = <8>;
496 node-name = "tfe2-all-wr";
497 client-name = "tfe2";
498 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
499 traffic-transaction-type =
500 <CAM_CPAS_TRANSACTION_WRITE>;
501 constituent-paths =
502 <CAM_CPAS_PATH_DATA_IFE_RDI0
503 CAM_CPAS_PATH_DATA_IFE_RDI1
504 CAM_CPAS_PATH_DATA_IFE_RDI2
505 CAM_CPAS_PATH_DATA_IFE_RDI3
506 CAM_CPAS_PATH_DATA_IFE_VID
507 CAM_CPAS_PATH_DATA_IFE_DISP
508 CAM_CPAS_PATH_DATA_IFE_STATS>;
509 parent-node = <&level1_rt0_wr>;
510 };
511
512 cpas_cdm0_all_rd: cpas-cdm0-all-rd {
513 cell-index = <9>;
514 node-name = "cpas-cdm0-all-rd";
515 client-name = "cpas-cdm0";
516 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
517 traffic-transaction-type =
518 <CAM_CPAS_TRANSACTION_READ>;
519 parent-node = <&level1_nrt0_rd_wr>;
520 };
521
522 ope_cdm0_all_rd: ope-cdm0-all-rd {
523 cell-index = <10>;
524 node-name = "ope-cdm0-all-rd";
525 client-name = "ope-cdm0";
526 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
527 traffic-transaction-type =
528 <CAM_CPAS_TRANSACTION_READ>;
529 parent-node = <&level1_nrt0_rd_wr>;
530 };
531 };
532 };
533 };
534
535 qcom,cam-cdm-intf {
536 compatible = "qcom,cam-cdm-intf";
537 cell-index = <0>;
538 label = "cam-cdm-intf";
539 num-hw-cdm = <2>;
540 cdm-client-names = "vfe";
541 status = "ok";
542 };
543
544 cam_cpas_cdm: qcom,cpas-cdm0@5c23000 {
545 cell-index = <0>;
546 compatible = "qcom,cam-cpas-cdm2_1";
547 label = "cpas-cdm";
548 reg = <0x5c23000 0x400>;
549 reg-names = "cpas-cdm0";
550 reg-cam-base = <0x23000>;
551 interrupts = <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>;
552 interrupt-names = "cpas-cdm0";
553 regulator-names = "camss";
554 camss-supply = <&gcc_camss_top_gdsc>;
555 clock-names = "cam_cc_cpas_top_ahb_clk";
556 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>;
557 clock-rates = <0>;
558 clock-cntl-level = "svs";
559 cdm-client-names = "tfe0", "tfe1", "tfe2";
560 config-fifo;
561 fifo-depths = <64 64 64 64>;
562 status = "ok";
563 };
564
565 cam_ope_cdm: qcom,ope-cdm0@5c42000 {
566 cell-index = <0>;
567 compatible = "qcom,cam-ope-cdm2_1";
568 label = "ope-cdm";
569 reg = <0x5c42000 0x400>;
570 reg-names = "ope-cdm0";
571 reg-cam-base = <0x42000>;
572 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>;
573 interrupt-names = "ope-cdm0";
574 regulator-names = "camss";
575 camss-supply = <&gcc_camss_top_gdsc>;
576 clock-names =
577 "ope_ahb_clk",
578 "ope_clk_src",
579 "ope_clk";
580 clocks =
581 <&gcc GCC_CAMSS_OPE_AHB_CLK>,
582 <&gcc GCC_CAMSS_OPE_CLK_SRC>,
583 <&gcc GCC_CAMSS_OPE_CLK>;
584 clock-rates = <0 0 0>,
585 <0 0 0>,
586 <0 0 0>,
587 <0 0 0>;
588 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
589 cdm-client-names = "ope";
590 config-fifo;
591 fifo-depths = <64 64 64 64>;
592 status = "ok";
593 };
594
595 qcom,cam-isp {
596 compatible = "qcom,cam-isp";
597 arch-compat = "tfe";
598 status = "ok";
599 };
600
601 cam_tfe_csid0: qcom,tfe_csid0@5c6e000 {
602 cell-index = <0>;
603 compatible = "qcom,csid530";
604 reg-names = "csid", "top", "camnoc";
605 reg = <0x5c6e000 0x5000>,
606 <0x5c11000 0x1000>,
607 <0x5c13000 0x4000>;
608 reg-cam-base = <0x6e000 0x11000 0x13000>;
609 interrupt-names = "csid0";
610 interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
611 regulator-names = "camss";
612 camss-supply = <&gcc_camss_top_gdsc>;
613 clock-names =
614 "tfe_csid_clk_src",
615 "tfe_csid_clk",
616 "cphy_rx_clk_src",
617 "tfe_cphy_rx_clk",
618 "tfe_clk_src",
619 "tfe_clk";
620 clocks =
621 <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>,
622 <&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
623 <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
624 <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
625 <&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
626 <&gcc GCC_CAMSS_TFE_0_CLK>;
627 clock-rates =
628 <266571429 0 0 0 300000000 0>,
629 <426400000 0 0 0 460800000 0>,
630 <466500000 0 0 0 576000000 0>;
631 clock-cntl-level = "svs", "svs_l1", "turbo";
632 src-clock-name = "tfe_csid_clk_src";
633 clock-control-debugfs = "true";
634 ppi-enable;
635 status = "ok";
636 };
637
638 cam_tfe0: qcom,tfe0@5c6e000 {
639 cell-index = <0>;
640 compatible = "qcom,tfe530";
641 reg-names = "tfe0";
642 reg = <0x5c6e000 0x5000>;
643 reg-cam-base = <0x6e000>;
644 interrupt-names = "tfe0";
645 interrupts = <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>;
646 regulator-names = "camss";
647 camss-supply = <&gcc_camss_top_gdsc>;
648 clock-names =
649 "tfe_clk_src",
650 "tfe_clk";
651 clocks =
652 <&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
653 <&gcc GCC_CAMSS_TFE_0_CLK>;
654 clock-rates =
655 <300000000 0>,
656 <460800000 0>,
657 <576000000 0>;
658 clock-cntl-level = "svs", "svs_l1", "turbo";
659 src-clock-name = "tfe_clk_src";
660 clock-control-debugfs = "true";
661 status = "ok";
662 };
663
664 cam_tfe_csid1: qcom,tfe_csid1@5c75000 {
665 cell-index = <1>;
666 compatible = "qcom,csid530";
667 reg-names = "csid", "top", "camnoc";
668 reg = <0x5c75000 0x5000>,
669 <0x5c11000 0x1000>,
670 <0x5c13000 0x4000>;
671 reg-cam-base = <0x75000 0x11000 0x13000>;
672 interrupt-names = "csid1";
673 interrupts = <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
674 regulator-names = "camss";
675 camss-supply = <&gcc_camss_top_gdsc>;
676 clock-names =
677 "tfe_csid_clk_src",
678 "tfe_csid_clk",
679 "cphy_rx_clk_src",
680 "tfe_cphy_rx_clk",
681 "tfe_clk_src",
682 "tfe_clk";
683 clocks =
684 <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>,
685 <&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
686 <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
687 <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
688 <&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
689 <&gcc GCC_CAMSS_TFE_1_CLK>;
690 clock-rates =
691 <266571429 0 0 0 300000000 0>,
692 <426400000 0 0 0 460800000 0>,
693 <466500000 0 0 0 576000000 0>;
694 clock-cntl-level = "svs", "svs_l1", "turbo";
695 src-clock-name = "tfe_csid_clk_src";
696 clock-control-debugfs = "true";
697 ppi-enable;
698 status = "ok";
699 };
700
701 cam_tfe1: qcom,tfe1@5c75000 {
702 cell-index = <1>;
703 compatible = "qcom,tfe530";
704 reg-names = "tfe1";
705 reg = <0x5c75000 0x5000>;
706 reg-cam-base = <0x75000>;
707 interrupt-names = "tfe1";
708 interrupts = <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
709 regulator-names = "camss";
710 camss-supply = <&gcc_camss_top_gdsc>;
711 clock-names =
712 "tfe_clk_src",
713 "tfe_clk";
714 clocks =
715 <&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
716 <&gcc GCC_CAMSS_TFE_1_CLK>;
717 clock-rates =
718 <300000000 0>,
719 <460800000 0>,
720 <576000000 0>;
721 clock-cntl-level = "svs", "svs_l1", "turbo";
722 src-clock-name = "tfe_clk_src";
723 clock-control-debugfs = "true";
724 status = "ok";
725 };
726
727 cam_tfe_csid2: qcom,tfe_csid2@5c7c000 {
728 cell-index = <2>;
729 compatible = "qcom,csid530";
730 reg-names = "csid", "top", "camnoc";
731 reg = <0x5c7c000 0x5000>,
732 <0x5c11000 0x1000>,
733 <0x5c13000 0x4000>;
734 reg-cam-base = <0x7c000 0x11000 0x13000>;
735 interrupt-names = "csid2";
736 interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
737 regulator-names = "camss";
738 camss-supply = <&gcc_camss_top_gdsc>;
739 clock-names =
740 "tfe_csid_clk_src",
741 "tfe_csid_clk",
742 "cphy_rx_clk_src",
743 "tfe_cphy_rx_clk",
744 "tfe_clk_src",
745 "tfe_clk";
746 clocks =
747 <&gcc GCC_CAMSS_TFE_2_CSID_CLK_SRC>,
748 <&gcc GCC_CAMSS_TFE_2_CSID_CLK>,
749 <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
750 <&gcc GCC_CAMSS_TFE_2_CPHY_RX_CLK>,
751 <&gcc GCC_CAMSS_TFE_2_CLK_SRC>,
752 <&gcc GCC_CAMSS_TFE_2_CLK>;
753 clock-rates =
754 <266571429 0 0 0 300000000 0>,
755 <426400000 0 0 0 460800000 0>,
756 <466500000 0 0 0 576000000 0>;
757 clock-cntl-level = "svs", "svs_l1", "turbo";
758 src-clock-name = "tfe_csid_clk_src";
759 clock-control-debugfs = "true";
760 ppi-enable;
761 status = "ok";
762 };
763
764 cam_tfe2: qcom,tfe2@5c7c000 {
765 cell-index = <2>;
766 compatible = "qcom,tfe530";
767 reg-names = "tfe2";
768 reg = <0x5c7c000 0x5000>;
769 reg-cam-base = <0x7c000>;
770 interrupt-names = "tfe2";
771 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
772 regulator-names = "camss";
773 camss-supply = <&gcc_camss_top_gdsc>;
774 clock-names =
775 "tfe_clk_src",
776 "tfe_clk";
777 clocks =
778 <&gcc GCC_CAMSS_TFE_2_CLK_SRC>,
779 <&gcc GCC_CAMSS_TFE_2_CLK>;
780 clock-rates =
781 <300000000 0>,
782 <460800000 0>,
783 <576000000 0>;
784 clock-cntl-level = "svs", "svs_l1", "turbo";
785 src-clock-name = "tfe_clk_src";
786 clock-control-debugfs = "true";
787 status = "ok";
788 };
789
790 cam_ppi0: qcom,ppi0@5cb3000 {
791 cell-index = <0>;
792 compatible = "qcom,ppi100";
793 reg-names = "ppi0";
794 reg = <0x5cb3000 0x200>;
795 reg-cam-base = <0xb3000>;
796 interrupt-names = "ppi0";
797 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
798 clocks = <&gcc GCC_CAMSS_CPHY_0_CLK>;
799 clock-names = "gcc_camss_cphy_0_clk";
800 clock-cntl-level = "svs";
801 clock-rates = <0>;
802 status = "ok";
803 };
804
805 cam_ppi1: qcom,ppi1@5cb3200 {
806 cell-index = <1>;
807 compatible = "qcom,ppi100";
808 reg-names = "ppi1";
809 reg = <0x5cb3200 0x200>;
810 reg-cam-base = <0xb3200>;
811 interrupt-names = "ppi1";
812 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
813 clocks = <&gcc GCC_CAMSS_CPHY_1_CLK>;
814 clock-names = "gcc_camss_cphy_1_clk";
815 clock-cntl-level = "svs";
816 clock-rates = <0>;
817 status = "ok";
818 };
819
820 cam_ppi2: qcom,ppi2@5cb3400 {
821 cell-index = <2>;
822 compatible = "qcom,ppi100";
823 reg-names = "ppi2";
824 reg = <0x5cb3400 0x200>;
825 reg-cam-base = <0xb3400>;
826 interrupt-names = "ppi2";
827 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
828 clocks = <&gcc GCC_CAMSS_CPHY_2_CLK>;
829 clock-names = "gcc_camss_cphy_2_clk";
830 clock-cntl-level = "svs";
831 clock-rates = <0>;
832 status = "ok";
833 };
834
835 cam_tfe_tpg0: qcom,tpg0@5c66000 {
836 cell-index = <0>;
837 compatible = "qcom,tpgv1";
838 reg-names = "tpg0", "top";
839 reg = <0x5c66000 0x400>,
840 <0x5c11000 0x1000>;
841 reg-cam-base = <0x66000 0x11000>;
842 regulator-names = "camss";
843 camss-supply = <&gcc_camss_top_gdsc>;
844 clock-names =
845 "cphy_rx_clk_src",
846 "tfe_0_cphy_rx_clk",
847 "gcc_camss_cphy_0_clk";
848 clocks =
849 <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
850 <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
851 <&gcc GCC_CAMSS_CPHY_0_CLK>;
852 clock-rates =
853 <256000000 0 0>,
854 <384000000 0 0>,
855 <384000000 0 0>;
856 clock-cntl-level = "svs", "svs_l1", "turbo";
857 src-clock-name = "cphy_rx_clk_src";
858 clock-control-debugfs = "false";
859 status = "ok";
860 };
861
862 cam_tfe_tpg1: qcom,tpg0@5c68000 {
863 cell-index = <1>;
864 compatible = "qcom,tpgv1";
865 reg-names = "tpg1", "top";
866 reg = <0x5c68000 0x400>,
867 <0x5c11000 0x1000>;
868 reg-cam-base = <0x68000 0x11000>;
869 regulator-names = "camss";
870 camss-supply = <&gcc_camss_top_gdsc>;
871 clock-names =
872 "cphy_rx_clk_src",
873 "tfe_1_cphy_rx_clk",
874 "gcc_camss_cphy_1_clk";
875 clocks =
876 <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
877 <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
878 <&gcc GCC_CAMSS_CPHY_1_CLK>;
879 clock-rates =
880 <256000000 0 0>,
881 <384000000 0 0>,
882 <384000000 0 0>;
883 clock-cntl-level = "svs", "svs_l1", "turbo";
884 src-clock-name = "cphy_rx_clk_src";
885 clock-control-debugfs = "false";
886 status = "ok";
887 };
888
889 qcom,cam-ope {
890 compatible = "qcom,cam-ope";
891 compat-hw-name = "qcom,ope";
892 num-ope = <1>;
893 status = "ok";
894 };
895
896 ope: qcom,ope@0x5c42000 {
897 cell-index = <0>;
898 compatible = "qcom,ope";
899 reg =
900 <0x5c42000 0x400>,
901 <0x5c42400 0x200>,
902 <0x5c42600 0x200>,
903 <0x5c42800 0x4400>,
904 <0x5c46c00 0x190>,
905 <0x5c46d90 0xA00>;
906 reg-names =
907 "ope_cdm",
908 "ope_top",
909 "ope_qos",
910 "ope_pp",
911 "ope_bus_rd",
912 "ope_bus_wr";
913 reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>;
914 interrupts = <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>;
915 interrupt-names = "ope";
916 regulator-names = "camss";
917 camss-supply = <&gcc_camss_top_gdsc>;
918 clock-names =
919 "ope_ahb_clk",
920 "ope_clk_src",
921 "ope_clk";
922 clocks =
923 <&gcc GCC_CAMSS_OPE_AHB_CLK>,
924 <&gcc GCC_CAMSS_OPE_CLK_SRC>,
925 <&gcc GCC_CAMSS_OPE_CLK>;
926 clock-rates =
927 <171428571 200000000 0>,
928 <171428571 266600000 0>,
929 <240000000 480000000 0>,
930 <240000000 580000000 0>;
931 clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";
932 src-clock-name = "ope_clk_src";
933 status = "ok";
934 };
935};