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gerrit-public.fairphone.software / kernel / msm-4.19 / 9b0224459fa8ee7c60d16a0b710ebf039da9f365 / . / arch / arm64 / boot / dts / vendor / qcom / camera / kona-camera.dtsi
blob: eb9b28860635b6e4ee62eb6c757be50e282f3a2a [file] [log] [blame]
Luca Weiss9b022442023-04-14 14:47:36 +0200[diff] [blame^]1#include <dt-bindings/msm/msm-camera.h>
2
3&soc {
4 qcom,cam-req-mgr {
5 compatible = "qcom,cam-req-mgr";
6 status = "ok";
7 };
8
9 cam_csiphy0: qcom,csiphy@ac6a000 {
10 cell-index = <0>;
11 compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
12 reg = <0x0ac6a000 0x2000>;
13 reg-names = "csiphy";
14 reg-cam-base = <0x6a000>;
15 interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
16 interrupt-names = "csiphy";
17 gdscr-supply = <&titan_top_gdsc>;
18 refgen-supply = <&refgen>;
19 regulator-names = "gdscr", "refgen";
20 csi-vdd-voltage = <1200000>;
21 mipi-csi-vdd-supply = <&pm8150_l9>;
22 clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
23 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
24 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
25 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;
26 clock-names = "cphy_rx_clk_src",
27 "csiphy0_clk",
28 "csi0phytimer_clk_src",
29 "csi0phytimer_clk";
30 src-clock-name = "csi0phytimer_clk_src";
31 clock-cntl-level = "turbo";
32 clock-rates =
33 <400000000 0 300000000 0>;
34 status = "ok";
35 };
36
37 cam_csiphy1: qcom,csiphy@ac6c000 {
38 cell-index = <1>;
39 compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
40 reg = <0xac6c000 0x2000>;
41 reg-names = "csiphy";
42 reg-cam-base = <0x6c000>;
43 interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
44 interrupt-names = "csiphy";
45 gdscr-supply = <&titan_top_gdsc>;
46 refgen-supply = <&refgen>;
47 regulator-names = "gdscr", "refgen";
48 csi-vdd-voltage = <1200000>;
49 mipi-csi-vdd-supply = <&pm8150_l9>;
50 clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
51 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
52 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
53 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>;
54 clock-names = "cphy_rx_clk_src",
55 "csiphy1_clk",
56 "csi1phytimer_clk_src",
57 "csi1phytimer_clk";
58 src-clock-name = "csi1phytimer_clk_src";
59 clock-cntl-level = "turbo";
60 clock-rates =
61 <400000000 0 300000000 0>;
62
63 status = "ok";
64 };
65
66 cam_csiphy2: qcom,csiphy@ac6e000 {
67 cell-index = <2>;
68 compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
69 reg = <0xac6e000 0x2000>;
70 reg-names = "csiphy";
71 reg-cam-base = <0x6e000>;
72 interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
73 interrupt-names = "csiphy";
74 gdscr-supply = <&titan_top_gdsc>;
75 refgen-supply = <&refgen>;
76 regulator-names = "gdscr", "refgen";
77 csi-vdd-voltage = <1200000>;
78 mipi-csi-vdd-supply = <&pm8150_l9>;
79 clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
80 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
81 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
82 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;
83 clock-names = "cphy_rx_clk_src",
84 "csiphy2_clk",
85 "csi2phytimer_clk_src",
86 "csi2phytimer_clk";
87 src-clock-name = "csi2phytimer_clk_src";
88 clock-cntl-level = "turbo";
89 clock-rates =
90 <400000000 0 300000000 0>;
91 status = "ok";
92 };
93
94 cam_csiphy3: qcom,csiphy@ac70000 {
95 cell-index = <3>;
96 compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
97 reg = <0xac70000 0x2000>;
98 reg-names = "csiphy";
99 reg-cam-base = <0x70000>;
100 interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
101 interrupt-names = "csiphy";
102 gdscr-supply = <&titan_top_gdsc>;
103 refgen-supply = <&refgen>;
104 regulator-names = "gdscr", "refgen";
105 csi-vdd-voltage = <1200000>;
106 mipi-csi-vdd-supply = <&pm8150_l9>;
107 clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
108 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
109 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
110 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>;
111 clock-names = "cphy_rx_clk_src",
112 "csiphy3_clk",
113 "csi3phytimer_clk_src",
114 "csi3phytimer_clk";
115 src-clock-name = "csi3phytimer_clk_src";
116 clock-cntl-level = "turbo";
117 clock-rates =
118 <400000000 0 300000000 0>;
119 status = "ok";
120 };
121
122 cam_csiphy4: qcom,csiphy@ac72000 {
123 cell-index = <4>;
124 compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
125 reg = <0xac72000 0x2000>;
126 reg-names = "csiphy";
127 reg-cam-base = <0x72000>;
128 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
129 interrupt-names = "csiphy";
130 gdscr-supply = <&titan_top_gdsc>;
131 refgen-supply = <&refgen>;
132 regulator-names = "gdscr", "refgen";
133 csi-vdd-voltage = <1200000>;
134 mipi-csi-vdd-supply = <&pm8150_l9>;
135 clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
136 <&clock_camcc CAM_CC_CSIPHY4_CLK>,
137 <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
138 <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>;
139 clock-names = "cphy_rx_clk_src",
140 "csiphy4_clk",
141 "csi4phytimer_clk_src",
142 "csi4phytimer_clk";
143 src-clock-name = "csi4phytimer_clk_src";
144 clock-cntl-level = "turbo";
145 clock-rates =
146 <400000000 0 300000000 0>;
147 status = "ok";
148 };
149
150 cam_csiphy5: qcom,csiphy@ac74000 {
151 cell-index = <5>;
152 compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
153 reg = <0xac74000 0x2000>;
154 reg-names = "csiphy";
155 reg-cam-base = <0x74000>;
156 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
157 interrupt-names = "csiphy";
158 gdscr-supply = <&titan_top_gdsc>;
159 refgen-supply = <&refgen>;
160 regulator-names = "gdscr", "refgen";
161 csi-vdd-voltage = <1200000>;
162 mipi-csi-vdd-supply = <&pm8150_l9>;
163 clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
164 <&clock_camcc CAM_CC_CSIPHY5_CLK>,
165 <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
166 <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK>;
167 clock-names = "cphy_rx_clk_src",
168 "csiphy5_clk",
169 "csi5phytimer_clk_src",
170 "csi5phytimer_clk";
171 src-clock-name = "csi5phytimer_clk_src";
172 clock-cntl-level = "turbo";
173 clock-rates =
174 <400000000 0 300000000 0>;
175 status = "ok";
176 };
177
178 cam_cci0: qcom,cci@ac4f000 {
179 cell-index = <0>;
180 compatible = "qcom,cci";
181 reg = <0xac4f000 0x1000>;
182 reg-names = "cci";
183 reg-cam-base = <0x4f000>;
184 interrupt-names = "cci";
185 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
186 status = "ok";
187 gdscr-supply = <&titan_top_gdsc>;
188 regulator-names = "gdscr";
189 clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>,
190 <&clock_camcc CAM_CC_CCI_0_CLK>;
191 clock-names = "cci_0_clk_src",
192 "cci_0_clk";
193 src-clock-name = "cci_0_clk_src";
194 clock-cntl-level = "lowsvs";
195 clock-rates = <37500000 0>;
196 pinctrl-names = "cam_default", "cam_suspend";
197 pinctrl-0 = <&cci0_active &cci1_active>;
198 pinctrl-1 = <&cci0_suspend &cci1_suspend>;
199 gpios = <&tlmm 101 0>,
200 <&tlmm 102 0>,
201 <&tlmm 103 0>,
202 <&tlmm 104 0>;
203 gpio-req-tbl-num = <0 1 2 3>;
204 gpio-req-tbl-flags = <1 1 1 1>;
205 gpio-req-tbl-label = "CCI_I2C_DATA0",
206 "CCI_I2C_CLK0",
207 "CCI_I2C_DATA1",
208 "CCI_I2C_CLK1";
209
210 i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
211 hw-thigh = <201>;
212 hw-tlow = <174>;
213 hw-tsu-sto = <204>;
214 hw-tsu-sta = <231>;
215 hw-thd-dat = <22>;
216 hw-thd-sta = <162>;
217 hw-tbuf = <227>;
218 hw-scl-stretch-en = <0>;
219 hw-trdhld = <6>;
220 hw-tsp = <3>;
221 cci-clk-src = <37500000>;
222 status = "ok";
223 };
224
225 i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
226 hw-thigh = <38>;
227 hw-tlow = <56>;
228 hw-tsu-sto = <40>;
229 hw-tsu-sta = <40>;
230 hw-thd-dat = <22>;
231 hw-thd-sta = <35>;
232 hw-tbuf = <62>;
233 hw-scl-stretch-en = <0>;
234 hw-trdhld = <6>;
235 hw-tsp = <3>;
236 cci-clk-src = <37500000>;
237 status = "ok";
238 };
239
240 i2c_freq_custom_cci0: qcom,i2c_custom_mode {
241 hw-thigh = <38>;
242 hw-tlow = <56>;
243 hw-tsu-sto = <40>;
244 hw-tsu-sta = <40>;
245 hw-thd-dat = <22>;
246 hw-thd-sta = <35>;
247 hw-tbuf = <62>;
248 hw-scl-stretch-en = <1>;
249 hw-trdhld = <6>;
250 hw-tsp = <3>;
251 cci-clk-src = <37500000>;
252 status = "ok";
253 };
254
255 i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
256 hw-thigh = <16>;
257 hw-tlow = <22>;
258 hw-tsu-sto = <17>;
259 hw-tsu-sta = <18>;
260 hw-thd-dat = <16>;
261 hw-thd-sta = <15>;
262 hw-tbuf = <24>;
263 hw-scl-stretch-en = <0>;
264 hw-trdhld = <3>;
265 hw-tsp = <3>;
266 cci-clk-src = <37500000>;
267 status = "ok";
268 };
269 };
270
271 cam_cci1: qcom,cci@ac50000 {
272 cell-index = <1>;
273 compatible = "qcom,cci";
274 reg = <0xac50000 0x1000>;
275 reg-names = "cci";
276 reg-cam-base = <0x50000>;
277 interrupt-names = "cci";
278 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
279 status = "ok";
280 gdscr-supply = <&titan_top_gdsc>;
281 regulator-names = "gdscr";
282 clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>,
283 <&clock_camcc CAM_CC_CCI_1_CLK>;
284 clock-names = "cci_1_clk_src",
285 "cci_1_clk";
286 src-clock-name = "cci_1_clk_src";
287 clock-cntl-level = "lowsvs";
288 clock-rates = <37500000 0>;
289 pinctrl-names = "cam_default", "cam_suspend";
290 pinctrl-0 = <&cci2_active &cci3_active>;
291 pinctrl-1 = <&cci2_suspend &cci3_suspend>;
292 gpios = <&tlmm 105 0>,
293 <&tlmm 106 0>,
294 <&tlmm 107 0>,
295 <&tlmm 108 0>;
296 gpio-req-tbl-num = <0 1 2 3>;
297 gpio-req-tbl-flags = <1 1 1 1>;
298 gpio-req-tbl-label = "CCI_I2C_DATA2",
299 "CCI_I2C_CLK2",
300 "CCI_I2C_DATA3",
301 "CCI_I2C_CLK3";
302
303 i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
304 hw-thigh = <201>;
305 hw-tlow = <174>;
306 hw-tsu-sto = <204>;
307 hw-tsu-sta = <231>;
308 hw-thd-dat = <22>;
309 hw-thd-sta = <162>;
310 hw-tbuf = <227>;
311 hw-scl-stretch-en = <0>;
312 hw-trdhld = <6>;
313 hw-tsp = <3>;
314 cci-clk-src = <37500000>;
315 status = "ok";
316 };
317
318 i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
319 hw-thigh = <38>;
320 hw-tlow = <56>;
321 hw-tsu-sto = <40>;
322 hw-tsu-sta = <40>;
323 hw-thd-dat = <22>;
324 hw-thd-sta = <35>;
325 hw-tbuf = <62>;
326 hw-scl-stretch-en = <0>;
327 hw-trdhld = <6>;
328 hw-tsp = <3>;
329 cci-clk-src = <37500000>;
330 status = "ok";
331 };
332
333 i2c_freq_custom_cci1: qcom,i2c_custom_mode {
334 hw-thigh = <38>;
335 hw-tlow = <56>;
336 hw-tsu-sto = <40>;
337 hw-tsu-sta = <40>;
338 hw-thd-dat = <22>;
339 hw-thd-sta = <35>;
340 hw-tbuf = <62>;
341 hw-scl-stretch-en = <1>;
342 hw-trdhld = <6>;
343 hw-tsp = <3>;
344 cci-clk-src = <37500000>;
345 status = "ok";
346 };
347
348 i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
349 hw-thigh = <16>;
350 hw-tlow = <22>;
351 hw-tsu-sto = <17>;
352 hw-tsu-sta = <18>;
353 hw-thd-dat = <16>;
354 hw-thd-sta = <15>;
355 hw-tbuf = <24>;
356 hw-scl-stretch-en = <0>;
357 hw-trdhld = <3>;
358 hw-tsp = <3>;
359 cci-clk-src = <37500000>;
360 status = "ok";
361 };
362 };
363
364 qcom,cam_smmu {
365 compatible = "qcom,msm-cam-smmu";
366 status = "ok";
367
368 msm_cam_smmu_ife {
369 compatible = "qcom,msm-cam-smmu-cb";
370 iommus = <&apps_smmu 0x800 0x400>,
371 <&apps_smmu 0x801 0x400>,
372 <&apps_smmu 0x840 0x400>,
373 <&apps_smmu 0x841 0x400>,
374 <&apps_smmu 0xC00 0x400>,
375 <&apps_smmu 0xC01 0x400>,
376 <&apps_smmu 0xC40 0x400>,
377 <&apps_smmu 0xC41 0x400>;
378 qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
379 label = "ife";
380 ife_iova_mem_map: iova-mem-map {
381 /* IO region is approximately 3.4 GB */
382 iova-mem-region-io {
383 iova-region-name = "io";
384 iova-region-start = <0x7400000>;
385 iova-region-len = <0xd8c00000>;
386 iova-region-id = <0x3>;
387 status = "ok";
388 };
389 };
390 };
391
392 msm_cam_smmu_jpeg {
393 compatible = "qcom,msm-cam-smmu-cb";
394 iommus = <&apps_smmu 0x2040 0x400>,
395 <&apps_smmu 0x2440 0x400>;
396 label = "jpeg";
397 qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
398 jpeg_iova_mem_map: iova-mem-map {
399 /* IO region is approximately 3.4 GB */
400 iova-mem-region-io {
401 iova-region-name = "io";
402 iova-region-start = <0x7400000>;
403 iova-region-len = <0xd8c00000>;
404 iova-region-id = <0x3>;
405 status = "ok";
406 };
407 };
408 };
409
410 msm_cam_icp_fw {
411 compatible = "qcom,msm-cam-smmu-fw-dev";
412 label="icp";
413 memory-region = <&pil_camera_mem>;
414 };
415
416 msm_cam_smmu_icp {
417 compatible = "qcom,msm-cam-smmu-cb";
418 iommus = <&apps_smmu 0x20E2 0x400>,
419 <&apps_smmu 0x24E2 0x400>,
420 <&apps_smmu 0x2000 0x400>,
421 <&apps_smmu 0x2001 0x400>,
422 <&apps_smmu 0x2400 0x400>,
423 <&apps_smmu 0x2401 0x400>,
424 <&apps_smmu 0x2060 0x400>,
425 <&apps_smmu 0x2061 0x400>,
426 <&apps_smmu 0x2460 0x400>,
427 <&apps_smmu 0x2461 0x400>,
428 <&apps_smmu 0x2020 0x400>,
429 <&apps_smmu 0x2021 0x400>,
430 <&apps_smmu 0x2420 0x400>,
431 <&apps_smmu 0x2421 0x400>;
432 label = "icp";
433 qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>;
434 iova-region-discard = <0xdff00000 0x300000>;
435 icp_iova_mem_map: iova-mem-map {
436 iova-mem-region-firmware {
437 /* Firmware region is 5MB */
438 iova-region-name = "firmware";
439 iova-region-start = <0x0>;
440 iova-region-len = <0x500000>;
441 iova-region-id = <0x0>;
442 status = "ok";
443 };
444
445 iova-mem-region-shared {
446 /* Shared region is 150MB long */
447 iova-region-name = "shared";
448 iova-region-start = <0x7400000>;
449 iova-region-len = <0x9600000>;
450 iova-region-id = <0x1>;
451 status = "ok";
452 };
453
454 iova-mem-region-secondary-heap {
455 /* Secondary heap region is 1MB long */
456 iova-region-name = "secheap";
457 iova-region-start = <0x10a00000>;
458 iova-region-len = <0x100000>;
459 iova-region-id = <0x4>;
460 status = "ok";
461 };
462
463 iova-mem-region-io {
464 /* IO region is approximately 3.7 GB */
465 iova-region-name = "io";
466 iova-region-start = <0x10c00000>;
467 iova-region-len = <0xee300000>;
468 iova-region-id = <0x3>;
469 iova-region-discard = <0xdff00000 0x300000>;
470 status = "ok";
471 };
472
473 iova-mem-qdss-region {
474 /* QDSS region is appropriate 1MB */
475 iova-region-name = "qdss";
476 iova-region-start = <0x10b00000>;
477 iova-region-len = <0x100000>;
478 iova-region-id = <0x5>;
479 qdss-phy-addr = <0x16790000>;
480 status = "ok";
481 };
482 };
483 };
484
485 msm_cam_smmu_cpas_cdm {
486 compatible = "qcom,msm-cam-smmu-cb";
487 iommus = <&apps_smmu 0x20C0 0x400>,
488 <&apps_smmu 0x24C0 0x400>;
489 label = "cpas-cdm0";
490 qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
491 cpas_cdm_iova_mem_map: iova-mem-map {
492 iova-mem-region-io {
493 /* IO region is approximately 3.4 GB */
494 iova-region-name = "io";
495 iova-region-start = <0x7400000>;
496 iova-region-len = <0xd8c00000>;
497 iova-region-id = <0x3>;
498 status = "ok";
499 };
500 };
501 };
502
503 msm_cam_smmu_secure {
504 compatible = "qcom,msm-cam-smmu-cb";
505 label = "cam-secure";
506 qcom,secure-cb;
507 };
508
509 msm_cam_smmu_fd {
510 compatible = "qcom,msm-cam-smmu-cb";
511 iommus = <&apps_smmu 0x2080 0x400>,
512 <&apps_smmu 0x2480 0x400>;
513 qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
514 label = "fd";
515 fd_iova_mem_map: iova-mem-map {
516 iova-mem-region-io {
517 /* IO region is approximately 3.4 GB */
518 iova-region-name = "io";
519 iova-region-start = <0x7400000>;
520 iova-region-len = <0xd8c00000>;
521 iova-region-id = <0x3>;
522 status = "ok";
523 };
524 };
525 };
526 };
527
528 qcom,cam-cpas@ac40000 {
529 cell-index = <0>;
530 compatible = "qcom,cam-cpas";
531 label = "cpas";
532 arch-compat = "cpas_top";
533 status = "ok";
534 reg-names = "cam_cpas_top", "cam_camnoc";
535 reg = <0xac40000 0x1000>,
536 <0xac42000 0x8000>;
537 reg-cam-base = <0x40000 0x42000>;
538 interrupt-names = "cpas_camnoc";
539 interrupts = <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>;
540 camnoc-axi-min-ib-bw = <3000000000>;
541 regulator-names = "camss-vdd";
542 camss-vdd-supply = <&titan_top_gdsc>;
543 clock-names =
544 "gcc_ahb_clk",
545 "gcc_axi_hf_clk",
546 "gcc_axi_sf_clk",
547 "slow_ahb_clk_src",
548 "cpas_ahb_clk",
549 "cpas_core_ahb_clk",
550 "camnoc_axi_clk_src",
551 "camnoc_axi_clk";
552 clocks =
553 <&clock_gcc GCC_CAMERA_AHB_CLK>,
554 <&clock_gcc GCC_CAMERA_HF_AXI_CLK>,
555 <&clock_gcc GCC_CAMERA_SF_AXI_CLK>,
556 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
557 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
558 <&clock_camcc CAM_CC_CORE_AHB_CLK>,
559 <&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
560 <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>;
561 src-clock-name = "camnoc_axi_clk_src";
562 clock-rates =
563 <0 0 0 0 0 0 0 0>,
564 <0 0 0 19200000 0 0 19200000 0>,
565 <0 0 0 80000000 0 0 300000000 0>,
566 <0 0 0 80000000 0 0 400000000 0>,
567 <0 0 0 80000000 0 0 400000000 0>,
568 <0 0 0 80000000 0 0 400000000 0>,
569 <0 0 0 80000000 0 0 400000000 0>,
570 <0 0 0 80000000 0 0 480000000 0>;
571 clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs",
572 "svs_l1", "nominal", "nominal_l1", "turbo";
573 control-camnoc-axi-clk;
574 camnoc-bus-width = <32>;
575 camnoc-axi-clk-bw-margin-perc = <20>;
576 qcom,msm-bus,name = "cam_ahb";
577 qcom,msm-bus,num-cases = <8>;
578 qcom,msm-bus,num-paths = <1>;
579 qcom,msm-bus,vectors-KBps =
580 <MSM_BUS_MASTER_AMPSS_M0
581 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
582 <MSM_BUS_MASTER_AMPSS_M0
583 MSM_BUS_SLAVE_CAMERA_CFG 0 76800>,
584 <MSM_BUS_MASTER_AMPSS_M0
585 MSM_BUS_SLAVE_CAMERA_CFG 0 76800>,
586 <MSM_BUS_MASTER_AMPSS_M0
587 MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
588 <MSM_BUS_MASTER_AMPSS_M0
589 MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
590 <MSM_BUS_MASTER_AMPSS_M0
591 MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
592 <MSM_BUS_MASTER_AMPSS_M0
593 MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
594 <MSM_BUS_MASTER_AMPSS_M0
595 MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
596 vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
597 RPMH_REGULATOR_LEVEL_MIN_SVS
598 RPMH_REGULATOR_LEVEL_LOW_SVS
599 RPMH_REGULATOR_LEVEL_SVS
600 RPMH_REGULATOR_LEVEL_SVS_L1
601 RPMH_REGULATOR_LEVEL_NOM
602 RPMH_REGULATOR_LEVEL_NOM_L1
603 RPMH_REGULATOR_LEVEL_NOM_L2
604 RPMH_REGULATOR_LEVEL_TURBO
605 RPMH_REGULATOR_LEVEL_TURBO_L1>;
606 vdd-corner-ahb-mapping = "suspend", "minsvs",
607 "lowsvs", "svs", "svs_l1",
608 "nominal", "nominal", "nominal",
609 "turbo", "turbo";
610 client-id-based;
611 client-names =
612 "csiphy0", "csiphy1", "csiphy2", "csiphy3",
613 "csiphy4", "csiphy5", "cci0", "cci1",
614 "csid0", "csid1", "csid2", "csid3",
615 "csid4", "csid5", "csid6", "ife0", "ife1",
616 "ife2", "ife3", "ife4", "ife5", "ife6",
617 "custom0", "ipe0", "cam-cdm-intf0", "cpas-cdm0",
618 "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", "fd0";
619
620 camera-bus-nodes {
621 level3-nodes {
622 level-index = <3>;
623 level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum {
624 cell-index = <0>;
625 node-name = "level3-rt0-rd-wr-sum";
626 traffic-merge-type =
627 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
628 qcom,axi-port-name = "cam_hf_0";
629 ib-bw-voting-needed;
630 qcom,axi-port-mnoc {
631 qcom,msm-bus,name =
632 "cam_hf_0_mnoc";
633 qcom,msm-bus-vector-dyn-vote;
634 qcom,msm-bus,num-cases = <2>;
635 qcom,msm-bus,num-paths = <1>;
636 qcom,msm-bus,vectors-KBps =
637 <MSM_BUS_MASTER_CAMNOC_HF
638 MSM_BUS_SLAVE_EBI_CH0 0 0>,
639 <MSM_BUS_MASTER_CAMNOC_HF
640 MSM_BUS_SLAVE_EBI_CH0 0 0>;
641 };
642 };
643
644 level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum {
645 cell-index = <1>;
646 node-name = "level3-nrt0-rd-wr-sum";
647 traffic-merge-type =
648 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
649 qcom,axi-port-name = "cam_sf_0";
650 qcom,axi-port-mnoc {
651 qcom,msm-bus,name =
652 "cam_sf_0_mnoc";
653 qcom,msm-bus-vector-dyn-vote;
654 qcom,msm-bus,num-cases = <2>;
655 qcom,msm-bus,num-paths = <1>;
656 qcom,msm-bus,vectors-KBps =
657 <MSM_BUS_MASTER_CAMNOC_SF
658 MSM_BUS_SLAVE_EBI_CH0 0 0>,
659 <MSM_BUS_MASTER_CAMNOC_SF
660 MSM_BUS_SLAVE_EBI_CH0 0 0>;
661 };
662 };
663
664 level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum {
665 cell-index = <2>;
666 node-name = "level3-nrt1-rd-wr-sum";
667 traffic-merge-type =
668 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
669 qcom,axi-port-name = "cam_sf_icp";
670 qcom,axi-port-mnoc {
671 qcom,msm-bus,name =
672 "cam_sf_icp_mnoc";
673 qcom,msm-bus-vector-dyn-vote;
674 qcom,msm-bus,num-cases = <2>;
675 qcom,msm-bus,num-paths = <1>;
676 qcom,msm-bus,vectors-KBps =
677 <MSM_BUS_MASTER_CAMNOC_ICP
678 MSM_BUS_SLAVE_EBI_CH0 0 0>,
679 <MSM_BUS_MASTER_CAMNOC_ICP
680 MSM_BUS_SLAVE_EBI_CH0 0 0>;
681 };
682 };
683 };
684
685 level2-nodes {
686 level-index = <2>;
687 camnoc-max-needed;
688 level2_rt0_wr: level2-rt0-wr {
689 cell-index = <3>;
690 node-name = "level2-rt0-wr";
691 parent-node = <&level3_rt0_rd_wr_sum>;
692 traffic-merge-type =
693 <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
694 };
695
696 level2_rt0_rd: level2-rt0-rd {
697 cell-index = <4>;
698 node-name = "level2-rt0-rd";
699 parent-node = <&level3_rt0_rd_wr_sum>;
700 traffic-merge-type =
701 <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
702 };
703
704 level2_nrt0_wr: level2-nrt0-wr {
705 cell-index = <5>;
706 node-name = "level2-nrt0-wr";
707 parent-node = <&level3_nrt0_rd_wr_sum>;
708 traffic-merge-type =
709 <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
710 };
711
712 level2_nrt0_rd: level2-nrt0-rd {
713 cell-index = <6>;
714 node-name = "level2-nrt0-rd";
715 parent-node = <&level3_nrt0_rd_wr_sum>;
716 traffic-merge-type =
717 <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
718 };
719
720 level2_nrt1_rd: level2-nrt1-rd {
721 cell-index = <7>;
722 node-name = "level2-nrt1-rd";
723 parent-node = <&level3_nrt1_rd_wr_sum>;
724 traffic-merge-type =
725 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
726 bus-width-factor = <4>;
727 };
728 };
729
730 level1-nodes {
731 level-index = <1>;
732 camnoc-max-needed;
733 level1_rt0_wr0: level1-rt0-wr0 {
734 cell-index = <8>;
735 node-name = "level1-rt0-wr0";
736 parent-node = <&level2_rt0_wr>;
737 traffic-merge-type =
738 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
739 };
740
741 level1_rt0_wr1: level1-rt0-wr1 {
742 cell-index = <9>;
743 node-name = "level1-rt0-wr1";
744 parent-node = <&level2_rt0_wr>;
745 traffic-merge-type =
746 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
747 };
748
749 level1_rt0_rd0: level1-rt0-rd0 {
750 cell-index = <10>;
751 node-name = "level1-rt0-rd0";
752 parent-node = <&level2_rt0_rd>;
753 traffic-merge-type =
754 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
755 };
756
757 level1_rt0_wr2: level1-rt0-wr2 {
758 cell-index = <11>;
759 node-name = "level1-rt0-wr2";
760 parent-node = <&level2_rt0_wr>;
761 traffic-merge-type =
762 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
763 };
764
765 level1_nrt0_wr0: level1-nrt0-wr0 {
766 cell-index = <12>;
767 node-name = "level1-nrt0-wr0";
768 parent-node = <&level2_nrt0_wr>;
769 traffic-merge-type =
770 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
771 };
772
773 level1_nrt0_rd0: level1-nrt0-rd0 {
774 cell-index = <13>;
775 node-name = "level1-nrt0-rd0";
776 parent-node = <&level2_nrt0_rd>;
777 traffic-merge-type =
778 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
779 };
780
781 level1_nrt0_wr1: level1-nrt0-wr1 {
782 cell-index = <14>;
783 node-name = "level1-nrt0-wr1";
784 parent-node = <&level2_nrt0_wr>;
785 traffic-merge-type =
786 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
787 };
788
789 level1_nrt0_rd2: level1-nrt0-rd2 {
790 cell-index = <15>;
791 node-name = "level1-nrt0-rd2";
792 parent-node = <&level2_nrt0_rd>;
793 traffic-merge-type =
794 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
795 };
796 };
797
798 level0-nodes {
799 level-index = <0>;
800 ife0_ubwc_stats_wr: ife0-ubwc-stats-wr {
801 cell-index = <16>;
802 node-name = "ife0-ubwc-stats-wr";
803 client-name = "ife0";
804 traffic-data =
805 <CAM_CPAS_PATH_DATA_IFE_UBWC_STATS>;
806 traffic-transaction-type =
807 <CAM_CPAS_TRANSACTION_WRITE>;
808 constituent-paths =
809 <CAM_CPAS_PATH_DATA_IFE_VID
810 CAM_CPAS_PATH_DATA_IFE_DISP
811 CAM_CPAS_PATH_DATA_IFE_STATS>;
812 parent-node = <&level1_rt0_wr0>;
813 };
814
815 ife1_ubwc_stats_wr: ife1-ubwc-stats-wr {
816 cell-index = <17>;
817 node-name = "ife1-ubwc-stats-wr";
818 client-name = "ife1";
819 traffic-data =
820 <CAM_CPAS_PATH_DATA_IFE_UBWC_STATS>;
821 traffic-transaction-type =
822 <CAM_CPAS_TRANSACTION_WRITE>;
823 constituent-paths =
824 <CAM_CPAS_PATH_DATA_IFE_VID
825 CAM_CPAS_PATH_DATA_IFE_DISP
826 CAM_CPAS_PATH_DATA_IFE_STATS>;
827 parent-node = <&level1_rt0_wr0>;
828 };
829
830 ife0_linear_pdaf_wr: ife0-linear-pdaf-wr {
831 cell-index = <18>;
832 node-name = "ife0-linear-pdaf-wr";
833 client-name = "ife0";
834 traffic-data =
835 <CAM_CPAS_PATH_DATA_IFE_LINEAR_PDAF>;
836 traffic-transaction-type =
837 <CAM_CPAS_TRANSACTION_WRITE>;
838 constituent-paths =
839 <CAM_CPAS_PATH_DATA_IFE_LINEAR
840 CAM_CPAS_PATH_DATA_IFE_PDAF>;
841 parent-node = <&level1_rt0_wr1>;
842 };
843
844 ife1_linear_pdaf_wr: ife1-linear-pdaf-wr {
845 cell-index = <19>;
846 node-name = "ife1-linear-pdaf-wr";
847 client-name = "ife1";
848 traffic-data =
849 <CAM_CPAS_PATH_DATA_IFE_LINEAR_PDAF>;
850 traffic-transaction-type =
851 <CAM_CPAS_TRANSACTION_WRITE>;
852 constituent-paths =
853 <CAM_CPAS_PATH_DATA_IFE_LINEAR
854 CAM_CPAS_PATH_DATA_IFE_PDAF>;
855 parent-node = <&level1_rt0_wr1>;
856 };
857
858 ife2_rdi_all_wr: ife2-rdi-all-wr {
859 cell-index = <20>;
860 node-name = "ife2-rdi-all-wr";
861 client-name = "ife2";
862 traffic-data =
863 <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
864 traffic-transaction-type =
865 <CAM_CPAS_TRANSACTION_WRITE>;
866 constituent-paths =
867 <CAM_CPAS_PATH_DATA_IFE_RDI0
868 CAM_CPAS_PATH_DATA_IFE_RDI1
869 CAM_CPAS_PATH_DATA_IFE_RDI2
870 CAM_CPAS_PATH_DATA_IFE_RDI3>;
871 parent-node = <&level1_rt0_wr1>;
872 };
873
874 ife3_rdi_all_wr: ife3-rdi-all-wr {
875 cell-index = <21>;
876 node-name = "ife3-rdi-all-wr";
877 client-name = "ife3";
878 traffic-data =
879 <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
880 traffic-transaction-type =
881 <CAM_CPAS_TRANSACTION_WRITE>;
882 constituent-paths =
883 <CAM_CPAS_PATH_DATA_IFE_RDI0
884 CAM_CPAS_PATH_DATA_IFE_RDI1
885 CAM_CPAS_PATH_DATA_IFE_RDI2
886 CAM_CPAS_PATH_DATA_IFE_RDI3>;
887 parent-node = <&level1_rt0_wr1>;
888 };
889
890 ife4_rdi_all_wr: ife4-rdi-all-wr {
891 cell-index = <22>;
892 node-name = "ife4-rdi-all-wr";
893 client-name = "ife4";
894 traffic-data =
895 <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
896 traffic-transaction-type =
897 <CAM_CPAS_TRANSACTION_WRITE>;
898 constituent-paths =
899 <CAM_CPAS_PATH_DATA_IFE_RDI0
900 CAM_CPAS_PATH_DATA_IFE_RDI1
901 CAM_CPAS_PATH_DATA_IFE_RDI2
902 CAM_CPAS_PATH_DATA_IFE_RDI3>;
903 parent-node = <&level1_rt0_wr1>;
904 };
905
906 ife5_rdi_all_wr: ife5-rdi-all-wr {
907 cell-index = <23>;
908 node-name = "ife5-rdi-all-wr";
909 client-name = "ife5";
910 traffic-data =
911 <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
912 traffic-transaction-type =
913 <CAM_CPAS_TRANSACTION_WRITE>;
914 constituent-paths =
915 <CAM_CPAS_PATH_DATA_IFE_RDI0
916 CAM_CPAS_PATH_DATA_IFE_RDI1
917 CAM_CPAS_PATH_DATA_IFE_RDI2
918 CAM_CPAS_PATH_DATA_IFE_RDI3>;
919 parent-node = <&level1_rt0_wr1>;
920 };
921
922 ife0_rdi_all_rd: ife0-rdi-all-rd {
923 cell-index = <24>;
924 node-name = "ife0-rdi-all-rd";
925 client-name = "ife0";
926 traffic-data =
927 <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
928 traffic-transaction-type =
929 <CAM_CPAS_TRANSACTION_READ>;
930 constituent-paths =
931 <CAM_CPAS_PATH_DATA_IFE_RDI0
932 CAM_CPAS_PATH_DATA_IFE_RDI1
933 CAM_CPAS_PATH_DATA_IFE_RDI2
934 CAM_CPAS_PATH_DATA_IFE_RDI3>;
935 parent-node = <&level1_rt0_rd0>;
936 };
937
938 ife1_rdi_all_rd: ife1-rdi-all-rd {
939 cell-index = <25>;
940 node-name = "ife1-rdi-all-rd";
941 client-name = "ife1";
942 traffic-data =
943 <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
944 traffic-transaction-type =
945 <CAM_CPAS_TRANSACTION_READ>;
946 constituent-paths =
947 <CAM_CPAS_PATH_DATA_IFE_RDI0
948 CAM_CPAS_PATH_DATA_IFE_RDI1
949 CAM_CPAS_PATH_DATA_IFE_RDI2
950 CAM_CPAS_PATH_DATA_IFE_RDI3>;
951 parent-node = <&level1_rt0_rd0>;
952 };
953
954 custom0_all_rd: custom0-all-rd {
955 cell-index = <26>;
956 node-name = "custom0-all-rd";
957 client-name = "custom0";
958 traffic-data =
959 <CAM_CPAS_PATH_DATA_ALL>;
960 traffic-transaction-type =
961 <CAM_CPAS_TRANSACTION_READ>;
962 parent-node = <&level1_rt0_rd0>;
963 };
964
965 ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr {
966 cell-index = <27>;
967 node-name = "ife0-rdi-pixel-raw-wr";
968 client-name = "ife0";
969 traffic-data =
970 <CAM_CPAS_PATH_DATA_IFE_RDI_PIXEL_RAW>;
971 traffic-transaction-type =
972 <CAM_CPAS_TRANSACTION_WRITE>;
973 constituent-paths =
974 <CAM_CPAS_PATH_DATA_IFE_RDI0
975 CAM_CPAS_PATH_DATA_IFE_RDI1
976 CAM_CPAS_PATH_DATA_IFE_RDI2
977 CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
978 parent-node = <&level1_rt0_wr2>;
979 };
980
981 ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr {
982 cell-index = <28>;
983 node-name = "ife1-rdi-pixel-raw-wr";
984 client-name = "ife1";
985 traffic-data =
986 <CAM_CPAS_PATH_DATA_IFE_RDI_PIXEL_RAW>;
987 traffic-transaction-type =
988 <CAM_CPAS_TRANSACTION_WRITE>;
989 constituent-paths =
990 <CAM_CPAS_PATH_DATA_IFE_RDI0
991 CAM_CPAS_PATH_DATA_IFE_RDI1
992 CAM_CPAS_PATH_DATA_IFE_RDI2
993 CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
994 parent-node = <&level1_rt0_wr2>;
995 };
996
997 ife6_rdi_all_wr: ife6-rdi-all-wr {
998 cell-index = <29>;
999 node-name = "ife6-rdi-all-wr";
1000 client-name = "ife6";
1001 traffic-data =
1002 <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
1003 traffic-transaction-type =
1004 <CAM_CPAS_TRANSACTION_WRITE>;
1005 constituent-paths =
1006 <CAM_CPAS_PATH_DATA_IFE_RDI0
1007 CAM_CPAS_PATH_DATA_IFE_RDI1
1008 CAM_CPAS_PATH_DATA_IFE_RDI2
1009 CAM_CPAS_PATH_DATA_IFE_RDI3>;
1010 parent-node = <&level1_rt0_wr2>;
1011 };
1012
1013 custom0_all_wr: custom0-all-wr {
1014 cell-index = <30>;
1015 node-name = "custom0-all-wr";
1016 client-name = "custom0";
1017 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
1018 traffic-transaction-type =
1019 <CAM_CPAS_TRANSACTION_WRITE>;
1020 parent-node = <&level1_rt0_wr2>;
1021 };
1022
1023 ipe0_all_wr: ipe0-all-wr {
1024 cell-index = <31>;
1025 node-name = "ipe0-all-wr";
1026 client-name = "ipe0";
1027 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
1028 traffic-transaction-type =
1029 <CAM_CPAS_TRANSACTION_WRITE>;
1030 constituent-paths =
1031 <CAM_CPAS_PATH_DATA_IPE_WR_VID
1032 CAM_CPAS_PATH_DATA_IPE_WR_DISP
1033 CAM_CPAS_PATH_DATA_IPE_WR_REF>;
1034 parent-node = <&level1_nrt0_wr0>;
1035 };
1036
1037 bps0_all_wr: bps0-all-wr {
1038 cell-index = <32>;
1039 node-name = "bps0-all-wr";
1040 client-name = "bps0";
1041 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
1042 traffic-transaction-type =
1043 <CAM_CPAS_TRANSACTION_WRITE>;
1044 parent-node = <&level1_nrt0_wr0>;
1045 };
1046
1047 ipe0_ref_rd: ipe0-ref-rd {
1048 cell-index = <33>;
1049 node-name = "ipe0-ref-rd";
1050 client-name = "ipe0";
1051 traffic-data =
1052 <CAM_CPAS_PATH_DATA_IPE_RD_REF>;
1053 traffic-transaction-type =
1054 <CAM_CPAS_TRANSACTION_READ>;
1055 parent-node = <&level1_nrt0_rd0>;
1056 };
1057
1058 bps0_all_rd: bps0-all-rd {
1059 cell-index = <34>;
1060 node-name = "bps0-all-rd";
1061 client-name = "bps0";
1062 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
1063 traffic-transaction-type =
1064 <CAM_CPAS_TRANSACTION_READ>;
1065 parent-node = <&level1_nrt0_rd0>;
1066 };
1067
1068 ipe0_in_rd: ipe0-in-rd {
1069 cell-index = <35>;
1070 node-name = "ipe0-in-rd";
1071 client-name = "ipe0";
1072 traffic-data =
1073 <CAM_CPAS_PATH_DATA_IPE_RD_IN>;
1074 traffic-transaction-type =
1075 <CAM_CPAS_TRANSACTION_READ>;
1076 parent-node = <&level2_nrt0_rd>;
1077 };
1078
1079 jpeg_enc0_all_wr: jpeg-enc0-all-wr {
1080 cell-index = <36>;
1081 node-name = "jpeg-enc0-all-wr";
1082 client-name = "jpeg-enc0";
1083 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
1084 traffic-transaction-type =
1085 <CAM_CPAS_TRANSACTION_WRITE>;
1086 parent-node = <&level1_nrt0_wr1>;
1087 };
1088
1089 jpeg_dma0_all_wr: jpeg-dma0-all-wr {
1090 cell-index = <37>;
1091 node-name = "jpeg-dma0-all-wr";
1092 client-name = "jpeg-dma0";
1093 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
1094 traffic-transaction-type =
1095 <CAM_CPAS_TRANSACTION_WRITE>;
1096 parent-node = <&level1_nrt0_wr1>;
1097 };
1098
1099 jpeg_enc0_all_rd: jpeg-enc0-all-rd {
1100 cell-index = <38>;
1101 node-name = "jpeg-enc0-all-rd";
1102 client-name = "jpeg-enc0";
1103 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
1104 traffic-transaction-type =
1105 <CAM_CPAS_TRANSACTION_READ>;
1106 parent-node = <&level1_nrt0_rd2>;
1107 };
1108
1109 jpeg_dma0_all_rd: jpeg-dma0-all-rd {
1110 cell-index = <39>;
1111 node-name = "jpeg-dma0-all-rd";
1112 client-name = "jpeg-dma0";
1113 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
1114 traffic-transaction-type =
1115 <CAM_CPAS_TRANSACTION_READ>;
1116 parent-node = <&level1_nrt0_rd2>;
1117 };
1118
1119 fd0_all_wr: fd0-all-wr {
1120 cell-index = <40>;
1121 node-name = "fd0-all-wr";
1122 client-name = "fd0";
1123 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
1124 traffic-transaction-type =
1125 <CAM_CPAS_TRANSACTION_WRITE>;
1126 parent-node = <&level2_nrt0_wr>;
1127 };
1128
1129 fd0_all_rd: fd0-all-rd {
1130 cell-index = <41>;
1131 node-name = "fd0-all-rd";
1132 client-name = "fd0";
1133 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
1134 traffic-transaction-type =
1135 <CAM_CPAS_TRANSACTION_READ>;
1136 parent-node = <&level2_nrt0_rd>;
1137 };
1138
1139 cpas_cdm0_all_rd: cpas-cdm0-all-rd {
1140 cell-index = <42>;
1141 node-name = "cpas-cdm0-all-rd";
1142 client-name = "cpas-cdm0";
1143 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
1144 traffic-transaction-type =
1145 <CAM_CPAS_TRANSACTION_READ>;
1146 parent-node = <&level2_nrt0_rd>;
1147 };
1148
1149 icp0_all_rd: icp0-all-rd {
1150 cell-index = <43>;
1151 node-name = "icp0-all-rd";
1152 client-name = "icp0";
1153 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
1154 traffic-transaction-type =
1155 <CAM_CPAS_TRANSACTION_READ>;
1156 parent-node = <&level2_nrt1_rd>;
1157 };
1158 };
1159 };
1160 };
1161
1162 qcom,cam-cdm-intf {
1163 compatible = "qcom,cam-cdm-intf";
1164 cell-index = <0>;
1165 label = "cam-cdm-intf";
1166 num-hw-cdm = <3>;
1167 cdm-client-names = "vfe",
1168 "jpegdma",
1169 "jpegenc",
1170 "fd";
1171 status = "ok";
1172 };
1173
1174 qcom,cpas-cdm0@ac4d000 {
1175 cell-index = <0>;
1176 compatible = "qcom,cam170-cpas-cdm0";
1177 label = "cpas-cdm";
1178 reg = <0xac4d000 0x1000>;
1179 reg-names = "cpas-cdm";
1180 reg-cam-base = <0x4d000>;
1181 interrupts = <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>;
1182 interrupt-names = "cpas-cdm";
1183 regulator-names = "camss";
1184 camss-supply = <&titan_top_gdsc>;
1185 clock-names = "cam_cc_cpas_slow_ahb_clk",
1186 "cam_cc_cpas_ahb_clk";
1187 clocks = <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
1188 <&clock_camcc CAM_CC_CPAS_AHB_CLK>;
1189 clock-rates = <0 0>;
1190 clock-cntl-level = "svs";
1191 cdm-client-names = "ife";
1192 status = "ok";
1193 };
1194
1195 qcom,cpas-cdm1@acb4200 {
1196 cell-index = <1>;
1197 compatible = "qcom,cam480-cpas-cdm1";
1198 label = "cpas-cdm";
1199 reg = <0xacb4200 0x1000>;
1200 reg-names = "cpas-cdm";
1201 reg-cam-base = <0xb4200>;
1202 interrupts = <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>;
1203 interrupt-names = "cpas-cdm";
1204 regulator-names = "camss";
1205 camss-supply = <&titan_top_gdsc>;
1206 clock-names = "cam_cc_cpas_slow_ahb_clk",
1207 "cam_cc_cpas_ahb_clk";
1208 clocks = <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
1209 <&clock_camcc CAM_CC_CPAS_AHB_CLK>;
1210 clock-rates = <0 0>;
1211 clock-cntl-level = "svs";
1212 cdm-client-names = "ife0";
1213 status = "disabled";
1214 };
1215
1216 qcom,cpas-cdm2@acc3200 {
1217 cell-index = <2>;
1218 compatible = "qcom,cam480-cpas-cdm2";
1219 label = "cpas-cdm";
1220 reg = <0xacc3200 0x1000>;
1221 reg-names = "cpas-cdm";
1222 reg-cam-base = <0xc3200>;
1223 interrupts = <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>;
1224 interrupt-names = "cpas-cdm";
1225 regulator-names = "camss";
1226 camss-supply = <&titan_top_gdsc>;
1227 clock-names = "cam_cc_cpas_slow_ahb_clk",
1228 "cam_cc_cpas_ahb_clk";
1229 clocks = <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
1230 <&clock_camcc CAM_CC_CPAS_AHB_CLK>;
1231 clock-rates = <0 0>;
1232 clock-cntl-level = "svs";
1233 cdm-client-names = "ife1";
1234 status = "disabled";
1235 };
1236
1237 qcom,cam-isp {
1238 compatible = "qcom,cam-isp";
1239 arch-compat = "ife";
1240 status = "ok";
1241 };
1242
1243 cam_csid0: qcom,csid0@acb5200 {
1244 cell-index = <0>;
1245 compatible = "qcom,csid480";
1246 reg-names = "csid";
1247 reg = <0xacb5200 0x1000>;
1248 reg-cam-base = <0xb5200>;
1249 interrupt-names = "csid";
1250 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>;
1251 regulator-names = "camss", "ife0";
1252 camss-supply = <&titan_top_gdsc>;
1253 ife0-supply = <&ife_0_gdsc>;
1254 clock-names =
1255 "ife_csid_clk_src",
1256 "ife_csid_clk",
1257 "cphy_rx_clk_src",
1258 "ife_cphy_rx_clk",
1259 "ife_clk_src",
1260 "ife_clk",
1261 "ife_0_areg",
1262 "ife_0_ahb",
1263 "ife_axi_clk";
1264 clocks =
1265 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
1266 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
1267 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
1268 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
1269 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
1270 <&clock_camcc CAM_CC_IFE_0_CLK>,
1271 <&clock_camcc CAM_CC_IFE_0_AREG_CLK>,
1272 <&clock_camcc CAM_CC_IFE_0_AHB_CLK>,
1273 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>;
1274 clock-rates =
1275 <400000000 0 400000000 0 350000000 0 100000000 0 0>,
1276 <400000000 0 400000000 0 475000000 0 200000000 0 0>,
1277 <400000000 0 400000000 0 576000000 0 300000000 0 0>,
1278 <400000000 0 400000000 0 720000000 0 400000000 0 0>;
1279 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
1280 src-clock-name = "ife_csid_clk_src";
1281 clock-control-debugfs = "true";
1282 status = "ok";
1283 };
1284
1285 cam_vfe0: qcom,ife0@acb4000 {
1286 cell-index = <0>;
1287 compatible = "qcom,vfe480";
1288 reg-names = "ife", "cam_camnoc";
1289 reg = <0xacb4000 0xd000>,
1290 <0xac42000 0x8000>;
1291 reg-cam-base = <0xb4000 0x42000>;
1292 interrupt-names = "ife";
1293 interrupts = <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
1294 regulator-names = "camss", "ife0";
1295 camss-supply = <&titan_top_gdsc>;
1296 ife0-supply = <&ife_0_gdsc>;
1297 clock-names =
1298 "ife_0_ahb",
1299 "ife_0_areg",
1300 "ife_clk_src",
1301 "ife_clk",
1302 "ife_axi_clk";
1303 clocks =
1304 <&clock_camcc CAM_CC_IFE_0_AHB_CLK>,
1305 <&clock_camcc CAM_CC_IFE_0_AREG_CLK>,
1306 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
1307 <&clock_camcc CAM_CC_IFE_0_CLK>,
1308 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>;
1309 clock-rates =
1310 <0 100000000 350000000 0 0>,
1311 <0 200000000 475000000 0 0>,
1312 <0 300000000 576000000 0 0>,
1313 <0 400000000 720000000 0 0>;
1314 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
1315 src-clock-name = "ife_clk_src";
1316 scl-clk-names = "ife_0_areg";
1317 clock-control-debugfs = "true";
1318 clock-names-option = "ife_dsp_clk";
1319 clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>;
1320 clock-rates-option = <720000000>;
1321 ubwc-static-cfg = <0x1026 0x1036>;
1322 status = "ok";
1323 };
1324
1325 cam_csid1: qcom,csid1@acc4200 {
1326 cell-index = <1>;
1327 compatible = "qcom,csid480";
1328 reg-names = "csid";
1329 reg = <0xacc4200 0x1000>;
1330 reg-cam-base = <0xc4200>;
1331 interrupt-names = "csid";
1332 interrupts = <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>;
1333 regulator-names = "camss", "ife1";
1334 camss-supply = <&titan_top_gdsc>;
1335 ife1-supply = <&ife_1_gdsc>;
1336 clock-names =
1337 "ife_csid_clk_src",
1338 "ife_csid_clk",
1339 "cphy_rx_clk_src",
1340 "ife_cphy_rx_clk",
1341 "ife_clk_src",
1342 "ife_clk",
1343 "ife_1_areg",
1344 "ife_1_ahb",
1345 "ife_axi_clk";
1346 clocks =
1347 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
1348 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
1349 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
1350 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
1351 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
1352 <&clock_camcc CAM_CC_IFE_1_CLK>,
1353 <&clock_camcc CAM_CC_IFE_1_AREG_CLK>,
1354 <&clock_camcc CAM_CC_IFE_1_AHB_CLK>,
1355 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>;
1356 clock-rates =
1357 <400000000 0 400000000 0 350000000 0 100000000 0 0>,
1358 <400000000 0 400000000 0 475000000 0 200000000 0 0>,
1359 <400000000 0 400000000 0 576000000 0 300000000 0 0>,
1360 <400000000 0 400000000 0 720000000 0 400000000 0 0>;
1361 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
1362 src-clock-name = "ife_csid_clk_src";
1363 clock-control-debugfs = "true";
1364 status = "ok";
1365 };
1366
1367 cam_vfe1: qcom,ife1@acc3000 {
1368 cell-index = <1>;
1369 compatible = "qcom,vfe480";
1370 reg-names = "ife", "cam_camnoc";
1371 reg = <0xacc3000 0xd000>,
1372 <0xac42000 0x8000>;
1373 reg-cam-base = <0xc3000 0x42000>;
1374 interrupt-names = "ife";
1375 interrupts = <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>;
1376 regulator-names = "camss", "ife1";
1377 camss-supply = <&titan_top_gdsc>;
1378 ife1-supply = <&ife_1_gdsc>;
1379 clock-names =
1380 "ife_1_ahb",
1381 "ife_1_areg",
1382 "ife_clk_src",
1383 "ife_clk",
1384 "ife_axi_clk";
1385 clocks =
1386 <&clock_camcc CAM_CC_IFE_1_AHB_CLK>,
1387 <&clock_camcc CAM_CC_IFE_1_AREG_CLK>,
1388 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
1389 <&clock_camcc CAM_CC_IFE_1_CLK>,
1390 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>;
1391 clock-rates =
1392 <0 100000000 350000000 0 0>,
1393 <0 200000000 475000000 0 0>,
1394 <0 300000000 576000000 0 0>,
1395 <0 400000000 720000000 0 0>;
1396 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
1397 src-clock-name = "ife_clk_src";
1398 scl-clk-names = "ife_1_areg";
1399 clock-control-debugfs = "true";
1400 clock-names-option = "ife_dsp_clk";
1401 clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>;
1402 clock-rates-option = <720000000>;
1403 ubwc-static-cfg = <0x1026 0x1036>;
1404 status = "ok";
1405 };
1406
1407 cam_csid_lite0: qcom,csid-lite0@acd9200 {
1408 cell-index = <2>;
1409 compatible = "qcom,csid-lite480";
1410 reg-names = "csid-lite";
1411 reg = <0xacd9200 0x1000>;
1412 reg-cam-base = <0xd9200>;
1413 interrupt-names = "csid-lite";
1414 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>;
1415 regulator-names = "camss";
1416 camss-supply = <&titan_top_gdsc>;
1417 clock-names =
1418 "ife_csid_clk_src",
1419 "ife_csid_clk",
1420 "cphy_rx_clk_src",
1421 "ife_cphy_rx_clk",
1422 "ife_clk_src",
1423 "ife_lite_ahb",
1424 "ife_clk";
1425 clocks =
1426 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
1427 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
1428 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
1429 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
1430 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
1431 <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
1432 <&clock_camcc CAM_CC_IFE_LITE_CLK>;
1433 clock-rates =
1434 <400000000 0 0 0 400000000 0 0>,
1435 <400000000 0 0 0 480000000 0 0>,
1436 <400000000 0 0 0 480000000 0 0>,
1437 <400000000 0 0 0 480000000 0 0>;
1438 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
1439 src-clock-name = "ife_csid_clk_src";
1440 clock-control-debugfs = "true";
1441 status = "ok";
1442 };
1443
1444 cam_vfe_lite0: qcom,ife-lite0@acd9000 {
1445 cell-index = <2>;
1446 compatible = "qcom,vfe-lite480";
1447 reg-names = "ife-lite";
1448 reg = <0xacd9000 0x2200>;
1449 reg-cam-base = <0xd9000>;
1450 interrupt-names = "ife-lite";
1451 interrupts = <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
1452 regulator-names = "camss";
1453 camss-supply = <&titan_top_gdsc>;
1454 clock-names =
1455 "ife_lite_ahb",
1456 "ife_lite_axi",
1457 "ife_clk_src",
1458 "ife_clk";
1459 clocks =
1460 <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
1461 <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>,
1462 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
1463 <&clock_camcc CAM_CC_IFE_LITE_CLK>;
1464 clock-rates =
1465 <0 0 400000000 0>,
1466 <0 0 480000000 0>,
1467 <0 0 480000000 0>,
1468 <0 0 480000000 0>;
1469 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
1470 src-clock-name = "ife_clk_src";
1471 clock-control-debugfs = "true";
1472 status = "ok";
1473 };
1474
1475 cam_csid_lite1: qcom,csid-lite1@acdb400 {
1476 cell-index = <3>;
1477 compatible = "qcom,csid-lite480";
1478 reg-names = "csid-lite";
1479 reg = <0xacdb400 0x1000>;
1480 reg-cam-base = <0xdb400>;
1481 interrupt-names = "csid-lite";
1482 interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>;
1483 regulator-names = "camss";
1484 camss-supply = <&titan_top_gdsc>;
1485 clock-names =
1486 "ife_csid_clk_src",
1487 "ife_csid_clk",
1488 "cphy_rx_clk_src",
1489 "ife_cphy_rx_clk",
1490 "ife_clk_src",
1491 "ife_lite_ahb",
1492 "ife_clk";
1493 clocks =
1494 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
1495 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
1496 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
1497 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
1498 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
1499 <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
1500 <&clock_camcc CAM_CC_IFE_LITE_CLK>;
1501 clock-rates =
1502 <400000000 0 0 0 400000000 0 0>,
1503 <400000000 0 0 0 480000000 0 0>,
1504 <400000000 0 0 0 480000000 0 0>,
1505 <400000000 0 0 0 480000000 0 0>;
1506 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
1507 src-clock-name = "ife_csid_clk_src";
1508 clock-control-debugfs = "true";
1509 status = "ok";
1510 };
1511
1512 cam_vfe_lite1: qcom,ife-lite1@acdb200 {
1513 cell-index = <3>;
1514 compatible = "qcom,vfe-lite480";
1515 reg-names = "ife-lite";
1516 reg = <0xacdb200 0x2200>;
1517 reg-cam-base = <0xdb200>;
1518 interrupt-names = "ife-lite";
1519 interrupts = <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
1520 regulator-names = "camss";
1521 camss-supply = <&titan_top_gdsc>;
1522 clock-names =
1523 "ife_lite_ahb",
1524 "ife_lite_axi",
1525 "ife_clk_src",
1526 "ife_clk";
1527 clocks =
1528 <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
1529 <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>,
1530 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
1531 <&clock_camcc CAM_CC_IFE_LITE_CLK>;
1532 clock-rates =
1533 <0 0 400000000 0>,
1534 <0 0 480000000 0>,
1535 <0 0 480000000 0>,
1536 <0 0 480000000 0>;
1537 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
1538 src-clock-name = "ife_clk_src";
1539 clock-control-debugfs = "true";
1540 status = "ok";
1541 };
1542
1543 qcom,cam-icp {
1544 compatible = "qcom,cam-icp";
1545 compat-hw-name = "qcom,a5",
1546 "qcom,ipe0",
1547 "qcom,bps";
1548 num-a5 = <1>;
1549 num-ipe = <1>;
1550 num-bps = <1>;
1551 status = "ok";
1552 icp_pc_en;
1553 ipe_bps_pc_en;
1554 };
1555
1556 cam_a5: qcom,a5@ac00000 {
1557 cell-index = <0>;
1558 compatible = "qcom,cam-a5";
1559 reg = <0xac00000 0x6000>,
1560 <0xac10000 0x8000>,
1561 <0xac18000 0x3000>;
1562 reg-names = "a5_qgic", "a5_sierra", "a5_csr";
1563 reg-cam-base = <0x00000 0x10000 0x18000>;
1564 interrupts = <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>;
1565 interrupt-names = "a5";
1566 regulator-names = "camss-vdd";
1567 camss-vdd-supply = <&titan_top_gdsc>;
1568 clock-names =
1569 "soc_fast_ahb",
1570 "icp_ahb_clk",
1571 "icp_clk_src",
1572 "icp_clk";
1573 src-clock-name = "icp_clk_src";
1574 clocks =
1575 <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>,
1576 <&clock_camcc CAM_CC_ICP_AHB_CLK>,
1577 <&clock_camcc CAM_CC_ICP_CLK_SRC>,
1578 <&clock_camcc CAM_CC_ICP_CLK>;
1579
1580 clock-rates =
1581 <100000000 0 400000000 0>,
1582 <200000000 0 480000000 0>,
1583 <300000000 0 600000000 0>,
1584 <400000000 0 600000000 0>,
1585 <400000000 0 600000000 0>;
1586 clock-cntl-level = "lowsvs", "svs", "svs_l1",
1587 "nominal", "turbo";
1588 fw_name = "CAMERA_ICP.elf";
1589 ubwc-ipe-fetch-cfg = <0x707b 0x7083>;
1590 ubwc-ipe-write-cfg = <0x161ef 0x1620f>;
1591 ubwc-bps-fetch-cfg = <0x707b 0x7083>;
1592 ubwc-bps-write-cfg = <0x161ef 0x1620f>;
1593 status = "ok";
1594 };
1595
1596 cam_ipe0: qcom,ipe0 {
1597 cell-index = <0>;
1598 compatible = "qcom,cam-ipe";
1599 reg = <0xac9a000 0xc000>;
1600 reg-names = "ipe0_top";
1601 reg-cam-base = <0x9a000>;
1602 regulator-names = "ipe0-vdd";
1603 ipe0-vdd-supply = <&ipe_0_gdsc>;
1604 clock-names =
1605 "ipe_0_ahb_clk",
1606 "ipe_0_areg_clk",
1607 "ipe_0_axi_clk",
1608 "ipe_0_clk_src",
1609 "ipe_0_clk";
1610 src-clock-name = "ipe_0_clk_src";
1611 clock-control-debugfs = "true";
1612 clocks =
1613 <&clock_camcc CAM_CC_IPE_0_AHB_CLK>,
1614 <&clock_camcc CAM_CC_IPE_0_AREG_CLK>,
1615 <&clock_camcc CAM_CC_IPE_0_AXI_CLK>,
1616 <&clock_camcc CAM_CC_IPE_0_CLK_SRC>,
1617 <&clock_camcc CAM_CC_IPE_0_CLK>;
1618
1619 clock-rates =
1620 <0 0 0 300000000 0>,
1621 <0 0 0 475000000 0>,
1622 <0 0 0 525000000 0>,
1623 <0 0 0 700000000 0>,
1624 <0 0 0 700000000 0>;
1625 clock-cntl-level = "lowsvs", "svs", "svs_l1",
1626 "nominal", "turbo";
1627 status = "ok";
1628 };
1629
1630 cam_bps: qcom,bps {
1631 cell-index = <0>;
1632 compatible = "qcom,cam-bps";
1633 reg = <0xac7a000 0x8000>;
1634 reg-names = "bps_top";
1635 reg-cam-base = <0x7a000>;
1636 regulator-names = "bps-vdd";
1637 bps-vdd-supply = <&bps_gdsc>;
1638 clock-names =
1639 "bps_ahb_clk",
1640 "bps_areg_clk",
1641 "bps_axi_clk",
1642 "bps_clk_src",
1643 "bps_clk";
1644 src-clock-name = "bps_clk_src";
1645 clock-control-debugfs = "true";
1646 clocks =
1647 <&clock_camcc CAM_CC_BPS_AHB_CLK>,
1648 <&clock_camcc CAM_CC_BPS_AREG_CLK>,
1649 <&clock_camcc CAM_CC_BPS_AXI_CLK>,
1650 <&clock_camcc CAM_CC_BPS_CLK_SRC>,
1651 <&clock_camcc CAM_CC_BPS_CLK>;
1652
1653 clock-rates =
1654 <0 0 0 200000000 0>,
1655 <0 0 0 400000000 0>,
1656 <0 0 0 480000000 0>,
1657 <0 0 0 600000000 0>,
1658 <0 0 0 600000000 0>;
1659 clock-cntl-level = "lowsvs", "svs", "svs_l1",
1660 "nominal", "turbo";
1661 status = "ok";
1662 };
1663
1664 qcom,cam-jpeg {
1665 compatible = "qcom,cam-jpeg";
1666 compat-hw-name = "qcom,jpegenc",
1667 "qcom,jpegdma";
1668 num-jpeg-enc = <1>;
1669 num-jpeg-dma = <1>;
1670 status = "ok";
1671 };
1672
1673 cam_jpeg_enc: qcom,jpegenc@ac53000 {
1674 cell-index = <0>;
1675 compatible = "qcom,cam_jpeg_enc";
1676 reg-names = "jpege_hw";
1677 reg = <0xac53000 0x4000>;
1678 reg-cam-base = <0x53000>;
1679 interrupt-names = "jpeg";
1680 interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>;
1681 regulator-names = "camss-vdd";
1682 camss-vdd-supply = <&titan_top_gdsc>;
1683 clock-names =
1684 "jpegenc_clk_src",
1685 "jpegenc_clk";
1686 clocks =
1687 <&clock_camcc CAM_CC_JPEG_CLK_SRC>,
1688 <&clock_camcc CAM_CC_JPEG_CLK>;
1689
1690 clock-rates = <600000000 0>;
1691 src-clock-name = "jpegenc_clk_src";
1692 clock-cntl-level = "nominal";
1693 status = "ok";
1694 };
1695
1696 cam_jpeg_dma: qcom,jpegdma@ac57000 {
1697 cell-index = <0>;
1698 compatible = "qcom,cam_jpeg_dma";
1699 reg-names = "jpegdma_hw";
1700 reg = <0xac57000 0x4000>;
1701 reg-cam-base = <0x57000>;
1702 interrupt-names = "jpegdma";
1703 interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>;
1704 regulator-names = "camss-vdd";
1705 camss-vdd-supply = <&titan_top_gdsc>;
1706 clock-names =
1707 "jpegdma_clk_src",
1708 "jpegdma_clk";
1709 clocks =
1710 <&clock_camcc CAM_CC_JPEG_CLK_SRC>,
1711 <&clock_camcc CAM_CC_JPEG_CLK>;
1712
1713 clock-rates = <600000000 0>;
1714 src-clock-name = "jpegdma_clk_src";
1715 clock-cntl-level = "nominal";
1716 status = "ok";
1717 };
1718
1719 qcom,cam-fd {
1720 compatible = "qcom,cam-fd";
1721 compat-hw-name = "qcom,fd";
1722 num-fd = <1>;
1723 status = "ok";
1724 };
1725
1726 cam_fd: qcom,fd@ac5f000 {
1727 cell-index = <0>;
1728 compatible = "qcom,fd600";
1729 reg-names = "fd_core", "fd_wrapper";
1730 reg = <0xac5f000 0x1000>,
1731 <0xac60000 0x400>;
1732 reg-cam-base = <0x5f000 0x60000>;
1733 interrupt-names = "fd";
1734 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
1735 regulator-names = "camss-vdd";
1736 camss-vdd-supply = <&titan_top_gdsc>;
1737 clock-names =
1738 "fd_core_clk_src",
1739 "fd_core_clk",
1740 "fd_core_uar_clk";
1741 clocks =
1742 <&clock_camcc CAM_CC_FD_CORE_CLK_SRC>,
1743 <&clock_camcc CAM_CC_FD_CORE_CLK>,
1744 <&clock_camcc CAM_CC_FD_CORE_UAR_CLK>;
1745 src-clock-name = "fd_core_clk_src";
1746 clock-control-debugfs = "true";
1747 clock-cntl-level = "svs", "svs_l1", "turbo";
1748 clock-rates =
1749 <400000000 0 0>,
1750 <480000000 0 0>,
1751 <600000000 0 0>;
1752 status = "ok";
1753 };
1754};