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gerrit-public.fairphone.software / kernel / msm-4.19 / 9b0224459fa8ee7c60d16a0b710ebf039da9f365 / . / arch / arm64 / boot / dts / vendor / qcom / camera / scuba-camera.dtsi
blob: beff5884daf87d2e31d7f22af4e7cfe1331a3322 [file] [log] [blame]
Luca Weiss9b022442023-04-14 14:47:36 +0200[diff] [blame^]1#include <dt-bindings/msm/msm-camera.h>
2
3&soc {
4 qcom,cam-req-mgr {
5 compatible = "qcom,cam-req-mgr";
6 status = "ok";
7 };
8
9 cam_csiphy0: qcom,csiphy0 {
10 cell-index = <0>;
11 compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
12 reg = <0x05C52000 0x1000>;
13 reg-names = "csiphy";
14 reg-cam-base = <0x52000>;
15 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
16 interrupt-names = "csiphy";
17 regulator-names = "gdscr";
18 gdscr-supply = <&gcc_camss_top_gdsc>;
19 csi-vdd-voltage = <1200000>;
20 mipi-csi-vdd-supply = <&L5A>;
21 clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
22 <&gcc GCC_CAMSS_CPHY_0_CLK>,
23 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>,
24 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>;
25 clock-names = "cphy_rx_clk_src",
26 "csiphy0_clk",
27 "csi0phytimer_clk_src",
28 "csi0phytimer_clk";
29 src-clock-name = "csi0phytimer_clk_src";
30 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
31 clock-rates =
32 <19200000 0 19200000 0>,
33 <341330000 0 200000000 0>,
34 <341330000 0 200000000 0>,
35 <384000000 0 268800000 0>;
36 status = "ok";
37 };
38
39 cam_csiphy1: qcom,csiphy1 {
40 cell-index = <1>;
41 compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
42 reg = <0x05C53000 0x1000>;
43 reg-names = "csiphy";
44 reg-cam-base = <0x53000>;
45 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
46 interrupt-names = "csiphy";
47 regulator-names = "gdscr";
48 gdscr-supply = <&gcc_camss_top_gdsc>;
49 csi-vdd-voltage = <1200000>;
50 mipi-csi-vdd-supply = <&L5A>;
51 clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
52 <&gcc GCC_CAMSS_CPHY_1_CLK>,
53 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>,
54 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>;
55 clock-names = "cphy_rx_clk_src",
56 "csiphy1_clk",
57 "csi1phytimer_clk_src",
58 "csi1phytimer_clk";
59 src-clock-name = "csi1phytimer_clk_src";
60 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
61 clock-rates =
62 <19200000 0 19200000 0>,
63 <341330000 0 200000000 0>,
64 <341330000 0 200000000 0>,
65 <384000000 0 268800000 0>;
66 status = "ok";
67 };
68
69 cam_cci0: qcom,cci0 {
70 cell-index = <0>;
71 compatible = "qcom,cci";
72 #address-cells = <1>;
73 #size-cells = <0>;
74 reg = <0x05C1B000 0x1000>;
75 reg-names = "cci";
76 reg-cam-base = <0x1B000>;
77 interrupt-names = "cci";
78 interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
79 status = "ok";
80 gdscr-supply = <&gcc_camss_top_gdsc>;
81 regulator-names = "gdscr";
82 clocks = <&gcc GCC_CAMSS_CCI_0_CLK>,
83 <&gcc GCC_CAMSS_CCI_CLK_SRC>;
84 clock-names = "cci_0_clk",
85 "cci_0_clk_src";
86 src-clock-name = "cci_0_clk_src";
87 clock-cntl-level = "svs";
88 clock-rates = <0 37500000>;
89 pinctrl-names = "cam_default", "cam_suspend";
90 pinctrl-0 = <&cci0_active &cci1_active>;
91 pinctrl-1 = <&cci0_suspend &cci1_suspend>;
92 gpios = <&tlmm 22 0>,
93 <&tlmm 23 0>,
94 <&tlmm 29 0>,
95 <&tlmm 30 0>;
96 gpio-req-tbl-num = <0 1 2 3>;
97 gpio-req-tbl-flags = <1 1 1 1>;
98 gpio-req-tbl-label = "CCI_I2C_DATA0",
99 "CCI_I2C_CLK0",
100 "CCI_I2C_DATA1",
101 "CCI_I2C_CLK1";
102
103 i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
104 hw-thigh = <201>;
105 hw-tlow = <174>;
106 hw-tsu-sto = <204>;
107 hw-tsu-sta = <231>;
108 hw-thd-dat = <22>;
109 hw-thd-sta = <162>;
110 hw-tbuf = <227>;
111 hw-scl-stretch-en = <0>;
112 hw-trdhld = <6>;
113 hw-tsp = <3>;
114 cci-clk-src = <37500000>;
115 status = "ok";
116 };
117
118 i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
119 hw-thigh = <38>;
120 hw-tlow = <56>;
121 hw-tsu-sto = <40>;
122 hw-tsu-sta = <40>;
123 hw-thd-dat = <22>;
124 hw-thd-sta = <35>;
125 hw-tbuf = <62>;
126 hw-scl-stretch-en = <0>;
127 hw-trdhld = <6>;
128 hw-tsp = <3>;
129 cci-clk-src = <37500000>;
130 status = "ok";
131 };
132
133 i2c_freq_custom_cci0: qcom,i2c_custom_mode {
134 hw-thigh = <38>;
135 hw-tlow = <56>;
136 hw-tsu-sto = <40>;
137 hw-tsu-sta = <40>;
138 hw-thd-dat = <22>;
139 hw-thd-sta = <35>;
140 hw-tbuf = <62>;
141 hw-scl-stretch-en = <1>;
142 hw-trdhld = <6>;
143 hw-tsp = <3>;
144 cci-clk-src = <37500000>;
145 status = "ok";
146 };
147
148 i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
149 hw-thigh = <16>;
150 hw-tlow = <22>;
151 hw-tsu-sto = <17>;
152 hw-tsu-sta = <18>;
153 hw-thd-dat = <16>;
154 hw-thd-sta = <15>;
155 hw-tbuf = <24>;
156 hw-scl-stretch-en = <0>;
157 hw-trdhld = <3>;
158 hw-tsp = <3>;
159 cci-clk-src = <37500000>;
160 status = "ok";
161 };
162 };
163
164 qcom,cam_smmu {
165 compatible = "qcom,msm-cam-smmu";
166 status = "ok";
167
168 msm_cam_smmu_tfe {
169 compatible = "qcom,msm-cam-smmu-cb";
170 iommus = <&apps_smmu 0x400 0x000>;
171 qcom,iommu-faults = "non-fatal";
172 qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
173 label = "tfe";
174 tfe_iova_mem_map: iova-mem-map {
175 /* IO region is approximately 3.4 GB */
176 iova-mem-region-io {
177 iova-region-name = "io";
178 iova-region-start = <0x7400000>;
179 iova-region-len = <0xd8c00000>;
180 iova-region-id = <0x3>;
181 status = "ok";
182 };
183 };
184 };
185
186 msm_cam_smmu_ope {
187 compatible = "qcom,msm-cam-smmu-cb";
188 iommus = <&apps_smmu 0x820 0x000>,
189 <&apps_smmu 0x840 0x000>;
190 qcom,iommu-faults = "non-fatal";
191 multiple-client-devices;
192 qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
193 label = "ope", "ope-cdm0";
194 ope_iova_mem_map: iova-mem-map {
195 /* IO region is approximately 3.4 GB */
196 iova-mem-region-io {
197 iova-region-name = "io";
198 iova-region-start = <0x7400000>;
199 iova-region-len = <0xd8c00000>;
200 iova-region-id = <0x3>;
201 status = "ok";
202 };
203 };
204 };
205
206 msm_cam_smmu_cpas_cdm {
207 compatible = "qcom,msm-cam-smmu-cb";
208 iommus = <&apps_smmu 0x800 0x000>;
209 label = "cpas-cdm0";
210 qcom,iommu-faults = "non-fatal";
211 qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
212 cpas_cdm_iova_mem_map: iova-mem-map {
213 iova-mem-region-io {
214 /* IO region is approximately 3.4 GB */
215 iova-region-name = "io";
216 iova-region-start = <0x7400000>;
217 iova-region-len = <0xd8c00000>;
218 iova-region-id = <0x3>;
219 status = "ok";
220 };
221 };
222 };
223
224 msm_cam_smmu_secure {
225 compatible = "qcom,msm-cam-smmu-cb";
226 label = "cam-secure";
227 qcom,secure-cb;
228 };
229
230 };
231
232 qcom,cam-cpas@5c11000 {
233 cell-index = <0>;
234 compatible = "qcom,cam-cpas";
235 label = "cpas";
236 arch-compat = "cpas_top";
237 status = "ok";
238 reg-names = "cam_cpas_top", "cam_camnoc";
239 reg = <0x5c11000 0x1000>,
240 <0x5c13000 0x4000>;
241 reg-cam-base = <0x11000 0x13000>;
242 cam_hw_fuse = <CAM_CPAS_SECURE_CAMERA_ENABLE 0x01B401E4 8>;
243 interrupt-names = "cpas_camnoc";
244 interrupts = <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>;
245 camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/
246 regulator-names = "camss-vdd";
247 camss-vdd-supply = <&gcc_camss_top_gdsc>;
248 clock-names =
249 "gcc_camss_ahb_clk",
250 "gcc_camss_top_ahb_clk",
251 "gcc_camss_top_ahb_clk_src",
252 "gcc_camss_axi_clk",
253 "gcc_camss_axi_clk_src",
254 "gcc_camss_nrt_axi_clk",
255 "gcc_camss_rt_axi_clk";
256 clocks =
257 <&gcc GCC_CAMERA_AHB_CLK>,
258 <&gcc GCC_CAMSS_TOP_AHB_CLK>,
259 <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>,
260 <&gcc GCC_CAMSS_AXI_CLK>,
261 <&gcc GCC_CAMSS_AXI_CLK_SRC>,
262 <&gcc GCC_CAMSS_NRT_AXI_CLK>,
263 <&gcc GCC_CAMSS_RT_AXI_CLK>;
264 src-clock-name = "gcc_camss_axi_clk_src";
265 clock-rates =
266 <0 0 0 0 0 0 0>,
267 <0 0 80000000 0 19200000 0 0>,
268 <0 0 80000000 0 150000000 0 0>,
269 <0 0 80000000 0 200000000 0 0>,
270 <0 0 80000000 0 300000000 0 0>,
271 <0 0 80000000 0 300000000 0 0>,
272 <0 0 80000000 0 300000000 0 0>;
273 clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs",
274 "svs_l1", "nominal", "turbo";
275 control-camnoc-axi-clk;
276 camnoc-bus-width = <32>;
277 camnoc-axi-clk-bw-margin-perc = <20>;
278 qcom,msm-bus,name = "cam_ahb";
279 qcom,msm-bus,num-cases = <7>;
280 qcom,msm-bus,num-paths = <1>;
281 qcom,msm-bus,vectors-KBps =
282 <MSM_BUS_MASTER_AMPSS_M0
283 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
284 <MSM_BUS_MASTER_AMPSS_M0
285 MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,
286 <MSM_BUS_MASTER_AMPSS_M0
287 MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,
288 <MSM_BUS_MASTER_AMPSS_M0
289 MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
290 <MSM_BUS_MASTER_AMPSS_M0
291 MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
292 <MSM_BUS_MASTER_AMPSS_M0
293 MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
294 <MSM_BUS_MASTER_AMPSS_M0
295 MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
296 vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
297 RPMH_REGULATOR_LEVEL_MIN_SVS
298 RPMH_REGULATOR_LEVEL_LOW_SVS
299 RPMH_REGULATOR_LEVEL_SVS
300 RPMH_REGULATOR_LEVEL_SVS_L1
301 RPMH_REGULATOR_LEVEL_NOM
302 RPMH_REGULATOR_LEVEL_NOM_L1
303 RPMH_REGULATOR_LEVEL_NOM_L2
304 RPMH_REGULATOR_LEVEL_TURBO
305 RPMH_REGULATOR_LEVEL_TURBO_L1>;
306 vdd-corner-ahb-mapping = "suspend", "minsvs",
307 "lowsvs", "svs", "svs_l1",
308 "nominal", "nominal", "nominal",
309 "turbo", "turbo";
310 client-id-based;
311 client-names =
312 "csiphy0", "csiphy1", "cci0",
313 "csid0", "csid1", "tfe0",
314 "tfe1", "ope0", "cam-cdm-intf0",
315 "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1";
316
317 camera-bus-nodes {
318 level2-nodes {
319 level-index = <2>;
320 level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum {
321 cell-index = <0>;
322 node-name = "level2-rt0-rd-wr-sum";
323 traffic-merge-type =
324 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
325 qcom,axi-port-name = "cam_hf_0";
326 ib-bw-voting-needed;
327 qcom,axi-port-mnoc {
328 qcom,msm-bus,name =
329 "cam_hf_0_mnoc";
330 qcom,msm-bus-vector-dyn-vote;
331 qcom,msm-bus,num-cases = <2>;
332 qcom,msm-bus,num-paths = <1>;
333 qcom,msm-bus,vectors-KBps =
334 <MSM_BUS_MASTER_CAMNOC_HF
335 MSM_BUS_SLAVE_EBI_CH0 0 0>,
336 <MSM_BUS_MASTER_CAMNOC_HF
337 MSM_BUS_SLAVE_EBI_CH0 0 0>;
338 };
339 };
340
341 level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum {
342 cell-index = <1>;
343 node-name = "level2-nrt0-rd-wr-sum";
344 traffic-merge-type =
345 <CAM_CPAS_TRAFFIC_MERGE_SUM>;
346 qcom,axi-port-name = "cam_sf_0";
347 qcom,axi-port-mnoc {
348 qcom,msm-bus,name =
349 "cam_sf_0_mnoc";
350 qcom,msm-bus-vector-dyn-vote;
351 qcom,msm-bus,num-cases = <2>;
352 qcom,msm-bus,num-paths = <1>;
353 qcom,msm-bus,vectors-KBps =
354 <MSM_BUS_MASTER_CAMNOC_SF
355 MSM_BUS_SLAVE_EBI_CH0 0 0>,
356 <MSM_BUS_MASTER_CAMNOC_SF
357 MSM_BUS_SLAVE_EBI_CH0 0 0>;
358 };
359 };
360 };
361
362 level1-nodes {
363 level-index = <1>;
364 camnoc-max-needed;
365 level1_rt0_wr: level1-rt0-wr {
366 cell-index = <2>;
367 node-name = "level1-rt0-wr";
368 parent-node = <&level2_rt0_rd_wr_sum>;
369 traffic-merge-type =
370 <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
371 };
372
373 level1_nrt0_rd_wr: level1-nrt0-rd-wr {
374 cell-index = <3>;
375 node-name = "level1-nrt0-rd-wr";
376 parent-node = <&level2_nrt0_rd_wr_sum>;
377 traffic-merge-type =
378 <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
379 };
380 };
381
382 level0-nodes {
383 level-index = <0>;
384 ope0_all_wr: ope0-all-wr {
385 cell-index = <4>;
386 node-name = "ope0-all-wr";
387 client-name = "ope0";
388 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
389 traffic-transaction-type =
390 <CAM_CPAS_TRANSACTION_WRITE>;
391 constituent-paths =
392 <CAM_CPAS_PATH_DATA_OPE_WR_VID
393 CAM_CPAS_PATH_DATA_OPE_WR_DISP
394 CAM_CPAS_PATH_DATA_OPE_WR_REF>;
395 parent-node = <&level1_nrt0_rd_wr>;
396 };
397
398 ope0_all_rd: ope0-all-rd {
399 cell-index = <5>;
400 node-name = "ope0-all-rd";
401 client-name = "ope0";
402 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
403 traffic-transaction-type =
404 <CAM_CPAS_TRANSACTION_READ>;
405 constituent-paths =
406 <CAM_CPAS_PATH_DATA_OPE_RD_IN
407 CAM_CPAS_PATH_DATA_OPE_RD_REF>;
408 parent-node = <&level1_nrt0_rd_wr>;
409 };
410
411 tfe0_all_wr: tfe0-all-wr {
412 cell-index = <6>;
413 node-name = "tfe0-all-wr";
414 client-name = "tfe0";
415 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
416 traffic-transaction-type =
417 <CAM_CPAS_TRANSACTION_WRITE>;
418 constituent-paths =
419 <CAM_CPAS_PATH_DATA_IFE_RDI0
420 CAM_CPAS_PATH_DATA_IFE_RDI1
421 CAM_CPAS_PATH_DATA_IFE_RDI2
422 CAM_CPAS_PATH_DATA_IFE_RDI3
423 CAM_CPAS_PATH_DATA_IFE_VID
424 CAM_CPAS_PATH_DATA_IFE_DISP
425 CAM_CPAS_PATH_DATA_IFE_STATS>;
426 parent-node = <&level1_rt0_wr>;
427 };
428
429 tfe1_all_wr: tfe1-all-wr {
430 cell-index = <7>;
431 node-name = "tfe1-all-wr";
432 client-name = "tfe1";
433 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
434 traffic-transaction-type =
435 <CAM_CPAS_TRANSACTION_WRITE>;
436 constituent-paths =
437 <CAM_CPAS_PATH_DATA_IFE_RDI0
438 CAM_CPAS_PATH_DATA_IFE_RDI1
439 CAM_CPAS_PATH_DATA_IFE_RDI2
440 CAM_CPAS_PATH_DATA_IFE_RDI3
441 CAM_CPAS_PATH_DATA_IFE_VID
442 CAM_CPAS_PATH_DATA_IFE_DISP
443 CAM_CPAS_PATH_DATA_IFE_STATS>;
444 parent-node = <&level1_rt0_wr>;
445 };
446
447 cpas_cdm0_all_rd: cpas-cdm0-all-rd {
448 cell-index = <9>;
449 node-name = "cpas-cdm0-all-rd";
450 client-name = "cpas-cdm0";
451 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
452 traffic-transaction-type =
453 <CAM_CPAS_TRANSACTION_READ>;
454 parent-node = <&level1_nrt0_rd_wr>;
455 };
456
457 ope_cdm0_all_rd: ope-cdm0-all-rd {
458 cell-index = <10>;
459 node-name = "ope-cdm0-all-rd";
460 client-name = "ope-cdm0";
461 traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
462 traffic-transaction-type =
463 <CAM_CPAS_TRANSACTION_READ>;
464 parent-node = <&level1_nrt0_rd_wr>;
465 };
466 };
467 };
468 };
469
470 qcom,cam-cdm-intf {
471 compatible = "qcom,cam-cdm-intf";
472 cell-index = <0>;
473 label = "cam-cdm-intf";
474 num-hw-cdm = <2>;
475 cdm-client-names = "vfe";
476 status = "ok";
477 };
478
479 cam_cpas_cdm: qcom,cpas-cdm0@5c23000 {
480 cell-index = <0>;
481 compatible = "qcom,cam-cpas-cdm2_0";
482 label = "cpas-cdm";
483 reg = <0x5c23000 0x400>;
484 reg-names = "cpas-cdm0";
485 reg-cam-base = <0x23000>;
486 interrupts = <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>;
487 interrupt-names = "cpas-cdm0";
488 regulator-names = "camss";
489 camss-supply = <&gcc_camss_top_gdsc>;
490 clock-names = "cam_cc_cpas_top_ahb_clk";
491 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>;
492 clock-rates = <0>;
493 clock-cntl-level = "svs";
494 cdm-client-names = "tfe0", "tfe1";
495 config-fifo;
496 fifo-depths = <64 64 64 64>;
497 status = "ok";
498 };
499
500 cam_ope_cdm: qcom,ope-cdm0@5c42000 {
501 cell-index = <0>;
502 compatible = "qcom,cam-ope-cdm2_0";
503 label = "ope-cdm";
504 reg = <0x5c42000 0x400>;
505 reg-names = "ope-cdm0";
506 reg-cam-base = <0x42000>;
507 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>;
508 interrupt-names = "ope-cdm0";
509 regulator-names = "camss";
510 camss-supply = <&gcc_camss_top_gdsc>;
511 clock-names =
512 "ope_ahb_clk",
513 "ope_clk_src",
514 "ope_clk";
515 clocks =
516 <&gcc GCC_CAMSS_OPE_AHB_CLK>,
517 <&gcc GCC_CAMSS_OPE_CLK_SRC>,
518 <&gcc GCC_CAMSS_OPE_CLK>;
519 clock-rates = <0 0 0>,
520 <0 0 0>,
521 <0 0 0>,
522 <0 0 0>;
523 clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
524 cdm-client-names = "ope";
525 config-fifo;
526 fifo-depths = <64 64 64 64>;
527 status = "ok";
528 };
529
530 qcom,cam-isp {
531 compatible = "qcom,cam-isp";
532 arch-compat = "tfe";
533 status = "ok";
534 };
535
536 cam_tfe_csid0: qcom,tfe_csid0@5c6e000 {
537 cell-index = <0>;
538 compatible = "qcom,csid530";
539 reg-names = "csid", "top", "camnoc";
540 reg = <0x5c6e000 0x1000>,
541 <0x5c11000 0x1000>,
542 <0x5c13000 0x4000>;
543 reg-cam-base = <0x6e000 0x11000 0x13000>;
544 interrupt-names = "csid0";
545 interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
546 regulator-names = "camss";
547 camss-supply = <&gcc_camss_top_gdsc>;
548 clock-names =
549 "tfe_csid_clk_src",
550 "tfe_csid_clk",
551 "cphy_rx_clk_src",
552 "tfe_cphy_rx_clk",
553 "tfe_clk_src",
554 "tfe_clk";
555 clocks =
556 <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>,
557 <&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
558 <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
559 <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
560 <&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
561 <&gcc GCC_CAMSS_TFE_0_CLK>;
562 clock-rates =
563 <240000000 0 240000000 0 256000000 0>,
564 <384000000 0 341333333 0 460800000 0>,
565 <426400000 0 384000000 0 576000000 0>;
566 clock-cntl-level = "svs", "svs_l1", "turbo";
567 src-clock-name = "tfe_csid_clk_src";
568 clock-control-debugfs = "true";
569 status = "ok";
570 };
571
572 cam_tfe0: qcom,tfe0@5c6e000 {
573 cell-index = <0>;
574 compatible = "qcom,tfe530";
575 reg-names = "tfe0";
576 reg = <0x5c6e000 0x5000>;
577 reg-cam-base = <0x6e000>;
578 interrupt-names = "tfe0";
579 interrupts = <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>;
580 regulator-names = "camss";
581 camss-supply = <&gcc_camss_top_gdsc>;
582 clock-names =
583 "tfe_clk_src",
584 "tfe_clk";
585 clocks =
586 <&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
587 <&gcc GCC_CAMSS_TFE_0_CLK>;
588 clock-rates =
589 <256000000 0>,
590 <460800000 0>,
591 <576000000 0>;
592 clock-cntl-level = "svs", "svs_l1", "turbo";
593 src-clock-name = "tfe_clk_src";
594 clock-control-debugfs = "true";
595 status = "ok";
596 };
597
598 cam_tfe_csid1: qcom,tfe_csid1@5c75000 {
599 cell-index = <1>;
600 compatible = "qcom,csid530";
601 reg-names = "csid", "top", "camnoc";
602 reg = <0x5c75000 0x1000>,
603 <0x5c11000 0x1000>,
604 <0x5c13000 0x4000>;
605 reg-cam-base = <0x75000 0x11000 0x13000>;
606 interrupt-names = "csid1";
607 interrupts = <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
608 regulator-names = "camss";
609 camss-supply = <&gcc_camss_top_gdsc>;
610 clock-names =
611 "tfe_csid_clk_src",
612 "tfe_csid_clk",
613 "cphy_rx_clk_src",
614 "tfe_cphy_rx_clk",
615 "tfe_clk_src",
616 "tfe_clk";
617 clocks =
618 <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>,
619 <&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
620 <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
621 <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
622 <&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
623 <&gcc GCC_CAMSS_TFE_1_CLK>;
624 clock-rates =
625 <240000000 0 240000000 0 256000000 0>,
626 <384000000 0 341333333 0 460800000 0>,
627 <426400000 0 384000000 0 576000000 0>;
628 clock-cntl-level = "svs", "svs_l1", "turbo";
629 src-clock-name = "tfe_csid_clk_src";
630 clock-control-debugfs = "true";
631 status = "ok";
632 };
633
634 cam_tfe1: qcom,tfe1@5c75000 {
635 cell-index = <1>;
636 compatible = "qcom,tfe530";
637 reg-names = "tfe1";
638 reg = <0x5c75000 0x5000>;
639 reg-cam-base = <0x75000>;
640 interrupt-names = "tfe1";
641 interrupts = <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
642 regulator-names = "camss";
643 camss-supply = <&gcc_camss_top_gdsc>;
644 clock-names =
645 "tfe_clk_src",
646 "tfe_clk";
647 clocks =
648 <&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
649 <&gcc GCC_CAMSS_TFE_1_CLK>;
650 clock-rates =
651 <256000000 0>,
652 <460800000 0>,
653 <576000000 0>;
654 clock-cntl-level = "svs", "svs_l1", "turbo";
655 src-clock-name = "tfe_clk_src";
656 clock-control-debugfs = "true";
657 status = "ok";
658 };
659
660 cam_tfe_tpg0: qcom,tpg0@5c66000 {
661 cell-index = <0>;
662 compatible = "qcom,tpgv1";
663 reg-names = "tpg0", "top";
664 reg = <0x5c66000 0x400>,
665 <0x5c11000 0x1000>;
666 reg-cam-base = <0x66000 0x11000>;
667 regulator-names = "camss";
668 camss-supply = <&gcc_camss_top_gdsc>;
669 clock-names =
670 "cphy_rx_clk_src",
671 "tfe_0_cphy_rx_clk",
672 "gcc_camss_cphy_0_clk";
673 clocks =
674 <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
675 <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
676 <&gcc GCC_CAMSS_CPHY_0_CLK>;
677 clock-rates =
678 <240000000 0 0>,
679 <341333333 0 0>,
680 <384000000 0 0>;
681 clock-cntl-level = "svs", "svs_l1", "turbo";
682 src-clock-name = "cphy_rx_clk_src";
683 clock-control-debugfs = "false";
684 status = "ok";
685 };
686
687 cam_tfe_tpg1: qcom,tpg0@5c68000 {
688 cell-index = <1>;
689 compatible = "qcom,tpgv1";
690 reg-names = "tpg0", "top";
691 reg = <0x5c68000 0x400>,
692 <0x5c11000 0x1000>;
693 reg-cam-base = <0x68000 0x11000>;
694 regulator-names = "camss";
695 camss-supply = <&gcc_camss_top_gdsc>;
696 clock-names =
697 "cphy_rx_clk_src",
698 "tfe_1_cphy_rx_clk",
699 "gcc_camss_cphy_1_clk";
700 clocks =
701 <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
702 <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
703 <&gcc GCC_CAMSS_CPHY_1_CLK>;
704 clock-rates =
705 <240000000 0 0>,
706 <341333333 0 0>,
707 <384000000 0 0>;
708 clock-cntl-level = "svs", "svs_l1", "turbo";
709 src-clock-name = "cphy_rx_clk_src";
710 clock-control-debugfs = "false";
711 status = "ok";
712 };
713
714 qcom,cam-ope {
715 compatible = "qcom,cam-ope";
716 compat-hw-name = "qcom,ope";
717 num-ope = <1>;
718 status = "ok";
719 };
720
721 ope: qcom,ope@0x5c42000 {
722 cell-index = <0>;
723 compatible = "qcom,ope";
724 reg =
725 <0x5c42000 0x400>,
726 <0x5c42400 0x200>,
727 <0x5c42600 0x200>,
728 <0x5c42800 0x4400>,
729 <0x5c46c00 0x190>,
730 <0x5c46d90 0xA00>;
731 reg-names =
732 "ope_cdm",
733 "ope_top",
734 "ope_qos",
735 "ope_pp",
736 "ope_bus_rd",
737 "ope_bus_wr";
738 reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>;
739 interrupts = <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>;
740 interrupt-names = "ope";
741 regulator-names = "camss";
742 camss-supply = <&gcc_camss_top_gdsc>;
743 clock-names =
744 "ope_ahb_clk_src",
745 "ope_ahb_clk",
746 "ope_clk_src",
747 "ope_clk";
748 clocks =
749 <&gcc GCC_CAMSS_OPE_AHB_CLK_SRC>,
750 <&gcc GCC_CAMSS_OPE_AHB_CLK>,
751 <&gcc GCC_CAMSS_OPE_CLK_SRC>,
752 <&gcc GCC_CAMSS_OPE_CLK>;
753 clock-rates =
754 <171428571 0 200000000 0>,
755 <171428571 0 266600000 0>,
756 <240000000 0 465000000 0>,
757 <240000000 0 580000000 0>;
758 clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";
759 src-clock-name = "ope_clk_src";
760 status = "ok";
761 };
762};