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gerrit-public.fairphone.software / kernel / msm-4.19 / 9b0224459fa8ee7c60d16a0b710ebf039da9f365 / . / arch / arm64 / boot / dts / vendor / qcom / khaje-usb.dtsi
blob: 849cdf38bfabe713cf97c72677945c6a542bbe9e [file] [log] [blame]
Luca Weiss9b022442023-04-14 14:47:36 +0200[diff] [blame^]1#include <dt-bindings/clock/qcom,gcc-khaje.h>
2#include <dt-bindings/msm/msm-bus-ids.h>
3#include <dt-bindings/phy/qcom,khaje-qmp-usb3.h>
4&soc {
5 /* Primary USB port related controller */
6 usb0: ssusb@4e00000 {
7 compatible = "qcom,dwc-usb3-msm";
8 reg = <0x4e00000 0x100000>;
9 reg-names = "core_base";
10
11 iommus = <&apps_smmu 0x120 0x0>;
12 qcom,iommu-dma = "atomic";
13 qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>;
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges;
17
18 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
19 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
20 <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
21 <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>;
22 interrupt-names = "pwr_event_irq", "ss_phy_irq",
23 "dp_hs_phy_irq", "dm_hs_phy_irq";
24
25 clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
26 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
27 <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
28 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
29 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
30 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
31 clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
32 "xo", "sleep_clk", "utmi_clk";
33
34 resets = <&gcc GCC_USB30_PRIM_BCR>;
35 reset-names = "core_reset";
36
37 USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
38 dpdm-supply = <&usb2_phy0>;
39
40 qcom,core-clk-rate = <133333333>;
41 qcom,core-clk-rate-hs = <66666667>;
42 qcom,num-gsi-evt-buffs = <0x3>;
43 qcom,gsi-reg-offset =
44 <0x0fc /* GSI_GENERAL_CFG */
45 0x110 /* GSI_DBL_ADDR_L */
46 0x120 /* GSI_DBL_ADDR_H */
47 0x130 /* GSI_RING_BASE_ADDR_L */
48 0x144 /* GSI_RING_BASE_ADDR_H */
49 0x1a4>; /* GSI_IF_STS */
50 qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
51 qcom,gsi-disable-io-coherency;
52
53 qcom,msm-bus,name = "usb0";
54 qcom,msm-bus,num-cases = <4>;
55 qcom,msm-bus,num-paths = <3>;
56 qcom,msm-bus,vectors-KBps =
57 /* suspend vote */
58 <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>,
59 <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>,
60 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>,
61
62 /* nominal vote */
63 <MSM_BUS_MASTER_USB3
64 MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
65 <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
66 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
67
68 /* svs vote */
69 <MSM_BUS_MASTER_USB3
70 MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
71 <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
72 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
73
74 /* min vote */
75 <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 1 1>,
76 <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>,
77 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>;
78
79 dwc3@4e00000 {
80 compatible = "snps,dwc3";
81 reg = <0x4e00000 0xe000>;
82 interrupt-parent = <&intc>;
83 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
84 usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;
85 tx-fifo-resize;
86 linux,sysdev_is_parent;
87 snps,disable-clk-gating;
88 snps,has-lpm-erratum;
89 snps,hird-threshold = /bits/ 8 <0x10>;
90 snps,usb3-u1u2-disable;
91 snps,usb3_lpm_capable;
92 usb-core-id = <0>;
93 maximum-speed = "super-speed";
94 dr_mode = "otg";
95 };
96
97 qcom,usbbam@0x04f04000 {
98 compatible = "qcom,usb-bam-msm";
99 reg = <0x04f04000 0x17000>;
100 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
101
102 qcom,usb-bam-fifo-baseaddr = <0xc121000>;
103 qcom,usb-bam-num-pipes = <4>;
104 qcom,disable-clk-gating;
105 qcom,usb-bam-override-threshold = <0x4001>;
106 qcom,usb-bam-max-mbps-highspeed = <400>;
107 qcom,usb-bam-max-mbps-superspeed = <3600>;
108 qcom,reset-bam-on-connect;
109
110 qcom,pipe0 {
111 label = "ssusb-qdss-in-0";
112 qcom,usb-bam-mem-type = <2>;
113 qcom,dir = <1>;
114 qcom,pipe-num = <0>;
115 qcom,peer-bam = <0>;
116 qcom,peer-bam-physical-address = <0x08064000>;
117 qcom,src-bam-pipe-index = <0>;
118 qcom,dst-bam-pipe-index = <0>;
119 qcom,data-fifo-offset = <0x0>;
120 qcom,data-fifo-size = <0x1800>;
121 qcom,descriptor-fifo-offset = <0x1800>;
122 qcom,descriptor-fifo-size = <0x800>;
123 };
124 };
125 };
126
127 /* Primary USB port related High Speed PHY */
128 usb2_phy0: hsphy@1613000 {
129 compatible = "qcom,usb-hsphy-snps-femto";
130 reg = <0x1613000 0x110>,
131 <0x1612000 0x4>;
132 reg-names = "hsusb_phy_base",
133 "eud_enable_reg";
134
135 vdd-supply = <&L4A>;
136 vdda18-supply = <&L12A>;
137 vdda33-supply = <&L15A>;
138 qcom,vdd-voltage-level = <0 880000 880000>;
139
140 clocks = <&rpmcc CXO_SMD_OTG_CLK>,
141 <&gcc GCC_AHB2PHY_USB_CLK>;
142 clock-names = "ref_clk_src", "cfg_ahb_clk";
143
144 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
145 reset-names = "phy_reset";
146 qcom,param-override-seq =
147 <0xa6 0x6c>, /* override_x0 */
148 <0x85 0x70>, /* override_x1 */
149 <0x16 0x74>; /* override_x2 */
150 };
151
152 /* Primary USB port related QMP USB PHY */
153 usb_qmp_dp_phy: ssphy@1615000 {
154 compatible = "qcom,usb-ssphy-qmp-dp-combo";
155 reg = <0x01615000 0x3000>;
156 reg-names = "qmp_phy_base";
157
158 core-supply = <&L18A>;
159 qcom,vdd-voltage-level = <0 880000 880000>;
160 qcom,core-voltage-level = <0 1232000 1260000>;
161
162 clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
163 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
164 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
165 <&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
166 <&rpmcc CXO_SMD_OTG_CLK>,
167 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
168 <&gcc GCC_AHB2PHY_USB_CLK>;
169
170 clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
171 "pipe_clk_ext_src", "ref_clk_src",
172 "com_aux_clk","cfg_ahb_clk";
173
174 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
175 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
176 reset-names = "global_phy_reset", "phy_reset";
177
178 qcom,qmp-phy-reg-offset =
179 <USB3_DP_PCS_PCS_STATUS1
180 USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
181 USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
182 USB3_DP_PCS_POWER_DOWN_CONTROL
183 USB3_DP_PCS_SW_RESET
184 USB3_DP_PCS_START_CONTROL
185 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
186 0x2a18 /* USB3_DP_DP_PHY_PD_CTL */
187 USB3_DP_COM_POWER_DOWN_CTRL
188 USB3_DP_COM_SW_RESET
189 USB3_DP_COM_RESET_OVRD_CTRL
190 USB3_DP_COM_PHY_MODE_CTRL
191 USB3_DP_COM_TYPEC_CTRL
192 USB3_DP_COM_SWI_CTRL
193 USB3_DP_PCS_CLAMP_ENABLE>;
194
195 qcom,qmp-phy-init-seq =
196 /* <reg_offset, value, delay> */
197 <USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
198 USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
199 USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
200 USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
201 USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
202 USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
203 USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
204 USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
205 USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
206 USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
207 USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
208 USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
209 USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
210 USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
211 USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
212 USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
213 USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
214 USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
215 USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
216 USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
217 USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
218 USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
219 USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
220 USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
221 USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
222 USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
223 USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
224 USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
225 USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
226 USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
227 USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
228 USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
229 USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
230 USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
231 USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
232 USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
233 USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
234 USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
235 USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
236 USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
237 USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x60 0
238 USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x60 0
239 USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11 0
240 USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02 0
241 USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5 0
242 USB3_DP_QSERDES_TXA_LANE_MODE_2 0x00 0
243 USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
244 USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40 0
245 USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09 0
246 USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0
247 USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
248 USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
249 USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
250 USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
251 USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
252 USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
253 USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
254 USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
255 USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
256 USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
257 USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C 0
258 USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
259 USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
260 USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
261 USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
262 USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
263 USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
264 USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
265 USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
266 USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF 0
267 USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F 0
268 USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F 0
269 USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0
270 USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97 0
271 USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0
272 USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0
273 USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0
274 USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B 0
275 USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4 0
276 USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
277 USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
278 USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
279 USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
280 USB3_DP_QSERDES_RXA_GM_CAL 0x1F 0
281 USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
282 USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x60 0
283 USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x60 0
284 USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11 0
285 USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02 0
286 USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5 0
287 USB3_DP_QSERDES_TXB_LANE_MODE_2 0x00 0
288 USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
289 USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54 0
290 USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09 0
291 USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0
292 USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
293 USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
294 USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
295 USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
296 USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
297 USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
298 USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
299 USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
300 USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
301 USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
302 USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C 0
303 USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
304 USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
305 USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
306 USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
307 USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
308 USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
309 USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
310 USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
311 USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F 0
312 USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF 0
313 USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0
314 USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0
315 USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xA6 0
316 USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0
317 USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0
318 USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0
319 USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B 0
320 USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4 0
321 USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
322 USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
323 USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
324 USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
325 USB3_DP_QSERDES_RXB_GM_CAL 0x1F 0
326 USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
327 USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0
328 USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0
329 USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
330 USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
331 USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
332 USB3_DP_PCS_RX_SIGDET_LVL 0xA9 0
333 USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
334 USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
335 USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
336 USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
337 USB3_DP_PCS_EQ_CONFIG1 0x4B 0
338 USB3_DP_PCS_EQ_CONFIG5 0x10 0
339 USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
340 USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
341 0xffffffff 0xffffffff 0x00>;
342 };
343
344 usb_nop_phy: usb_nop_phy {
345 compatible = "usb-nop-xceiv";
346 };
347
348 usb_audio_qmi_dev {
349 compatible = "qcom,usb-audio-qmi-dev";
350 iommus = <&apps_smmu 0x1cf 0x0>;
351 qcom,iommu-dma = "disabled";
352 qcom,usb-audio-stream-id = <0xf>;
353 qcom,usb-audio-intr-num = <2>;
354 };
355};