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gerrit-public.fairphone.software / kernel / msm-4.19 / 9b0224459fa8ee7c60d16a0b710ebf039da9f365 / . / arch / arm64 / boot / dts / vendor / qcom / khaje.dtsi
blob: 0d5c32bcd256d0f075e6e246152fe8cf12a8a366 [file] [log] [blame]
Luca Weiss9b022442023-04-14 14:47:36 +0200[diff] [blame^]1#include <dt-bindings/interrupt-controller/arm-gic.h>
2#include <dt-bindings/clock/qcom,rpmcc.h>
3#include <dt-bindings/clock/qcom,dispcc-khaje.h>
4#include <dt-bindings/clock/qcom,gcc-khaje.h>
5#include <dt-bindings/clock/qcom,gpucc-khaje.h>
6#include <dt-bindings/spmi/spmi.h>
7#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
8#include <dt-bindings/msm/msm-bus-ids.h>
9#include <dt-bindings/soc/qcom,dcc_v2.h>
10
11#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
12#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
13
14#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
15 opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
16 opp-supported-hw = <ddrtype>;}
17
18#define DDR_TYPE_LPDDR3 5
19#define DDR_TYPE_LPDDR4X 7
20
21/ {
22 model = "Qualcomm Technologies, Inc. Khaje SoC";
23 compatible = "qcom,khaje";
24 qcom,msm-id = <518 0x10000>;
25 interrupt-parent = <&wakegic>;
26
27 #address-cells = <2>;
28 #size-cells = <2>;
29 memory { device_type = "memory"; reg = <0 0 0 0>; };
30
31 mem-offline {
32 compatible = "qcom,mem-offline";
33 offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
34 <0x1 0xc0000000 0x0 0x80000000>,
35 <0x2 0xc0000000 0x1 0x40000000>;
36 granule = <512>;
37 };
38
39 aliases {
40 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
41 sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
42 swr0 = &swr0;
43 swr1 = &swr1;
44 ufshc1 = &ufshc_mem; /* Embedded UFS slot */
45 };
46
47 cpus {
48 #address-cells = <2>;
49 #size-cells = <0>;
50
51 CPU0: cpu@0 {
52 device_type = "cpu";
53 compatible = "arm,armv8";
54 reg = <0x0 0x0>;
55 capacity-dmips-mhz = <1024>;
56 dynamic-power-coefficient = <100>;
57 enable-method = "psci";
58 next-level-cache = <&L2_0>;
59 qcom,freq-domain = <&cpufreq_hw 0 7>;
60 qcom,lmh-dcvs = <&lmh_dcvs0>;
61 #cooling-cells = <2>;
62 L2_0: l2-cache {
63 compatible = "arm,arch-cache";
64 cache-level = <2>;
65 };
66
67 L1_I_0: l1-icache {
68 compatible = "arm,arch-cache";
69 };
70
71 L1_D_0: l1-dcache {
72 compatible = "arm,arch-cache";
73 };
74 };
75
76 CPU1: cpu@1 {
77 device_type = "cpu";
78 compatible = "arm,armv8";
79 reg = <0x0 0x1>;
80 capacity-dmips-mhz = <1024>;
81 dynamic-power-coefficient = <100>;
82 enable-method = "psci";
83 next-level-cache = <&L2_0>;
84 qcom,freq-domain = <&cpufreq_hw 0 7>;
85 qcom,lmh-dcvs = <&lmh_dcvs0>;
86
87 L1_I_1: l1-icache {
88 compatible = "arm,arch-cache";
89 };
90
91 L1_D_1: l1-dcache {
92 compatible = "arm,arch-cache";
93 };
94 };
95
96 CPU2: cpu@2 {
97 device_type = "cpu";
98 compatible = "arm,armv8";
99 reg = <0x0 0x2>;
100 capacity-dmips-mhz = <1024>;
101 dynamic-power-coefficient = <100>;
102 enable-method = "psci";
103 next-level-cache = <&L2_0>;
104 qcom,freq-domain = <&cpufreq_hw 0 7>;
105 qcom,lmh-dcvs = <&lmh_dcvs0>;
106
107 L1_I_2: l1-icache {
108 compatible = "arm,arch-cache";
109 };
110
111 L1_D_2: l1-dcache {
112 compatible = "arm,arch-cache";
113 };
114 };
115
116 CPU3: cpu@3 {
117 device_type = "cpu";
118 compatible = "arm,armv8";
119 reg = <0x0 0x3>;
120 capacity-dmips-mhz = <1024>;
121 dynamic-power-coefficient = <100>;
122 enable-method = "psci";
123 next-level-cache = <&L2_0>;
124 qcom,freq-domain = <&cpufreq_hw 0 7>;
125 qcom,lmh-dcvs = <&lmh_dcvs0>;
126
127 L1_I_3: l1-icache {
128 compatible = "arm,arch-cache";
129 };
130
131 L1_D_3: l1-dcache {
132 compatible = "arm,arch-cache";
133 };
134 };
135
136 CPU4: cpu@100 {
137 device_type = "cpu";
138 compatible = "arm,armv8";
139 reg = <0x0 0x100>;
140 enable-method = "psci";
141 capacity-dmips-mhz = <1638>;
142 dynamic-power-coefficient = <282>;
143 next-level-cache = <&L2_1>;
144 qcom,freq-domain = <&cpufreq_hw 1 7>;
145 qcom,lmh-dcvs = <&lmh_dcvs1>;
146 #cooling-cells = <2>;
147 L2_1: l2-cache {
148 compatible = "arm,arch-cache";
149 cache-level = <2>;
150 };
151
152 L1_I_100: l1-icache {
153 compatible = "arm,arch-cache";
154 };
155
156 L1_D_100: l1-dcache {
157 compatible = "arm,arch-cache";
158 };
159 };
160
161 CPU5: cpu@101 {
162 device_type = "cpu";
163 compatible = "arm,armv8";
164 reg = <0x0 0x101>;
165 capacity-dmips-mhz = <1638>;
166 dynamic-power-coefficient = <282>;
167 enable-method = "psci";
168 next-level-cache = <&L2_1>;
169 qcom,freq-domain = <&cpufreq_hw 1 7>;
170 qcom,lmh-dcvs = <&lmh_dcvs1>;
171
172 L1_I_101: l1-icache {
173 compatible = "arm,arch-cache";
174 };
175
176 L1_D_101: l1-dcache {
177 compatible = "arm,arch-cache";
178 };
179 };
180
181 CPU6: cpu@102 {
182 device_type = "cpu";
183 compatible = "arm,armv8";
184 reg = <0x0 0x102>;
185 capacity-dmips-mhz = <1638>;
186 dynamic-power-coefficient = <282>;
187 enable-method = "psci";
188 next-level-cache = <&L2_1>;
189 qcom,freq-domain = <&cpufreq_hw 1 7>;
190 qcom,lmh-dcvs = <&lmh_dcvs1>;
191
192 L1_I_102: l1-icache {
193 compatible = "arm,arch-cache";
194 };
195
196 L1_D_102: l1-dcache {
197 compatible = "arm,arch-cache";
198 };
199 };
200
201 CPU7: cpu@103 {
202 device_type = "cpu";
203 compatible = "arm,armv8";
204 reg = <0x0 0x103>;
205 capacity-dmips-mhz = <1638>;
206 dynamic-power-coefficient = <282>;
207 enable-method = "psci";
208 next-level-cache = <&L2_1>;
209 qcom,freq-domain = <&cpufreq_hw 1 7>;
210 qcom,lmh-dcvs = <&lmh_dcvs1>;
211
212 L1_I_103: l1-icache {
213 compatible = "arm,arch-cache";
214 };
215
216 L1_D_103: l1-dcache {
217 compatible = "arm,arch-cache";
218 };
219 };
220
221 cpu-map {
222 cluster0 {
223 core0 {
224 cpu = <&CPU0>;
225 };
226
227 core1 {
228 cpu = <&CPU1>;
229 };
230
231 core2 {
232 cpu = <&CPU2>;
233 };
234
235 core3 {
236 cpu = <&CPU3>;
237 };
238 };
239
240 cluster1 {
241 core0 {
242 cpu = <&CPU4>;
243 };
244
245 core1 {
246 cpu = <&CPU5>;
247 };
248
249 core2 {
250 cpu = <&CPU6>;
251 };
252
253 core3 {
254 cpu = <&CPU7>;
255 };
256 };
257 };
258 };
259
260 psci {
261 compatible = "arm,psci-1.0";
262 method = "smc";
263 };
264
265 firmware: firmware {
266 android {
267 compatible = "android,firmware";
268 vbmeta {
269 compatible="android,vbmeta";
270 parts = "vbmeta,boot,system,vendor,dtbo,recovery";
271 };
272
273 fstab {
274 compatible = "android,fstab";
275 vendor {
276 compatible = "android,vendor";
277 dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor";
278 type = "ext4";
279 mnt_flags = "ro,barrier=1,discard";
280 fsmgr_flags = "wait,slotselect,avb";
281 status = "ok";
282 };
283 };
284 };
285 };
286
287 reserved_memory: reserved-memory {
288 #address-cells = <2>;
289 #size-cells = <2>;
290 ranges;
291
292 hyp_mem: hyp_region@45700000 {
293 compatible = "removed-dma-pool";
294 no-map;
295 reg = <0x0 0x45700000 0x0 0x600000>;
296 };
297
298 xbl_aop_mem: xbl_aop_region@45e00000 {
299 compatible = "removed-dma-pool";
300 no-map;
301 reg = <0x0 0x45e00000 0x0 0x140000>;
302 };
303
304 sec_apps_mem: sec_apps_region@45fff000 {
305 compatible = "removed-dma-pool";
306 no-map;
307 reg = <0x0 0x45fff000 0x0 0x1000>;
308 };
309
310 smem_mem: smem_region@46000000 {
311 compatible = "removed-dma-pool";
312 no-map;
313 reg = <0x0 0x46000000 0x0 0x200000>;
314 };
315
316 removed_mem: removed_region@60000000 {
317 compatible = "removed-dma-pool";
318 no-map;
319 reg = <0x0 0x60000000 0x0 0x3900000>;
320 };
321
322 pil_modem_mem: modem_region@4ab00000 {
323 compatible = "removed-dma-pool";
324 no-map;
325 reg = <0x0 0x4ab00000 0x0 0x6900000>;
326 };
327
328 pil_video_mem: pil_video_region@51400000 {
329 compatible = "removed-dma-pool";
330 no-map;
331 reg = <0x0 0x51400000 0x0 0x500000>;
332 };
333
334 wlan_msa_mem: wlan_msa_region@51900000 {
335 compatible = "removed-dma-pool";
336 no-map;
337 reg = <0x0 0x51900000 0x0 0x100000>;
338 };
339
340 pil_cdsp_mem: cdsp_regions@51a00000 {
341 compatible = "removed-dma-pool";
342 no-map;
343 reg = <0x0 0x51a00000 0x0 0x1e00000>;
344 };
345
346 pil_adsp_mem: pil_adsp_region@53800000 {
347 compatible = "removed-dma-pool";
348 no-map;
349 reg = <0x0 0x53800000 0x0 0x1e00000>;
350 };
351
352 pil_ipa_fw_mem: ipa_fw_region@55600000 {
353 compatible = "removed-dma-pool";
354 no-map;
355 reg = <0x0 0x55600000 0x0 0x10000>;
356 };
357
358 pil_ipa_gsi_mem: ipa_gsi_region@55610000 {
359 compatible = "removed-dma-pool";
360 no-map;
361 reg = <0x0 0x55610000 0x0 0x5000>;
362 };
363
364 pil_gpu_mem: gpu_region@55615000 {
365 compatible = "removed-dma-pool";
366 no-map;
367 reg = <0x0 0x55615000 0x0 0x2000>;
368 };
369
370 user_contig_mem: user_contig_region {
371 compatible = "shared-dma-pool";
372 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
373 reusable;
374 alignment = <0x0 0x400000>;
375 size = <0x0 0x1000000>;
376 };
377
378 qseecom_mem: qseecom_region {
379 compatible = "shared-dma-pool";
380 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
381 reusable;
382 alignment = <0x0 0x400000>;
383 size = <0x0 0x1400000>;
384 };
385
386 qseecom_ta_mem: qseecom_ta_region {
387 compatible = "shared-dma-pool";
388 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
389 reusable;
390 alignment = <0x0 0x400000>;
391 size = <0x0 0x1000000>;
392 };
393
394 cdsp_sec_mem: cdsp_sec_regions@46200000 {
395 compatible = "removed-dma-pool";
396 no-map;
397 reg = <0x0 0x46200000 0x0 0x1e00000>;
398 };
399
400 secure_display_memory: secure_display_region {
401 compatible = "shared-dma-pool";
402 alloc-ranges = <0 0x00000000 0 0xffffffff>;
403 reusable;
404 alignment = <0 0x400000>;
405 size = <0 0x5c00000>;
406 };
407
408 cont_splash_memory: cont_splash_region@5c000000 {
409 reg = <0x0 0x5c000000 0x0 0x00f00000>;
410 label = "cont_splash_region";
411 };
412
413 disp_rdump_memory: disp_rdump_region@5c000000 {
414 reg = <0x0 0x5c000000 0x0 0x00f00000>;
415 label = "disp_rdump_region";
416 };
417
418 dfps_data_memory: dfps_data_region@5cf00000 {
419 reg = <0x0 0x5cf00000 0x0 0x0100000>;
420 label = "dfps_data_region";
421 };
422
423 adsp_mem: adsp_region {
424 compatible = "shared-dma-pool";
425 alloc-ranges = <0 0x00000000 0 0xffffffff>;
426 reusable;
427 alignment = <0 0x400000>;
428 size = <0 0x800000>;
429 };
430
431 dump_mem: mem_dump_region {
432 compatible = "shared-dma-pool";
433 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
434 reusable;
435 size = <0 0x800000>;
436 };
437
438 /* global autoconfigured region for contiguous allocations */
439 linux,cma {
440 compatible = "shared-dma-pool";
441 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
442 reusable;
443 alignment = <0x0 0x400000>;
444 size = <0x0 0x2000000>;
445 linux,cma-default;
446 };
447 };
448
449 chosen {
450 bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
451 };
452
453 soc: soc { };
454};
455
456#include "bengal-coresight.dtsi"
457
458&soc {
459 #address-cells = <1>;
460 #size-cells = <1>;
461 ranges = <0 0 0 0xffffffff>;
462 compatible = "simple-bus";
463
464 intc: interrupt-controller@f200000 {
465 compatible = "arm,gic-v3";
466 #interrupt-cells = <3>;
467 interrupt-controller;
468 interrupt-parent = <&intc>;
469 #redistributor-regions = <1>;
470 redistributor-stride = <0x0 0x20000>;
471 reg = <0xf200000 0x10000>, /* GICD */
472 <0xf300000 0x100000>; /* GICR * 8 */
473 interrupts = <1 9 4>;
474 };
475
476 jtag_mm0: jtagmm@9040000 {
477 compatible = "qcom,jtagv8-mm";
478 reg = <0x9040000 0x1000>;
479 reg-names = "etm-base";
480
481 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
482 clock-names = "core_clk";
483
484 qcom,coresight-jtagmm-cpu = <&CPU0>;
485 };
486
487 jtag_mm1: jtagmm@9140000 {
488 compatible = "qcom,jtagv8-mm";
489 reg = <0x9140000 0x1000>;
490 reg-names = "etm-base";
491
492 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
493 clock-names = "core_clk";
494
495 qcom,coresight-jtagmm-cpu = <&CPU1>;
496 };
497
498 jtag_mm2: jtagmm@9240000 {
499 compatible = "qcom,jtagv8-mm";
500 reg = <0x9240000 0x1000>;
501 reg-names = "etm-base";
502
503 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
504 clock-names = "core_clk";
505
506 qcom,coresight-jtagmm-cpu = <&CPU2>;
507 };
508
509 jtag_mm3: jtagmm@9340000 {
510 compatible = "qcom,jtagv8-mm";
511 reg = <0x9340000 0x1000>;
512 reg-names = "etm-base";
513
514 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
515 clock-names = "core_clk";
516
517 qcom,coresight-jtagmm-cpu = <&CPU3>;
518 };
519
520 jtag_mm4: jtagmm@9440000 {
521 compatible = "qcom,jtagv8-mm";
522 reg = <0x9440000 0x1000>;
523 reg-names = "etm-base";
524
525 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
526 clock-names = "core_clk";
527
528 qcom,coresight-jtagmm-cpu = <&CPU4>;
529 };
530
531 jtag_mm5: jtagmm@9540000 {
532 compatible = "qcom,jtagv8-mm";
533 reg = <0x9540000 0x1000>;
534 reg-names = "etm-base";
535
536 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
537 clock-names = "core_clk";
538
539 qcom,coresight-jtagmm-cpu = <&CPU5>;
540 };
541
542 jtag_mm6: jtagmm@9640000 {
543 compatible = "qcom,jtagv8-mm";
544 reg = <0x9640000 0x1000>;
545 reg-names = "etm-base";
546
547 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
548 clock-names = "core_clk";
549
550 qcom,coresight-jtagmm-cpu = <&CPU6>;
551 };
552
553 jtag_mm7: jtagmm@9740000 {
554 compatible = "qcom,jtagv8-mm";
555 reg = <0x9740000 0x1000>;
556 reg-names = "etm-base";
557
558 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
559 clock-names = "core_clk";
560
561 qcom,coresight-jtagmm-cpu = <&CPU7>;
562 };
563
564 qcom,memshare {
565 compatible = "qcom,memshare";
566
567 qcom,client_1 {
568 compatible = "qcom,memshare-peripheral";
569 qcom,peripheral-size = <0x0>;
570 qcom,client-id = <0>;
571 qcom,allocate-boot-time;
572 label = "modem";
573 };
574
575 qcom,client_2 {
576 compatible = "qcom,memshare-peripheral";
577 qcom,peripheral-size = <0x0>;
578 qcom,client-id = <2>;
579 label = "modem";
580 };
581
582 mem_client_3_size: qcom,client_3 {
583 compatible = "qcom,memshare-peripheral";
584 qcom,peripheral-size = <0x500000>;
585 qcom,client-id = <1>;
586 qcom,allocate-on-request;
587 label = "modem";
588 };
589 };
590
591 slim_aud: slim@a5c0000 {
592 cell-index = <1>;
593 compatible = "qcom,slim-ngd";
594 reg = <0xa5c0000 0x2c000>,
595 <0xa584000 0x20000>, <0xa66e000 0x2000>;
596 reg-names = "slimbus_physical",
597 "slimbus_bam_physical", "slimbus_lpass_mem";
598 interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
599 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>;
600 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
601 qcom,apps-ch-pipes = <0x0>;
602 qcom,ea-pc = <0x3b0>;
603 status = "ok";
604
605 /* Slimbus Slave DT for WCN3990 */
606 btfmslim_codec: wcn3990 {
607 compatible = "qcom,btfmslim_slave";
608 elemental-addr = [00 01 20 02 17 02];
609 qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
610 qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
611 };
612 };
613
614 wakegic: wake-gic {
615 compatible = "qcom,mpm-gic-khaje", "qcom,mpm-gic";
616 interrupts-extended = <&wakegic GIC_SPI 197
617 IRQ_TYPE_EDGE_RISING>;
618 reg = <0x45f01b8 0x1000>,
619 <0xf011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
620 reg-names = "vmpm", "ipc";
621 qcom,num-mpm-irqs = <96>;
622 interrupt-controller;
623 interrupt-parent = <&intc>;
624 #interrupt-cells = <3>;
625 };
626
627 wakegpio: wake-gpio {
628 compatible = "qcom,mpm-gpio";
629 interrupt-controller;
630 interrupt-parent = <&intc>;
631 #interrupt-cells = <2>;
632 };
633
634 bluetooth: bt_wcn3990 {
635 compatible = "qca,wcn3990";
636 qca,bt-sw-ctrl-gpio = <&tlmm 87 0>; /* SW_CTRL */
637 qca,bt-vdd-io-supply = <&L9A>; /* IO */
638 qca,bt-vdd-core-supply = <&L17A>; /* RFA */
639 qca,bt-vdd-pa-supply = <&L23A>; /* CH0 */
640 qca,bt-vdd-xtal-supply = <&L16A>; /* XO */
641
642 qca,bt-vdd-io-voltage-level = <1700000 1900000>;
643 qca,bt-vdd-core-voltage-level = <1304000 1304000>;
644 qca,bt-vdd-pa-voltage-level = <3000000 3312000>;
645 qca,bt-vdd-xtal-voltage-level = <1700000 1900000>;
646
647 qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */
648 qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
649 qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
650 qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */
651 };
652
653 timer {
654 compatible = "arm,armv8-timer";
655 interrupts = <1 1 0xf08>,
656 <1 2 0xf08>,
657 <1 3 0xf08>,
658 <1 0 0xf08>;
659 clock-frequency = <19200000>;
660 };
661
662 dcc: dcc_v2@1be2000 {
663 compatible = "qcom,dcc-v2";
664 reg = <0x1be2000 0x1000>,
665 <0x1bee000 0x2000>;
666 reg-names = "dcc-base", "dcc-ram-base";
667 dcc-ram-offset = <0x2000>;
668
669 link_list1 {
670 qcom,curr-link-list = <3>;
671 qcom,data-sink = "sram";
672 qcom,link-list = <DCC_READ 0x0F1880B4 1 0>,
673 <DCC_READ 0x0F1980B4 1 0>,
674 <DCC_READ 0x0F1A80B4 1 0>,
675 <DCC_READ 0x0F1B80B4 1 0>,
676 <DCC_READ 0x0F0880B4 1 0>,
677 <DCC_READ 0x0F0980B4 1 0>,
678 <DCC_READ 0x0F0A80B4 1 0>,
679 <DCC_READ 0x0F0B80B4 1 0>,
680 <DCC_READ 0x0F1D1228 1 0>,
681 <DCC_READ 0x0F1880B0 1 0>,
682 <DCC_READ 0x0F1980B0 1 0>,
683 <DCC_READ 0x0F1A80B0 1 0>,
684 <DCC_READ 0x0F1B80B0 1 0>,
685 <DCC_READ 0x0F0880B0 1 0>,
686 <DCC_READ 0x0F0980B0 1 0>,
687 <DCC_READ 0x0F0A80B0 1 0>,
688 <DCC_READ 0x0F0B80B0 1 0>,
689 <DCC_READ 0x0F1880B8 1 0>,
690 <DCC_READ 0x0F1980B8 1 0>,
691 <DCC_READ 0x0F1A80B8 1 0>,
692 <DCC_READ 0x0F1B80B8 1 0>,
693 <DCC_READ 0x0F0880B8 1 0>,
694 <DCC_READ 0x0F0980B8 1 0>,
695 <DCC_READ 0x0F0A80B8 1 0>,
696 <DCC_READ 0x0F0B80B8 1 0>,
697 <DCC_READ 0x0F1D160C 1 0>,
698 <DCC_READ 0x0F1D120C 1 0>,
699 <DCC_READ 0x0F1D1434 1 0>,
700 <DCC_READ 0x0F1D141C 5 0>,
701 <DCC_READ 0x0F1D1448 1 0>,
702 <DCC_READ 0x0F1D144C 1 0>,
703 <DCC_READ 0xA754520 1 0>,
704 <DCC_READ 0xA751020 1 0>,
705 <DCC_READ 0xA751024 1 0>,
706 <DCC_READ 0xA751030 1 0>,
707 <DCC_READ 0xA751200 1 0>,
708 <DCC_READ 0xA751214 1 0>,
709 <DCC_READ 0xA751228 1 0>,
710 <DCC_READ 0xA75123C 1 0>,
711 <DCC_READ 0xA751250 1 0>,
712 <DCC_READ 0xA751204 1 0>,
713 <DCC_READ 0xA751218 1 0>,
714 <DCC_READ 0xA75122C 1 0>,
715 <DCC_READ 0xA751240 1 0>,
716 <DCC_READ 0xA751254 1 0>,
717 <DCC_READ 0xA751208 1 0>,
718 <DCC_READ 0xA75121C 1 0>,
719 <DCC_READ 0xA751230 1 0>,
720 <DCC_READ 0xA751244 1 0>,
721 <DCC_READ 0xA751258 1 0>,
722 <DCC_READ 0xA754510 1 0>,
723 <DCC_READ 0xA754514 1 0>,
724 <DCC_READ 0xA750010 1 0>,
725 <DCC_READ 0xA750014 1 0>,
726 <DCC_READ 0xA750900 1 0>,
727 <DCC_READ 0xA750904 1 0>,
728 <DCC_READ 0x0A402028 1 0>,
729 <DCC_READ 0x0A900010 1 0>,
730 <DCC_READ 0x0A900014 1 0>,
731 <DCC_READ 0x0A900018 1 0>,
732 <DCC_READ 0x0A900030 1 0>,
733 <DCC_READ 0x0A900038 1 0>,
734 <DCC_READ 0x0A900040 1 0>,
735 <DCC_READ 0x0A900048 1 0>,
736 <DCC_READ 0x0A9000D0 1 0>,
737 <DCC_READ 0x0A900210 1 0>,
738 <DCC_READ 0x0A900230 1 0>,
739 <DCC_READ 0x0A900250 1 0>,
740 <DCC_READ 0x0A900270 1 0>,
741 <DCC_READ 0x0A900290 1 0>,
742 <DCC_READ 0x0A9002B0 1 0>,
743 <DCC_READ 0x0A900208 1 0>,
744 <DCC_READ 0x0A900228 1 0>,
745 <DCC_READ 0x0A900248 1 0>,
746 <DCC_READ 0x0A900268 1 0>,
747 <DCC_READ 0x0A900288 1 0>,
748 <DCC_READ 0x0A9002A8 1 0>,
749 <DCC_READ 0x0A90020C 1 0>,
750 <DCC_READ 0x0A90022C 1 0>,
751 <DCC_READ 0x0A90024C 1 0>,
752 <DCC_READ 0x0A90026C 1 0>,
753 <DCC_READ 0x0A90028C 1 0>,
754 <DCC_READ 0x0A9002AC 1 0>,
755 <DCC_READ 0x0A900404 1 0>,
756 <DCC_READ 0x0A900408 1 0>,
757 <DCC_READ 0x0A900400 1 0>,
758 <DCC_READ 0x0A900D04 1 0>,
759 <DCC_READ 0x0A4B0010 1 0>,
760 <DCC_READ 0x0A4B0014 1 0>,
761 <DCC_READ 0x0A4B0018 1 0>,
762 <DCC_READ 0x0A4B0210 1 0>,
763 <DCC_READ 0x0A4B0230 1 0>,
764 <DCC_READ 0x0A4B0250 1 0>,
765 <DCC_READ 0x0A4B0270 1 0>,
766 <DCC_READ 0x0A4B0290 1 0>,
767 <DCC_READ 0x0A4B02B0 1 0>,
768 <DCC_READ 0x0A4B0208 1 0>,
769 <DCC_READ 0x0A4B0228 1 0>,
770 <DCC_READ 0x0A4B0248 1 0>,
771 <DCC_READ 0x0A4B0268 1 0>,
772 <DCC_READ 0x0A4B0288 1 0>,
773 <DCC_READ 0x0A4B02A8 1 0>,
774 <DCC_READ 0x0A4B020C 1 0>,
775 <DCC_READ 0x0A4B022C 1 0>,
776 <DCC_READ 0x0A4B024C 1 0>,
777 <DCC_READ 0x0A4B026C 1 0>,
778 <DCC_READ 0x0A4B028C 1 0>,
779 <DCC_READ 0x0A4B02AC 1 0>,
780 <DCC_READ 0x0A4B0400 1 0>,
781 <DCC_READ 0x0A4B0404 1 0>,
782 <DCC_READ 0x0A4B0408 1 0>,
783 <DCC_READ 0x4488100 1 0>,
784 <DCC_READ 0x4488400 2 0>,
785 <DCC_READ 0x4488410 1 0>,
786 <DCC_READ 0x4488420 2 0>,
787 <DCC_READ 0x4488430 2 0>,
788 <DCC_READ 0x448c100 1 0>,
789 <DCC_READ 0x448c400 2 0>,
790 <DCC_READ 0x448c410 1 0>,
791 <DCC_READ 0x448c420 2 0>,
792 <DCC_READ 0x448c430 2 0>,
793 <DCC_READ 0x4490100 1 0>,
794 <DCC_READ 0x4490400 2 0>,
795 <DCC_READ 0x4490410 1 0>,
796 <DCC_READ 0x4490420 2 0>,
797 <DCC_READ 0x4490430 2 0>,
798 <DCC_READ 0x4494100 1 0>,
799 <DCC_READ 0x4494400 2 0>,
800 <DCC_READ 0x4494410 1 0>,
801 <DCC_READ 0x4494420 2 0>,
802 <DCC_READ 0x4494430 2 0>,
803 <DCC_READ 0x449810c 1 0>,
804 <DCC_READ 0x4498400 2 0>,
805 <DCC_READ 0x4498410 1 0>,
806 <DCC_READ 0x4498420 2 0>,
807 <DCC_READ 0x4498430 2 0>,
808 <DCC_READ 0x44a0100 1 0>,
809 <DCC_READ 0x44a0400 2 0>,
810 <DCC_READ 0x44a0410 1 0>,
811 <DCC_READ 0x44a0420 2 0>,
812 <DCC_READ 0x44a0430 2 0>,
813 <DCC_READ 0x44b0560 1 0>,
814 <DCC_READ 0x44b05a0 1 0>,
815 <DCC_READ 0x44b1800 1 0>,
816 <DCC_READ 0x44b408c 1 0>,
817 <DCC_READ 0x44b409c 1 0>,
818 <DCC_READ 0x44b0520 1 0>,
819 <DCC_READ 0x44b5070 2 0>,
820 <DCC_READ 0x44bc220 1 0>,
821 <DCC_READ 0x44bc400 7 0>,
822 <DCC_READ 0x44bc420 9 0>,
823 <DCC_READ 0x44bd800 1 0>,
824 <DCC_READ 0x44c5800 1 0>,
825 <DCC_READ 0x4480040 2 0>,
826 <DCC_READ 0x4480810 2 0>,
827 <DCC_READ 0x44b0a40 1 0>,
828 <DCC_READ 0x4506044 1 0>,
829 <DCC_READ 0x45061dc 1 0>,
830 <DCC_READ 0x45061ec 1 0>,
831 <DCC_READ 0x4506028 2 0>,
832 <DCC_READ 0x4506094 1 0>,
833 <DCC_READ 0x4506608 1 0>,
834 <DCC_READ 0x447d02c 4 0>,
835 <DCC_READ 0x447d040 1 0>,
836 <DCC_READ 0x450002c 2 0>,
837 <DCC_READ 0x4500094 1 0>,
838 <DCC_READ 0x450009c 1 0>,
839 <DCC_READ 0x45000c4 2 0>,
840 <DCC_READ 0x45003dc 1 0>,
841 <DCC_READ 0x45005d8 1 0>,
842 <DCC_READ 0x450102c 2 0>,
843 <DCC_READ 0x4501094 1 0>,
844 <DCC_READ 0x450109c 1 0>,
845 <DCC_READ 0x45010c4 2 0>,
846 <DCC_READ 0x45013dc 1 0>,
847 <DCC_READ 0x45015d8 1 0>,
848 <DCC_READ 0x450202c 2 0>,
849 <DCC_READ 0x4502094 1 0>,
850 <DCC_READ 0x450209c 1 0>,
851 <DCC_READ 0x45020c4 2 0>,
852 <DCC_READ 0x45023dc 1 0>,
853 <DCC_READ 0x45025d8 1 0>,
854 <DCC_READ 0x450302c 2 0>,
855 <DCC_READ 0x4503094 1 0>,
856 <DCC_READ 0x450309c 1 0>,
857 <DCC_READ 0x45030c4 2 0>,
858 <DCC_READ 0x45033dc 1 0>,
859 <DCC_READ 0x45035d8 1 0>,
860 <DCC_READ 0x450402c 2 0>,
861 <DCC_READ 0x4504094 1 0>,
862 <DCC_READ 0x450409c 1 0>,
863 <DCC_READ 0x45040c8 2 0>,
864 <DCC_READ 0x45043dc 1 0>,
865 <DCC_READ 0x45045d8 1 0>,
866 <DCC_READ 0x450502c 2 0>,
867 <DCC_READ 0x4505094 1 0>,
868 <DCC_READ 0x450509c 1 0>,
869 <DCC_READ 0x45050c4 2 0>,
870 <DCC_READ 0x45053dc 1 0>,
871 <DCC_READ 0x45055d8 1 0>,
872 <DCC_READ 0x141102C 1 0>,
873 <DCC_READ 0x1436004 1 0>,
874 <DCC_READ 0x1471154 1 0>,
875 <DCC_READ 0x141050C 1 0>,
876 <DCC_READ 0x143600C 1 0>,
877 <DCC_READ 0x1436018 1 0>,
878 <DCC_READ 0x147C000 1 0>,
879 <DCC_READ 0x147D000 1 0>,
880 <DCC_READ 0x1436048 1 0>,
881 <DCC_READ 0x1436040 1 0>,
882 <DCC_READ 0x5991004 1 0>,
883 <DCC_READ 0x599100c 1 0>,
884 <DCC_READ 0x5991010 1 0>,
885 <DCC_READ 0x5991014 1 0>,
886 <DCC_READ 0x5991054 1 0>,
887 <DCC_READ 0x5991060 1 0>,
888 <DCC_READ 0x599106c 1 0>,
889 <DCC_READ 0x5991070 1 0>,
890 <DCC_READ 0x5991074 1 0>,
891 <DCC_READ 0x5991078 1 0>,
892 <DCC_READ 0x599107c 1 0>,
893 <DCC_READ 0x599108c 1 0>,
894 <DCC_READ 0x5991098 1 0>,
895 <DCC_READ 0x599109c 1 0>,
896 <DCC_READ 0x5991540 1 0>,
897 <DCC_READ 0x5995000 1 0>,
898 <DCC_READ 0x5995004 1 0>,
899 <DCC_READ 0x599101C 1 0>,
900 <DCC_READ 0x5991020 1 0>,
901 <DCC_READ 0x5990000 1 0>,
902 <DCC_READ 0x5990100 1 0>,
903 <DCC_READ 0x5991508 1 0>,
904 <DCC_READ 0x59910A4 1 0>,
905 <DCC_READ 0x5991578 1 0>,
906 <DCC_READ 0x5990010 1 0>,
907 <DCC_READ 0x5990110 1 0>,
908 <DCC_READ 0xf189000 1 0>,
909 <DCC_READ 0xf18900c 1 0>,
910 <DCC_READ 0xf189c0c 1 0>,
911 <DCC_READ 0xf189c10 1 0>,
912 <DCC_READ 0xf189c20 1 0>,
913 <DCC_READ 0xf199000 1 0>,
914 <DCC_READ 0xf19900c 1 0>,
915 <DCC_READ 0xf199c0c 1 0>,
916 <DCC_READ 0xf199c10 1 0>,
917 <DCC_READ 0xf199c20 1 0>,
918 <DCC_READ 0xf1a9000 1 0>,
919 <DCC_READ 0xf1a900c 1 0>,
920 <DCC_READ 0xf1a9c0c 1 0>,
921 <DCC_READ 0xf1a9c10 1 0>,
922 <DCC_READ 0xf1a9c20 1 0>,
923 <DCC_READ 0xf1b9000 1 0>,
924 <DCC_READ 0xf1b900c 1 0>,
925 <DCC_READ 0xf1b9c0c 1 0>,
926 <DCC_READ 0xf1b9c10 1 0>,
927 <DCC_READ 0xf1b9c18 1 0>,
928 <DCC_READ 0xf089000 1 0>,
929 <DCC_READ 0xf08900c 1 0>,
930 <DCC_READ 0xf089c0c 1 0>,
931 <DCC_READ 0xf089c10 1 0>,
932 <DCC_READ 0xf089c20 1 0>,
933 <DCC_READ 0xf099000 1 0>,
934 <DCC_READ 0xf09900c 1 0>,
935 <DCC_READ 0xf099c0c 1 0>,
936 <DCC_READ 0xf099c10 1 0>,
937 <DCC_READ 0xf099c20 1 0>,
938 <DCC_READ 0xf0a9000 1 0>,
939 <DCC_READ 0xf0a900c 1 0>,
940 <DCC_READ 0xf0a9c0c 1 0>,
941 <DCC_READ 0xf0a9c10 1 0>,
942 <DCC_READ 0xf0a9c20 1 0>,
943 <DCC_READ 0xf0b9000 1 0>,
944 <DCC_READ 0xf0b900c 1 0>,
945 <DCC_READ 0xf0b9c0c 1 0>,
946 <DCC_READ 0xf0b9c10 1 0>,
947 <DCC_READ 0xf0b9c20 1 0>,
948 <DCC_READ 0xf112000 1 0>,
949 <DCC_READ 0xf11200c 1 0>,
950 <DCC_READ 0xf112c0c 1 0>,
951 <DCC_READ 0xf112c10 1 0>,
952 <DCC_READ 0xf112c20 1 0>,
953 <DCC_READ 0xf012000 1 0>,
954 <DCC_READ 0xf01200c 1 0>,
955 <DCC_READ 0xf012c0c 1 0>,
956 <DCC_READ 0xf012c10 1 0>,
957 <DCC_READ 0xf012c20 1 0>,
958 <DCC_READ 0xf1d2000 1 0>,
959 <DCC_READ 0xf1d200c 1 0>,
960 <DCC_READ 0xf1d2c0c 1 0>,
961 <DCC_READ 0xf1d2c10 1 0>,
962 <DCC_READ 0xf1d2c20 1 0>,
963 <DCC_READ 0xf011014 1 0>,
964 <DCC_READ 0xf011018 1 0>,
965 <DCC_READ 0xf011218 1 0>,
966 <DCC_READ 0xf011234 1 0>,
967 <DCC_READ 0xf011220 1 0>,
968 <DCC_READ 0xf011264 1 0>,
969 <DCC_READ 0xf011290 1 0>,
970 <DCC_READ 0xf111014 1 0>,
971 <DCC_READ 0xf111018 1 0>,
972 <DCC_READ 0xf111218 1 0>,
973 <DCC_READ 0xf111234 1 0>,
974 <DCC_READ 0xf111264 1 0>,
975 <DCC_READ 0xf111290 1 0>,
976 <DCC_READ 0x0F521700 1 0>,
977 <DCC_READ 0x0F523700 1 0>,
978 <DCC_READ 0x0F112C18 1 0>,
979 <DCC_READ 0x0F012C18 1 0>,
980 <DCC_READ 0x0F513A84 1 0>,
981 <DCC_READ 0x0F513A88 1 0>,
982 <DCC_READ 0x01B60110 1 0>,
983 <DCC_READ 0x1900010 1 0>,
984 <DCC_READ 0x1900020 1 0>,
985 <DCC_READ 0x1900024 1 0>,
986 <DCC_READ 0x1900028 1 0>,
987 <DCC_READ 0x190002C 1 0>,
988 <DCC_READ 0x1900030 1 0>,
989 <DCC_READ 0x1900034 1 0>,
990 <DCC_READ 0x1900038 1 0>,
991 <DCC_READ 0x190003C 1 0>,
992 <DCC_READ 0x1900300 1 0>,
993 <DCC_READ 0x1900304 1 0>,
994 <DCC_READ 0x1900308 1 0>,
995 <DCC_READ 0x190030C 1 0>,
996 <DCC_READ 0x1900310 1 0>,
997 <DCC_READ 0x1900314 1 0>,
998 <DCC_READ 0x1900900 1 0>,
999 <DCC_READ 0x1900904 1 0>,
1000 <DCC_READ 0x1900B00 1 0>,
1001 <DCC_READ 0x1900D00 1 0>,
1002 <DCC_READ 0x1909100 1 0>,
1003 <DCC_READ 0x1909104 1 0>,
1004 <DCC_READ 0x1480140 1 0>,
1005 <DCC_READ 0x1481140 1 0>,
1006 <DCC_READ 0x1415008 1 0>,
1007 <DCC_READ 0x1416008 1 0>,
1008 <DCC_READ 0x44B0120 1 0>,
1009 <DCC_READ 0x44B0124 1 0>,
1010 <DCC_READ 0x44B0128 1 0>,
1011 <DCC_READ 0x44B012C 1 0>,
1012 <DCC_READ 0x44B0130 1 0>,
1013 <DCC_READ 0x44B0100 1 0>,
1014 <DCC_READ 0x44B0020 1 0>,
1015 <DCC_READ 0x44C4000 1 0>,
1016 <DCC_READ 0x44C4020 1 0>,
1017 <DCC_READ 0x44C4030 1 0>,
1018 <DCC_READ 0x44C4100 1 0>,
1019 <DCC_READ 0x44C410C 1 0>,
1020 <DCC_READ 0x44C4400 1 0>,
1021 <DCC_READ 0x44C4410 1 0>,
1022 <DCC_READ 0x44C4420 1 0>,
1023 <DCC_READ 0x1900240 1 0>,
1024 <DCC_READ 0x1900244 1 0>,
1025 <DCC_READ 0x1900248 1 0>,
1026 <DCC_READ 0x190024C 1 0>,
1027 <DCC_READ 0x1900250 1 0>,
1028 <DCC_READ 0x1900258 1 0>,
1029 <DCC_READ 0x1411004 1 0>,
1030 <DCC_READ 0x1411028 1 0>,
1031 <DCC_READ 0x1458004 1 0>,
1032 <DCC_READ 0x1880108 1 0>,
1033 <DCC_READ 0x1880110 1 0>,
1034 <DCC_READ 0x1880120 1 0>,
1035 <DCC_READ 0x1880124 1 0>,
1036 <DCC_READ 0x1880128 1 0>,
1037 <DCC_READ 0x188012C 1 0>,
1038 <DCC_READ 0x1880130 1 0>,
1039 <DCC_READ 0x1880134 1 0>,
1040 <DCC_READ 0x1880138 1 0>,
1041 <DCC_READ 0x188013C 1 0>,
1042 <DCC_READ 0x1880300 1 0>,
1043 <DCC_READ 0x1880304 1 0>,
1044 <DCC_READ 0x1880308 1 0>,
1045 <DCC_READ 0x188030C 1 0>,
1046 <DCC_READ 0x1880310 1 0>,
1047 <DCC_READ 0x1880314 1 0>,
1048 <DCC_READ 0x1880318 1 0>,
1049 <DCC_READ 0x188031C 1 0>,
1050 <DCC_READ 0x1880700 1 0>,
1051 <DCC_READ 0x1880704 1 0>,
1052 <DCC_READ 0x1880708 1 0>,
1053 <DCC_READ 0x188070C 1 0>,
1054 <DCC_READ 0x1880710 1 0>,
1055 <DCC_READ 0x1880714 1 0>,
1056 <DCC_READ 0x1880718 1 0>,
1057 <DCC_READ 0x188071C 1 0>,
1058 <DCC_READ 0x1881100 1 0>,
1059 <DCC_READ 0x1880240 1 0>,
1060 <DCC_READ 0x1880248 1 0>,
1061 <DCC_READ 0xF017000 1 0>,
1062 <DCC_READ 0xF01700C 1 0>,
1063 <DCC_READ 0xF017010 1 0>,
1064 <DCC_READ 0xF017014 1 0>,
1065 <DCC_READ 0xF017018 1 0>,
1066 <DCC_READ 0xF017020 1 0>,
1067 <DCC_READ 0x1414008 1 0>,
1068 <DCC_READ 0x1414004 1 0>,
1069 <DCC_READ 0x5991554 1 0>,
1070 <DCC_READ 0x5991544 1 0>,
1071 <DCC_READ 0x599155C 1 0>,
1072 <DCC_READ 0x440B00C 1 0>,
1073 <DCC_READ 0x440B014 1 0>,
1074 <DCC_READ 0x0F522C14 1 0>,
1075 <DCC_READ 0x0F522C1C 1 0>,
1076 <DCC_READ 0x0F522C10 1 0>,
1077 <DCC_READ 0x0F524C10 1 0>,
1078 <DCC_READ 0x0F524C14 1 0>,
1079 <DCC_READ 0x0F524C18 1 0>,
1080 <DCC_READ 0x0F524C1C 1 0>,
1081 <DCC_READ 0x0F521920 1 0>,
1082 <DCC_READ 0x0F52102C 1 0>,
1083 <DCC_READ 0x0F521044 1 0>,
1084 <DCC_READ 0x0F521710 1 0>,
1085 <DCC_READ 0x0F52176C 1 0>,
1086 <DCC_READ 0x0F523920 1 0>,
1087 <DCC_READ 0x0F52302C 1 0>,
1088 <DCC_READ 0x0F523044 1 0>,
1089 <DCC_READ 0x0F523710 1 0>,
1090 <DCC_READ 0x0F52376C 1 0>,
1091 <DCC_READ 0x0F116000 1 0>,
1092 <DCC_READ 0x0F116004 1 0>,
1093 <DCC_READ 0x0F11602C 1 0>,
1094 <DCC_READ 0x0F016000 1 0>,
1095 <DCC_READ 0x0F016004 1 0>,
1096 <DCC_READ 0x0F01602C 1 0>,
1097 <DCC_READ 0x0F111250 1 0>,
1098 <DCC_READ 0x0F111254 1 0>,
1099 <DCC_READ 0x0F111258 1 0>,
1100 <DCC_READ 0x0F11125C 1 0>,
1101 <DCC_READ 0x0F111260 1 0>,
1102 <DCC_READ 0x0F188078 1 0>,
1103 <DCC_READ 0x0F188084 1 0>,
1104 <DCC_READ 0x0F198078 1 0>,
1105 <DCC_READ 0x0F198084 1 0>,
1106 <DCC_READ 0x0F1A8078 1 0>,
1107 <DCC_READ 0x0F1A8084 1 0>,
1108 <DCC_READ 0x0F1B8078 1 0>,
1109 <DCC_READ 0x0F1B8084 1 0>,
1110 <DCC_READ 0x0F521818 1 0>,
1111 <DCC_READ 0x0F52181C 1 0>,
1112 <DCC_READ 0x0F521828 1 0>,
1113 <DCC_READ 0x0F523818 1 0>,
1114 <DCC_READ 0x0F52381C 1 0>,
1115 <DCC_READ 0x0F523828 1 0>,
1116 <DCC_READ 0x0F522C18 1 0>,
1117 <DCC_READ 0x0F111310 1 0>,
1118 <DCC_READ 0x0F111314 1 0>,
1119 <DCC_READ 0x0F111318 1 0>,
1120 <DCC_READ 0x0F01125C 1 0>,
1121 <DCC_READ 0x0F011258 1 0>,
1122 <DCC_READ 0x0F011310 1 0>,
1123 <DCC_READ 0x0F011314 1 0>,
1124 <DCC_READ 0x0F011318 1 0>,
1125 <DCC_WRITE 0x9870010 0x14000 0>,
1126 <DCC_READ 0xF011600 1 0>,
1127 <DCC_READ 0xF011608 1 0>,
1128 <DCC_READ 0xF01160C 1 0>,
1129 <DCC_READ 0xF011610 1 0>,
1130 <DCC_READ 0xF011614 1 0>,
1131 <DCC_READ 0xF011618 1 0>,
1132 <DCC_READ 0xF01161C 1 0>,
1133 <DCC_READ 0xF011620 1 0>,
1134 <DCC_READ 0xF011624 1 0>,
1135 <DCC_READ 0xF011628 1 0>,
1136 <DCC_READ 0xF01162C 1 0>,
1137 <DCC_READ 0xF011630 1 0>,
1138 <DCC_READ 0xF011634 1 0>,
1139 <DCC_READ 0xF011638 1 0>,
1140 <DCC_READ 0xF01163C 1 0>,
1141 <DCC_READ 0xF011640 1 0>,
1142 <DCC_READ 0xF011644 1 0>,
1143 <DCC_READ 0xF011648 1 0>,
1144 <DCC_READ 0xF01164C 1 0>,
1145 <DCC_READ 0xF011650 1 0>,
1146 <DCC_READ 0xF011654 1 0>,
1147 <DCC_READ 0xF011658 1 0>,
1148 <DCC_READ 0xF01165C 1 0>,
1149 <DCC_READ 0xF011664 1 0>,
1150 <DCC_READ 0xF111600 1 0>,
1151 <DCC_READ 0xF111608 1 0>,
1152 <DCC_READ 0xF11160C 1 0>,
1153 <DCC_READ 0xF111610 1 0>,
1154 <DCC_READ 0xF111614 1 0>,
1155 <DCC_READ 0xF111618 1 0>,
1156 <DCC_READ 0xF11161C 1 0>,
1157 <DCC_READ 0xF111620 1 0>,
1158 <DCC_READ 0xF111624 1 0>,
1159 <DCC_READ 0xF111628 1 0>,
1160 <DCC_READ 0xF11162C 1 0>,
1161 <DCC_READ 0xF111630 1 0>,
1162 <DCC_READ 0xF111634 1 0>,
1163 <DCC_READ 0xF111638 1 0>,
1164 <DCC_READ 0xF11163C 1 0>,
1165 <DCC_READ 0xF111640 1 0>,
1166 <DCC_READ 0xF111644 1 0>,
1167 <DCC_READ 0xF111648 1 0>,
1168 <DCC_READ 0xF111650 1 0>,
1169 <DCC_READ 0xF111654 1 0>,
1170 <DCC_READ 0xF111658 1 0>,
1171 <DCC_READ 0xF11165C 1 0>,
1172 <DCC_READ 0xF111664 1 0>,
1173 <DCC_READ 0xF011400 1 0>,
1174 <DCC_READ 0xF111400 1 0>,
1175 <DCC_WRITE 0x9870010 0x0 0>,
1176 <DCC_READ 0x06130010 1 0>,
1177 <DCC_READ 0x06130014 1 0>,
1178 <DCC_READ 0x06130018 1 0>,
1179 <DCC_READ 0x06130210 1 0>,
1180 <DCC_READ 0x06130230 1 0>,
1181 <DCC_READ 0x06130250 1 0>,
1182 <DCC_READ 0x06130270 1 0>,
1183 <DCC_READ 0x06130290 1 0>,
1184 <DCC_READ 0x061302B0 1 0>,
1185 <DCC_READ 0x06130208 1 0>,
1186 <DCC_READ 0x06130228 1 0>,
1187 <DCC_READ 0x06130248 1 0>,
1188 <DCC_READ 0x06130268 1 0>,
1189 <DCC_READ 0x06130288 1 0>,
1190 <DCC_READ 0x061302A8 1 0>,
1191 <DCC_READ 0x0613020C 1 0>,
1192 <DCC_READ 0x0613022C 1 0>,
1193 <DCC_READ 0x0613024C 1 0>,
1194 <DCC_READ 0x0613026C 1 0>,
1195 <DCC_READ 0x0613028C 1 0>,
1196 <DCC_READ 0x061302AC 1 0>,
1197 <DCC_READ 0x06130400 1 0>,
1198 <DCC_READ 0x06130404 1 0>,
1199 <DCC_READ 0x06130408 1 0>,
1200 <DCC_READ 0x6082028 1 0>,
1201 <DCC_READ 0x0143300C 1 0>,
1202 <DCC_READ 0x0B3B0010 1 0>,
1203 <DCC_READ 0x0B3B0014 1 0>,
1204 <DCC_READ 0x0B3B0018 1 0>,
1205 <DCC_READ 0x0B3B0210 1 0>,
1206 <DCC_READ 0x0B3B0230 1 0>,
1207 <DCC_READ 0x0B3B0250 1 0>,
1208 <DCC_READ 0x0B3B0270 1 0>,
1209 <DCC_READ 0x0B3B0290 1 0>,
1210 <DCC_READ 0x0B3B02B0 1 0>,
1211 <DCC_READ 0x0B3B0208 1 0>,
1212 <DCC_READ 0x0B3B0228 1 0>,
1213 <DCC_READ 0x0B3B0248 1 0>,
1214 <DCC_READ 0x0B3B0268 1 0>,
1215 <DCC_READ 0x0B3B0288 1 0>,
1216 <DCC_READ 0x0B3B02A8 1 0>,
1217 <DCC_READ 0x0B3B020C 1 0>,
1218 <DCC_READ 0x0B3B022C 1 0>,
1219 <DCC_READ 0x0B3B024C 1 0>,
1220 <DCC_READ 0x0B3B026C 1 0>,
1221 <DCC_READ 0x0B3B028C 1 0>,
1222 <DCC_READ 0x0B3B02AC 1 0>,
1223 <DCC_READ 0x0B3B0400 1 0>,
1224 <DCC_READ 0x0B3B0404 1 0>,
1225 <DCC_READ 0x0B3B0408 1 0>,
1226 <DCC_READ 0x0B302028 1 0>,
1227 <DCC_READ 0x0B300044 1 0>,
1228 <DCC_READ 0x0B300304 1 0>,
1229 <DCC_READ 0x5C6F000 1 0>,
1230 <DCC_READ 0x5C42000 1 0>,
1231 <DCC_READ 0x5C42400 1 0>,
1232 <DCC_READ 0x5C23000 1 0>;
1233 };
1234
1235 link_list2 {
1236 qcom,curr-link-list = <2>;
1237 qcom,data-sink = "sram";
1238 qcom,link-list = <DCC_READ 0x01480140 1 0>,
1239 <DCC_READ 0x01481140 1 0>,
1240 <DCC_READ 0x0148014C 1 0>,
1241 <DCC_READ 0x0148114C 1 0>,
1242 <DCC_READ 0x01477008 1 0>,
1243 <DCC_READ 0x01439000 1 0>,
1244 <DCC_READ 0x01415010 1 0>,
1245 <DCC_READ 0x01416010 1 0>,
1246 <DCC_READ 0x0142A00C 1 0>,
1247 <DCC_READ 0x1400000 1 0>,
1248 <DCC_READ 0x1400004 1 0>,
1249 <DCC_READ 0x1400008 1 0>,
1250 <DCC_READ 0x140000C 1 0>,
1251 <DCC_READ 0x1400010 1 0>,
1252 <DCC_READ 0x1400014 1 0>,
1253 <DCC_READ 0x1400018 1 0>,
1254 <DCC_READ 0x140001C 1 0>,
1255 <DCC_READ 0x1400020 1 0>,
1256 <DCC_READ 0x1400024 1 0>,
1257 <DCC_READ 0x1401000 1 0>,
1258 <DCC_READ 0x1401004 1 0>,
1259 <DCC_READ 0x1401008 1 0>,
1260 <DCC_READ 0x140100C 1 0>,
1261 <DCC_READ 0x1401010 1 0>,
1262 <DCC_READ 0x1401014 1 0>,
1263 <DCC_READ 0x1401018 1 0>,
1264 <DCC_READ 0x140101C 1 0>,
1265 <DCC_READ 0x1401020 1 0>,
1266 <DCC_READ 0x1401024 1 0>,
1267 <DCC_READ 0x1402000 1 0>,
1268 <DCC_READ 0x1402004 1 0>,
1269 <DCC_READ 0x1402008 1 0>,
1270 <DCC_READ 0x140200C 1 0>,
1271 <DCC_READ 0x1402010 1 0>,
1272 <DCC_READ 0x1402014 1 0>,
1273 <DCC_READ 0x1402018 1 0>,
1274 <DCC_READ 0x140201C 1 0>,
1275 <DCC_READ 0x1402020 1 0>,
1276 <DCC_READ 0x1402024 1 0>,
1277 <DCC_READ 0x1403000 1 0>,
1278 <DCC_READ 0x1403004 1 0>,
1279 <DCC_READ 0x1403008 1 0>,
1280 <DCC_READ 0x140300C 1 0>,
1281 <DCC_READ 0x1403010 1 0>,
1282 <DCC_READ 0x1403014 1 0>,
1283 <DCC_READ 0x1403018 1 0>,
1284 <DCC_READ 0x140301C 1 0>,
1285 <DCC_READ 0x1403020 1 0>,
1286 <DCC_READ 0x1403024 1 0>,
1287 <DCC_READ 0x1404000 1 0>,
1288 <DCC_READ 0x1404004 1 0>,
1289 <DCC_READ 0x1404008 1 0>,
1290 <DCC_READ 0x140400C 1 0>,
1291 <DCC_READ 0x1404010 1 0>,
1292 <DCC_READ 0x1404014 1 0>,
1293 <DCC_READ 0x1404018 1 0>,
1294 <DCC_READ 0x140401C 1 0>,
1295 <DCC_READ 0x1404020 1 0>,
1296 <DCC_READ 0x1404024 1 0>,
1297 <DCC_READ 0x1405000 1 0>,
1298 <DCC_READ 0x1405004 1 0>,
1299 <DCC_READ 0x1405008 1 0>,
1300 <DCC_READ 0x140500C 1 0>,
1301 <DCC_READ 0x1405010 1 0>,
1302 <DCC_READ 0x1405014 1 0>,
1303 <DCC_READ 0x1405018 1 0>,
1304 <DCC_READ 0x140501C 1 0>,
1305 <DCC_READ 0x1405020 1 0>,
1306 <DCC_READ 0x1405024 1 0>,
1307 <DCC_READ 0x1406000 1 0>,
1308 <DCC_READ 0x1406004 1 0>,
1309 <DCC_READ 0x1406008 1 0>,
1310 <DCC_READ 0x140600C 1 0>,
1311 <DCC_READ 0x1406010 1 0>,
1312 <DCC_READ 0x1406014 1 0>,
1313 <DCC_READ 0x1406018 1 0>,
1314 <DCC_READ 0x140601C 1 0>,
1315 <DCC_READ 0x1406020 1 0>,
1316 <DCC_READ 0x1406024 1 0>,
1317 <DCC_READ 0x1407000 1 0>,
1318 <DCC_READ 0x1407004 1 0>,
1319 <DCC_READ 0x1407008 1 0>,
1320 <DCC_READ 0x140700C 1 0>,
1321 <DCC_READ 0x1407010 1 0>,
1322 <DCC_READ 0x1407014 1 0>,
1323 <DCC_READ 0x1407018 1 0>,
1324 <DCC_READ 0x140701C 1 0>,
1325 <DCC_READ 0x1407020 1 0>,
1326 <DCC_READ 0x1407024 1 0>,
1327 <DCC_READ 0x1407028 1 0>,
1328 <DCC_READ 0x140702C 1 0>,
1329 <DCC_READ 0x1407030 1 0>,
1330 <DCC_READ 0x1407034 1 0>,
1331 <DCC_READ 0x1408000 1 0>,
1332 <DCC_READ 0x1408004 1 0>,
1333 <DCC_READ 0x1408008 1 0>,
1334 <DCC_READ 0x140800C 1 0>,
1335 <DCC_READ 0x1408010 1 0>,
1336 <DCC_READ 0x1408014 1 0>,
1337 <DCC_READ 0x1408018 1 0>,
1338 <DCC_READ 0x140801C 1 0>,
1339 <DCC_READ 0x1408020 1 0>,
1340 <DCC_READ 0x1408024 1 0>,
1341 <DCC_READ 0x1409000 1 0>,
1342 <DCC_READ 0x1409004 1 0>,
1343 <DCC_READ 0x1409008 1 0>,
1344 <DCC_READ 0x140900C 1 0>,
1345 <DCC_READ 0x1409010 1 0>,
1346 <DCC_READ 0x1409014 1 0>,
1347 <DCC_READ 0x1409018 1 0>,
1348 <DCC_READ 0x140901C 1 0>,
1349 <DCC_READ 0x1409020 1 0>,
1350 <DCC_READ 0x1409024 1 0>,
1351 <DCC_READ 0x141001C 1 0>,
1352 <DCC_READ 0x14103EC 1 0>,
1353 <DCC_READ 0x1414024 1 0>,
1354 <DCC_READ 0x1415004 1 0>,
1355 <DCC_READ 0x1415008 1 0>,
1356 <DCC_READ 0x141500C 1 0>,
1357 <DCC_READ 0x1415034 1 0>,
1358 <DCC_READ 0x1416004 1 0>,
1359 <DCC_READ 0x1416008 1 0>,
1360 <DCC_READ 0x141600C 1 0>,
1361 <DCC_READ 0x1416038 1 0>,
1362 <DCC_READ 0x141703C 1 0>,
1363 <DCC_READ 0x1417040 1 0>,
1364 <DCC_READ 0x141A004 1 0>,
1365 <DCC_READ 0x141A008 1 0>,
1366 <DCC_READ 0x141A00C 1 0>,
1367 <DCC_READ 0x141A01C 1 0>,
1368 <DCC_READ 0x141A020 1 0>,
1369 <DCC_READ 0x141A034 1 0>,
1370 <DCC_READ 0x141A038 1 0>,
1371 <DCC_READ 0x141A060 1 0>,
1372 <DCC_READ 0x141A064 1 0>,
1373 <DCC_READ 0x141E00C 1 0>,
1374 <DCC_READ 0x141E010 1 0>,
1375 <DCC_READ 0x141F02C 1 0>,
1376 <DCC_READ 0x141F148 1 0>,
1377 <DCC_READ 0x141F14C 1 0>,
1378 <DCC_READ 0x141F15C 1 0>,
1379 <DCC_READ 0x141F278 1 0>,
1380 <DCC_READ 0x141F27C 1 0>,
1381 <DCC_READ 0x141F28C 1 0>,
1382 <DCC_READ 0x141F3A8 1 0>,
1383 <DCC_READ 0x141F3AC 1 0>,
1384 <DCC_READ 0x141F3BC 1 0>,
1385 <DCC_READ 0x141F4D8 1 0>,
1386 <DCC_READ 0x141F4DC 1 0>,
1387 <DCC_READ 0x141F4EC 1 0>,
1388 <DCC_READ 0x141F608 1 0>,
1389 <DCC_READ 0x141F60C 1 0>,
1390 <DCC_READ 0x141F61C 1 0>,
1391 <DCC_READ 0x141F738 1 0>,
1392 <DCC_READ 0x141F73C 1 0>,
1393 <DCC_READ 0x141F74C 1 0>,
1394 <DCC_READ 0x1420010 1 0>,
1395 <DCC_READ 0x1420014 1 0>,
1396 <DCC_READ 0x1426018 1 0>,
1397 <DCC_READ 0x142601C 1 0>,
1398 <DCC_READ 0x1426030 1 0>,
1399 <DCC_READ 0x1426034 1 0>,
1400 <DCC_READ 0x1427024 1 0>,
1401 <DCC_READ 0x1428014 1 0>,
1402 <DCC_READ 0x1428018 1 0>,
1403 <DCC_READ 0x142802C 1 0>,
1404 <DCC_READ 0x1428030 1 0>,
1405 <DCC_READ 0x1429004 1 0>,
1406 <DCC_READ 0x1429008 1 0>,
1407 <DCC_READ 0x142900C 1 0>,
1408 <DCC_READ 0x1429040 1 0>,
1409 <DCC_READ 0x1429044 1 0>,
1410 <DCC_READ 0x142A000 1 0>,
1411 <DCC_READ 0x142A004 1 0>,
1412 <DCC_READ 0x142A008 1 0>,
1413 <DCC_READ 0x142A154 1 0>,
1414 <DCC_READ 0x142A158 1 0>,
1415 <DCC_READ 0x142B13C 1 0>,
1416 <DCC_READ 0x142B140 1 0>,
1417 <DCC_READ 0x142B158 1 0>,
1418 <DCC_READ 0x142B15C 1 0>,
1419 <DCC_READ 0x142E00C 1 0>,
1420 <DCC_READ 0x142E010 1 0>,
1421 <DCC_READ 0x142F00C 1 0>,
1422 <DCC_READ 0x142F010 1 0>,
1423 <DCC_READ 0x1432004 1 0>,
1424 <DCC_READ 0x1432008 1 0>,
1425 <DCC_READ 0x143200C 1 0>,
1426 <DCC_READ 0x1432034 1 0>,
1427 <DCC_READ 0x1432080 1 0>,
1428 <DCC_READ 0x1438010 1 0>,
1429 <DCC_READ 0x1438014 1 0>,
1430 <DCC_READ 0x1438028 1 0>,
1431 <DCC_READ 0x143802C 1 0>,
1432 <DCC_READ 0x143B000 1 0>,
1433 <DCC_READ 0x143B004 1 0>,
1434 <DCC_READ 0x143B008 1 0>,
1435 <DCC_READ 0x143B00C 1 0>,
1436 <DCC_READ 0x143B010 1 0>,
1437 <DCC_READ 0x143B014 1 0>,
1438 <DCC_READ 0x143B018 1 0>,
1439 <DCC_READ 0x143B01C 1 0>,
1440 <DCC_READ 0x143B020 1 0>,
1441 <DCC_READ 0x143B024 1 0>,
1442 <DCC_READ 0x143D01C 1 0>,
1443 <DCC_READ 0x143D020 1 0>,
1444 <DCC_READ 0x143E000 1 0>,
1445 <DCC_READ 0x143E004 1 0>,
1446 <DCC_READ 0x143E008 1 0>,
1447 <DCC_READ 0x143E00C 1 0>,
1448 <DCC_READ 0x143E010 1 0>,
1449 <DCC_READ 0x143E014 1 0>,
1450 <DCC_READ 0x143E018 1 0>,
1451 <DCC_READ 0x143E01C 1 0>,
1452 <DCC_READ 0x143E020 1 0>,
1453 <DCC_READ 0x143E024 1 0>,
1454 <DCC_READ 0x143E060 1 0>,
1455 <DCC_READ 0x143F000 1 0>,
1456 <DCC_READ 0x143F004 1 0>,
1457 <DCC_READ 0x143F008 1 0>,
1458 <DCC_READ 0x143F00C 1 0>,
1459 <DCC_READ 0x143F010 1 0>,
1460 <DCC_READ 0x143F014 1 0>,
1461 <DCC_READ 0x143F018 1 0>,
1462 <DCC_READ 0x143F01C 1 0>,
1463 <DCC_READ 0x143F020 1 0>,
1464 <DCC_READ 0x143F024 1 0>,
1465 <DCC_READ 0x1442018 1 0>,
1466 <DCC_READ 0x144201C 1 0>,
1467 <DCC_READ 0x1442030 1 0>,
1468 <DCC_READ 0x1442034 1 0>,
1469 <DCC_READ 0x1445004 1 0>,
1470 <DCC_READ 0x1445008 1 0>,
1471 <DCC_READ 0x144500C 1 0>,
1472 <DCC_READ 0x1445020 1 0>,
1473 <DCC_READ 0x1445024 1 0>,
1474 <DCC_READ 0x1445048 1 0>,
1475 <DCC_READ 0x144504C 1 0>,
1476 <DCC_READ 0x1445060 1 0>,
1477 <DCC_READ 0x1445064 1 0>,
1478 <DCC_READ 0x144507C 1 0>,
1479 <DCC_READ 0x1445080 1 0>,
1480 <DCC_READ 0x1446004 1 0>,
1481 <DCC_READ 0x1446008 1 0>,
1482 <DCC_READ 0x1446024 1 0>,
1483 <DCC_READ 0x1446150 1 0>,
1484 <DCC_READ 0x1448024 1 0>,
1485 <DCC_READ 0x144D004 1 0>,
1486 <DCC_READ 0x144D008 1 0>,
1487 <DCC_READ 0x144E004 1 0>,
1488 <DCC_READ 0x144E008 1 0>,
1489 <DCC_READ 0x144F004 1 0>,
1490 <DCC_READ 0x144F008 1 0>,
1491 <DCC_READ 0x1451000 1 0>,
1492 <DCC_READ 0x1451004 1 0>,
1493 <DCC_READ 0x145101C 1 0>,
1494 <DCC_READ 0x1451020 1 0>,
1495 <DCC_READ 0x1451038 1 0>,
1496 <DCC_READ 0x145103C 1 0>,
1497 <DCC_READ 0x1451054 1 0>,
1498 <DCC_READ 0x1451058 1 0>,
1499 <DCC_READ 0x1452004 1 0>,
1500 <DCC_READ 0x1452008 1 0>,
1501 <DCC_READ 0x1452028 1 0>,
1502 <DCC_READ 0x145202C 1 0>,
1503 <DCC_READ 0x1454004 1 0>,
1504 <DCC_READ 0x1455000 1 0>,
1505 <DCC_READ 0x1455004 1 0>,
1506 <DCC_READ 0x1457000 1 0>,
1507 <DCC_READ 0x1457004 1 0>,
1508 <DCC_READ 0x1457008 1 0>,
1509 <DCC_READ 0x145700C 1 0>,
1510 <DCC_READ 0x1457010 1 0>,
1511 <DCC_READ 0x145A000 1 0>,
1512 <DCC_READ 0x145A004 1 0>,
1513 <DCC_READ 0x145A008 1 0>,
1514 <DCC_READ 0x145A00C 1 0>,
1515 <DCC_READ 0x145A010 1 0>,
1516 <DCC_READ 0x145B000 1 0>,
1517 <DCC_READ 0x145B004 1 0>,
1518 <DCC_READ 0x145B00C 1 0>,
1519 <DCC_READ 0x1463020 1 0>,
1520 <DCC_READ 0x1469000 1 0>,
1521 <DCC_READ 0x1469004 1 0>,
1522 <DCC_READ 0x1469008 1 0>,
1523 <DCC_READ 0x146900C 1 0>,
1524 <DCC_READ 0x1469010 1 0>,
1525 <DCC_READ 0x146B000 1 0>,
1526 <DCC_READ 0x146B004 1 0>,
1527 <DCC_READ 0x146B008 1 0>,
1528 <DCC_READ 0x146B00C 1 0>,
1529 <DCC_READ 0x146B010 1 0>,
1530 <DCC_READ 0x146B014 1 0>,
1531 <DCC_READ 0x146B018 1 0>,
1532 <DCC_READ 0x146B01C 1 0>,
1533 <DCC_READ 0x146B020 1 0>,
1534 <DCC_READ 0x146C000 1 0>,
1535 <DCC_READ 0x146C004 1 0>,
1536 <DCC_READ 0x146C00C 1 0>,
1537 <DCC_READ 0x1475000 1 0>,
1538 <DCC_READ 0x1475004 1 0>,
1539 <DCC_READ 0x147500C 1 0>,
1540 <DCC_READ 0x1477000 1 0>,
1541 <DCC_READ 0x1477004 1 0>,
1542 <DCC_READ 0x147700C 1 0>,
1543 <DCC_READ 0x1478030 1 0>,
1544 <DCC_READ 0x1479000 1 0>,
1545 <DCC_READ 0x1479004 1 0>,
1546 <DCC_READ 0x147900C 1 0>,
1547 <DCC_READ 0x147A000 1 0>,
1548 <DCC_READ 0x147A004 1 0>,
1549 <DCC_READ 0x147A00C 1 0>,
1550 <DCC_READ 0x1480018 1 0>,
1551 <DCC_READ 0x1480144 1 0>,
1552 <DCC_READ 0x1481144 1 0>,
1553 <DCC_READ 0x148B004 1 0>,
1554 <DCC_READ 0x1490004 1 0>,
1555 <DCC_READ 0x1490008 1 0>,
1556 <DCC_READ 0x1490024 1 0>,
1557 <DCC_READ 0x1490028 1 0>,
1558 <DCC_READ 0x149002C 1 0>,
1559 <DCC_READ 0x1490034 1 0>,
1560 <DCC_READ 0x1495000 1 0>,
1561 <DCC_READ 0x1495004 1 0>,
1562 <DCC_READ 0x149500C 1 0>,
1563 <DCC_READ 0x14B5000 1 0>,
1564 <DCC_READ 0x14C4000 1 0>,
1565 <DCC_READ 0x14C5000 1 0>,
1566 <DCC_READ 0x14C6000 1 0>,
1567 <DCC_READ 0x14C7000 1 0>,
1568 <DCC_READ 0x440C000 1 0>,
1569 <DCC_READ 0x440C004 1 0>,
1570 <DCC_READ 0x440C008 1 0>,
1571 <DCC_READ 0x440C040 1 0>,
1572 <DCC_READ 0x440C044 1 0>,
1573 <DCC_READ 0x440C048 1 0>,
1574 <DCC_READ 0x440C04C 1 0>,
1575 <DCC_READ 0x440C050 1 0>,
1576 <DCC_READ 0x440C054 1 0>,
1577 <DCC_READ 0x440C058 1 0>,
1578 <DCC_READ 0x440C05C 1 0>,
1579 <DCC_READ 0x440C060 1 0>,
1580 <DCC_READ 0x440C068 1 0>,
1581 <DCC_READ 0x440C06C 1 0>,
1582 <DCC_READ 0x440E050 1 0>,
1583 <DCC_READ 0x440E054 1 0>,
1584 <DCC_READ 0x440E0A0 1 0>,
1585 <DCC_READ 0x440E0A4 1 0>,
1586 <DCC_READ 0x440F010 1 0>;
1587 };
1588 };
1589
1590 timer@f120000 {
1591 #address-cells = <1>;
1592 #size-cells = <1>;
1593 ranges;
1594 compatible = "arm,armv7-timer-mem";
1595 reg = <0xf120000 0x1000>;
1596 clock-frequency = <19200000>;
1597
1598 frame@f121000 {
1599 frame-number = <0>;
1600 interrupts = <0 8 0x4>,
1601 <0 7 0x4>;
1602 reg = <0xf121000 0x1000>,
1603 <0xf122000 0x1000>;
1604 };
1605
1606 frame@f123000 {
1607 frame-number = <1>;
1608 interrupts = <0 9 0x4>;
1609 reg = <0xf123000 0x1000>;
1610 status = "disabled";
1611 };
1612
1613 frame@f124000 {
1614 frame-number = <2>;
1615 interrupts = <0 10 0x4>;
1616 reg = <0xf124000 0x1000>;
1617 status = "disabled";
1618 };
1619
1620 frame@f125000 {
1621 frame-number = <3>;
1622 interrupts = <0 11 0x4>;
1623 reg = <0xf125000 0x1000>;
1624 status = "disabled";
1625 };
1626
1627 frame@f126000 {
1628 frame-number = <4>;
1629 interrupts = <0 12 0x4>;
1630 reg = <0xf126000 0x1000>;
1631 status = "disabled";
1632 };
1633
1634 frame@f127000 {
1635 frame-number = <5>;
1636 interrupts = <0 13 0x4>;
1637 reg = <0xf127000 0x1000>;
1638 status = "disabled";
1639 };
1640
1641 frame@f128000 {
1642 frame-number = <6>;
1643 interrupts = <0 14 0x4>;
1644 reg = <0xf128000 0x1000>;
1645 status = "disabled";
1646 };
1647 };
1648
1649 arm64_cpu_erp {
1650 compatible = "arm,arm64-cpu-erp";
1651 interrupt-names = "pri-dbe-irq",
1652 "sec-dbe-irq",
1653 "pri-ext-irq",
1654 "sec-ext-irq";
1655 interrupts = <0 43 4>,
1656 <0 44 4>,
1657 <0 41 4>,
1658 <0 42 4>;
1659 poll-delay-ms = <5000>;
1660 };
1661
1662 l2cache_pmu {
1663 #address-cells = <1>;
1664 #size-cells = <1>;
1665 compatible = "qcom,l2cache-pmu";
1666 ranges;
1667
1668 cluster0@f111000 {
1669 cluster-id = <0>;
1670 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1671 reg = <0xf111000 0x1000>;
1672 };
1673
1674 cluster1@f011000 {
1675 cluster-id = <1>;
1676 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1677 reg = <0xf011000 0x1000>;
1678 };
1679 };
1680
1681 qcom,msm-imem@c125000 {
1682 compatible = "qcom,msm-imem";
1683 reg = <0xc125000 0x1000>;
1684 ranges = <0x0 0xc125000 0x1000>;
1685 #address-cells = <1>;
1686 #size-cells = <1>;
1687
1688 mem_dump_table@10 {
1689 compatible = "qcom,msm-imem-mem_dump_table";
1690 reg = <0x10 0x8>;
1691 };
1692
1693 restart_reason@65c {
1694 compatible = "qcom,msm-imem-restart_reason";
1695 reg = <0x65c 0x4>;
1696 };
1697
1698 dload_type@1c {
1699 compatible = "qcom,msm-imem-dload-type";
1700 reg = <0x1c 0x4>;
1701 };
1702
1703 boot_stats@6b0 {
1704 compatible = "qcom,msm-imem-boot_stats";
1705 reg = <0x6b0 0x20>;
1706 };
1707
1708 kaslr_offset@6d0 {
1709 compatible = "qcom,msm-imem-kaslr_offset";
1710 reg = <0x6d0 0xc>;
1711 };
1712
1713 pil@94c {
1714 compatible = "qcom,msm-imem-pil";
1715 reg = <0x94c 0xc8>;
1716 };
1717
1718 diag_dload@c8 {
1719 compatible = "qcom,msm-imem-diag-dload";
1720 reg = <0xc8 0xc8>;
1721 };
1722 };
1723
1724 restart@440b000 {
1725 compatible = "qcom,pshold";
1726 reg = <0x440b000 0x4>,
1727 <0x03d3000 0x4>;
1728 reg-names = "pshold-base", "tcsr-boot-misc-detect";
1729 };
1730
1731 qcom_seecom: qseecom@61800000 {
1732 compatible = "qcom,qseecom";
1733 reg = <0x61800000 0x2100000>;
1734 reg-names = "secapp-region";
1735 memory-region = <&qseecom_mem>;
1736 qcom,hlos-num-ce-hw-instances = <1>;
1737 qcom,hlos-ce-hw-instance = <0>;
1738 qcom,qsee-ce-hw-instance = <0>;
1739 qcom,disk-encrypt-pipe-pair = <2>;
1740 qcom,support-fde;
1741 qcom,fde-key-size;
1742 qcom,appsbl-qseecom-support;
1743 qcom,commonlib64-loaded-by-uefi;
1744 qcom,msm-bus,name = "qseecom-noc";
1745 qcom,msm-bus,num-cases = <4>;
1746 qcom,msm-bus,num-paths = <1>;
1747 qcom,msm-bus,vectors-KBps =
1748 <MSM_BUS_MASTER_CRYPTO_CORE0
1749 MSM_BUS_SLAVE_FIRST 0 0>,
1750 <MSM_BUS_MASTER_CRYPTO_CORE0
1751 MSM_BUS_SLAVE_FIRST 200000 400000>,
1752 <MSM_BUS_MASTER_CRYPTO_CORE0
1753 MSM_BUS_SLAVE_FIRST 300000 800000>,
1754 <MSM_BUS_MASTER_CRYPTO_CORE0
1755 MSM_BUS_SLAVE_FIRST 400000 1000000>;
1756 clock-names =
1757 "core_clk_src", "core_clk",
1758 "iface_clk", "bus_clk";
1759 clocks =
1760 <&rpmcc QSEECOM_CE1_CLK>,
1761 <&rpmcc QSEECOM_CE1_CLK>,
1762 <&rpmcc QSEECOM_CE1_CLK>,
1763 <&rpmcc QSEECOM_CE1_CLK>;
1764 qcom,ce-opp-freq = <192000000>;
1765 qcom,qsee-reentrancy-support = <2>;
1766 };
1767
1768 qcom_smcinvoke: smcinvoke@61800000 {
1769 compatible = "qcom,smcinvoke";
1770 reg = <0x61800000 0x2100000>;
1771 reg-names = "secapp-region";
1772 };
1773
1774 qcom_rng: qrng@1b53000 {
1775 compatible = "qcom,msm-rng";
1776 reg = <0x1b53000 0x1000>;
1777 qcom,msm-rng-iface-clk;
1778 qcom,no-qrng-config;
1779 qcom,msm-bus,name = "msm-rng-noc";
1780 qcom,msm-bus,num-cases = <2>;
1781 qcom,msm-bus,num-paths = <1>;
1782 qcom,msm-bus,vectors-KBps =
1783 <MSM_BUS_MASTER_AMPSS_M0
1784 MSM_BUS_SLAVE_PRNG 0 0>, /* No vote */
1785 <MSM_BUS_MASTER_AMPSS_M0
1786 MSM_BUS_SLAVE_PRNG 0 300000>; /* 75 MHz */
1787 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1788 clock-names = "iface_clk";
1789 };
1790
1791 qcom_tzlog: tz-log@c125720 {
1792 compatible = "qcom,tz-log";
1793 reg = <0xc125720 0x3000>;
1794 qcom,hyplog-enabled;
1795 hyplog-address-offset = <0x410>;
1796 hyplog-size-offset = <0x414>;
1797 };
1798
1799 qcom_cedev: qcedev@1b20000 {
1800 compatible = "qcom,qcedev";
1801 reg = <0x1b20000 0x20000>,
1802 <0x1b04000 0x24000>;
1803 reg-names = "crypto-base","crypto-bam-base";
1804 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
1805 qcom,bam-pipe-pair = <3>;
1806 qcom,ce-hw-instance = <0>;
1807 qcom,ce-device = <0>;
1808 qcom,ce-hw-shared;
1809 qcom,bam-ee = <0>;
1810 qcom,msm-bus,name = "qcedev-noc";
1811 qcom,msm-bus,num-cases = <2>;
1812 qcom,msm-bus,num-paths = <1>;
1813 qcom,msm-bus,vectors-KBps =
1814 <MSM_BUS_MASTER_CRYPTO_CORE0
1815 MSM_BUS_SLAVE_FIRST 0 0>,
1816 <MSM_BUS_MASTER_CRYPTO_CORE0
1817 MSM_BUS_SLAVE_FIRST 393600 393600>;
1818 clock-names =
1819 "core_clk_src", "core_clk",
1820 "iface_clk", "bus_clk";
1821 clocks =
1822 <&rpmcc QCEDEV_CE1_CLK>,
1823 <&rpmcc QCEDEV_CE1_CLK>,
1824 <&rpmcc QCEDEV_CE1_CLK>,
1825 <&rpmcc QCEDEV_CE1_CLK>;
1826 qcom,ce-opp-freq = <192000000>;
1827 qcom,smmu-s1-enable;
1828 iommus = <&apps_smmu 0x0086 0x0011>,
1829 <&apps_smmu 0x0096 0x0011>;
1830 qcom,iommu-dma = "atomic";
1831
1832 qcom_cedev_ns_cb {
1833 compatible = "qcom,qcedev,context-bank";
1834 label = "ns_context";
1835 iommus = <&apps_smmu 0x92 0>,
1836 <&apps_smmu 0x98 0x1>,
1837 <&apps_smmu 0x9F 0>;
1838 qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
1839 };
1840
1841 qcom_cedev_s_cb {
1842 compatible = "qcom,qcedev,context-bank";
1843 label = "secure_context";
1844 iommus = <&apps_smmu 0x93 0>,
1845 <&apps_smmu 0x9C 0x1>,
1846 <&apps_smmu 0x9E 0>;
1847 qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
1848 qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
1849 qcom,secure-context-bank;
1850 };
1851 };
1852
1853 qcom_crypto: qcrypto@1b20000 {
1854 compatible = "qcom,qcrypto";
1855 reg = <0x1b20000 0x20000>,
1856 <0x1b04000 0x24000>;
1857 reg-names = "crypto-base","crypto-bam-base";
1858 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
1859 qcom,bam-pipe-pair = <2>;
1860 qcom,ce-hw-instance = <0>;
1861 qcom,ce-device = <0>;
1862 qcom,bam-ee = <0>;
1863 qcom,ce-hw-shared;
1864 qcom,clk-mgmt-sus-res;
1865 qcom,msm-bus,name = "qcrypto-noc";
1866 qcom,msm-bus,num-cases = <2>;
1867 qcom,msm-bus,num-paths = <1>;
1868 qcom,msm-bus,vectors-KBps =
1869 <MSM_BUS_MASTER_CRYPTO_CORE0
1870 MSM_BUS_SLAVE_FIRST
1871 0 0>,
1872 <MSM_BUS_MASTER_CRYPTO_CORE0
1873 MSM_BUS_SLAVE_FIRST
1874 393600 393600>;
1875 clock-names =
1876 "core_clk_src", "core_clk",
1877 "iface_clk", "bus_clk";
1878 clocks =
1879 <&rpmcc QCRYPTO_CE1_CLK>,
1880 <&rpmcc QCRYPTO_CE1_CLK>,
1881 <&rpmcc QCRYPTO_CE1_CLK>,
1882 <&rpmcc QCRYPTO_CE1_CLK>;
1883 qcom,use-sw-aes-cbc-ecb-ctr-algo;
1884 qcom,use-sw-aes-xts-algo;
1885 qcom,use-sw-aes-ccm-algo;
1886 qcom,use-sw-ahash-algo;
1887 qcom,use-sw-aead-algo;
1888 qcom,use-sw-hmac-algo;
1889 qcom,smmu-s1-enable;
1890 iommus = <&apps_smmu 0x0084 0x0011>,
1891 <&apps_smmu 0x0094 0x0011>;
1892 qcom,iommu-dma = "atomic";
1893 };
1894
1895 qcom,mpm2-sleep-counter@4403000 {
1896 compatible = "qcom,mpm2-sleep-counter";
1897 reg = <0x4403000 0x1000>;
1898 clock-frequency = <32768>;
1899 };
1900
1901 qcom,msm-rtb {
1902 compatible = "qcom,msm-rtb";
1903 qcom,rtb-size = <0x100000>;
1904 };
1905
1906 cpu_pmu: cpu-pmu {
1907 compatible = "arm,armv8-pmuv3";
1908 qcom,irq-is-percpu;
1909 interrupts = <1 6 4>;
1910 };
1911
1912 eud: qcom,msm-eud@1610000 {
1913 compatible = "qcom,msm-eud";
1914 interrupt-names = "eud_irq";
1915 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
1916 reg = <0x1610000 0x2000>,
1917 <0x1612000 0x1000>,
1918 <0x3E5018 0x4>;
1919 reg-names = "eud_base", "eud_mode_mgr2",
1920 "eud_tcsr_check_reg";
1921 qcom,secure-eud-en;
1922 qcom,eud-tcsr-check-enable;
1923 qcom,eud-clock-vote-req;
1924 clocks = <&gcc GCC_AHB2PHY_USB_CLK>;
1925 clock-names = "eud_ahb2phy_clk";
1926 status = "ok";
1927 };
1928
1929 qcom,msm-gladiator-v2@f100000 {
1930 compatible = "qcom,msm-gladiator-v2";
1931 reg = <0xf100000 0xdc00>;
1932 reg-names = "gladiator_base";
1933 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1934 clock-names = "atb_clk";
1935 clocks = <&rpmcc RPM_QDSS_CLK>;
1936 };
1937
1938 wdog: qcom,wdt@f017000 {
1939 compatible = "qcom,msm-watchdog";
1940 reg = <0xf017000 0x1000>;
1941 reg-names = "wdt-base";
1942 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
1943 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1944 qcom,bark-time = <11000>;
1945 qcom,pet-time = <9360>;
1946 qcom,ipi-ping;
1947 qcom,wakeup-enable;
1948 };
1949
1950 rpm_bus: qcom,rpm-smd {
1951 compatible = "qcom,rpm-smd";
1952 rpm-channel-name = "rpm_requests";
1953 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
1954 rpm-channel-type = <15>; /* SMD_APPS_RPM */
1955 };
1956
1957 qcom,chd_silver {
1958 compatible = "qcom,core-hang-detect";
1959 label = "silver";
1960 qcom,threshold-arr = <0x0f1880b0 0x0f1980b0
1961 0x0f1a80b0 0x0f1b80b0>;
1962 qcom,config-arr = <0x0f1880b8 0x0f1980b8
1963 0x0f1a80b8 0x0f1b80b8>;
1964 };
1965
1966 qcom,chd_gold {
1967 compatible = "qcom,core-hang-detect";
1968 label = "gold";
1969 qcom,threshold-arr = <0x0f0880b0 0x0f0980b0
1970 0x0f0a80b0 0x0f0b80b0>;
1971 qcom,config-arr = <0x0f0880b8 0x0f0980b8
1972 0x0f0a80b8 0x0f0b80b8>;
1973 };
1974
1975 qcom,ghd {
1976 compatible = "qcom,gladiator-hang-detect";
1977 qcom,threshold-arr = <0x0f1d141c 0x0f1d1420
1978 0x0f1d1424 0x0f1d1428
1979 0x0f1d142c 0x0f1d1430>;
1980 qcom,config-reg = <0x0f1d1434>;
1981 };
1982
1983 qcom,lpass@ab00000 {
1984 compatible = "qcom,pil-tz-generic";
1985 reg = <0xab00000 0x00100>;
1986
1987 vdd_lpi_cx-supply = <&L3A_LEVEL>;
1988 qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
1989 qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
1990 vdd_lpi_mx-supply = <&L2A_LEVEL>;
1991 qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
1992
1993 clocks = <&rpmcc CXO_SMD_PIL_LPASS_CLK>;
1994 clock-names = "xo";
1995 qcom,proxy-clock-names = "xo";
1996 qcom,mas-crypto = <&mas_crypto_c0>;
1997
1998 qcom,pas-id = <1>;
1999 qcom,proxy-timeout-ms = <10000>;
2000 qcom,smem-id = <423>;
2001 qcom,minidump-id = <5>;
2002 qcom,sysmon-id = <1>;
2003 qcom,ssctl-instance-id = <0x14>;
2004 qcom,firmware-name = "adsp";
2005 memory-region = <&pil_adsp_mem>;
2006 qcom,complete-ramdump;
2007 qcom,minidump-as-elf32;
2008
2009 /* Inputs from lpass */
2010 interrupts-extended = <&intc 0 282 1>,
2011 <&adsp_smp2p_in 0 0>,
2012 <&adsp_smp2p_in 2 0>,
2013 <&adsp_smp2p_in 1 0>,
2014 <&adsp_smp2p_in 3 0>;
2015
2016 interrupt-names = "qcom,wdog",
2017 "qcom,err-fatal",
2018 "qcom,proxy-unvote",
2019 "qcom,err-ready",
2020 "qcom,stop-ack";
2021
2022 /* Outputs to lpass */
2023 qcom,smem-states = <&adsp_smp2p_out 0>;
2024 qcom,smem-state-names = "qcom,force-stop";
2025 };
2026
2027 qcom,turing@b300000 {
2028 compatible = "qcom,pil-tz-generic";
2029 reg = <0xb300000 0x100000>;
2030
2031 vdd_cx-supply = <&VDD_CX_LEVEL>;
2032 qcom,proxy-reg-names = "vdd_cx";
2033 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
2034
2035 clocks = <&rpmcc CXO_SMD_PIL_CDSP_CLK>;
2036 clock-names = "xo";
2037 qcom,proxy-clock-names = "xo";
2038 qcom,mas-crypto = <&mas_crypto_c0>;
2039
2040 qcom,pas-id = <18>;
2041 qcom,proxy-timeout-ms = <10000>;
2042 qcom,smem-id = <601>;
2043 qcom,minidump-id = <7>;
2044 qcom,sysmon-id = <7>;
2045 qcom,ssctl-instance-id = <0x17>;
2046 qcom,firmware-name = "cdsp";
2047 memory-region = <&pil_cdsp_mem>;
2048 qcom,complete-ramdump;
2049 qcom,minidump-as-elf32;
2050
2051 /* Inputs from turing */
2052 interrupts-extended = <&intc 0 265 1>,
2053 <&cdsp_smp2p_in 0 0>,
2054 <&cdsp_smp2p_in 2 0>,
2055 <&cdsp_smp2p_in 1 0>,
2056 <&cdsp_smp2p_in 3 0>;
2057
2058 interrupt-names = "qcom,wdog",
2059 "qcom,err-fatal",
2060 "qcom,proxy-unvote",
2061 "qcom,err-ready",
2062 "qcom,stop-ack";
2063
2064 /* Outputs to turing */
2065 qcom,smem-states = <&cdsp_smp2p_out 0>;
2066 qcom,smem-state-names = "qcom,force-stop";
2067 };
2068
2069 mem_dump {
2070 compatible = "qcom,mem-dump";
2071 memory-region = <&dump_mem>;
2072
2073 c0_context {
2074 qcom,dump-size = <0x800>;
2075 qcom,dump-id = <0x0>;
2076 };
2077
2078 c1_context {
2079 qcom,dump-size = <0x800>;
2080 qcom,dump-id = <0x1>;
2081 };
2082
2083 c2_context {
2084 qcom,dump-size = <0x800>;
2085 qcom,dump-id = <0x2>;
2086 };
2087
2088 c3_context {
2089 qcom,dump-size = <0x800>;
2090 qcom,dump-id = <0x3>;
2091 };
2092
2093 c100_context {
2094 qcom,dump-size = <0x800>;
2095 qcom,dump-id = <0x4>;
2096 };
2097
2098 c101_context {
2099 qcom,dump-size = <0x800>;
2100 qcom,dump-id = <0x5>;
2101 };
2102
2103 c102_context {
2104 qcom,dump-size = <0x800>;
2105 qcom,dump-id = <0x6>;
2106 };
2107
2108 c103_context {
2109 qcom,dump-size = <0x800>;
2110 qcom,dump-id = <0x7>;
2111 };
2112
2113 c_scandump {
2114 qcom,dump-size = <0x40000>;
2115 qcom,dump-id = <0xeb>;
2116 };
2117
2118 l1_icache0 {
2119 qcom,dump-size = <0x8900>;
2120 qcom,dump-id = <0x60>;
2121 };
2122
2123 l1_icache1 {
2124 qcom,dump-size = <0x8900>;
2125 qcom,dump-id = <0x61>;
2126 };
2127
2128 l1_icache2 {
2129 qcom,dump-size = <0x8900>;
2130 qcom,dump-id = <0x62>;
2131 };
2132
2133 l1_icache3 {
2134 qcom,dump-size = <0x8900>;
2135 qcom,dump-id = <0x63>;
2136 };
2137
2138 l1_icache100 {
2139 qcom,dump-size = <0x11100>;
2140 qcom,dump-id = <0x64>;
2141 };
2142
2143 l1_icache101 {
2144 qcom,dump-size = <0x11100>;
2145 qcom,dump-id = <0x65>;
2146 };
2147
2148 l1_icache102 {
2149 qcom,dump-size = <0x11100>;
2150 qcom,dump-id = <0x66>;
2151 };
2152
2153 l1_icache103 {
2154 qcom,dump-size = <0x11100>;
2155 qcom,dump-id = <0x67>;
2156 };
2157
2158 l1_dcache0 {
2159 qcom,dump-size = <0x9100>;
2160 qcom,dump-id = <0x80>;
2161 };
2162
2163 l1_dcache1 {
2164 qcom,dump-size = <0x9100>;
2165 qcom,dump-id = <0x81>;
2166 };
2167
2168 l1_dcache2 {
2169 qcom,dump-size = <0x9100>;
2170 qcom,dump-id = <0x82>;
2171 };
2172
2173 l1_dcache3 {
2174 qcom,dump-size = <0x9100>;
2175 qcom,dump-id = <0x83>;
2176 };
2177
2178 l1_dcache100 {
2179 qcom,dump-size = <0x12100>;
2180 qcom,dump-id = <0x84>;
2181 };
2182
2183 l1_dcache101 {
2184 qcom,dump-size = <0x12100>;
2185 qcom,dump-id = <0x85>;
2186 };
2187
2188 l1_dcache102 {
2189 qcom,dump-size = <0x12100>;
2190 qcom,dump-id = <0x86>;
2191 };
2192
2193 l1_dcache103 {
2194 qcom,dump-size = <0x12100>;
2195 qcom,dump-id = <0x87>;
2196 };
2197
2198 l2_tlb0 {
2199 qcom,dump-size = <0x2100>;
2200 qcom,dump-id = <0x120>;
2201 };
2202
2203 l2_tlb1 {
2204 qcom,dump-size = <0x2100>;
2205 qcom,dump-id = <0x121>;
2206 };
2207
2208 l2_tlb2 {
2209 qcom,dump-size = <0x2100>;
2210 qcom,dump-id = <0x122>;
2211 };
2212
2213 l2_tlb3 {
2214 qcom,dump-size = <0x2100>;
2215 qcom,dump-id = <0x123>;
2216 };
2217
2218 l2_tlb100 {
2219 qcom,dump-size = <0x4900>;
2220 qcom,dump-id = <0x124>;
2221 };
2222
2223 l2_tlb101 {
2224 qcom,dump-size = <0x4900>;
2225 qcom,dump-id = <0x125>;
2226 };
2227
2228 l2_tlb102 {
2229 qcom,dump-size = <0x4900>;
2230 qcom,dump-id = <0x126>;
2231 };
2232
2233 l2_tlb103 {
2234 qcom,dump-size = <0x4900>;
2235 qcom,dump-id = <0x127>;
2236 };
2237
2238 rpm_sw {
2239 qcom,dump-size = <0x28000>;
2240 qcom,dump-id = <0xea>;
2241 };
2242
2243 pmic {
2244 qcom,dump-size = <0x40000>;
2245 qcom,dump-id = <0xe4>;
2246 };
2247
2248 fcm {
2249 qcom,dump-size = <0x8400>;
2250 qcom,dump-id = <0xee>;
2251 };
2252
2253 tmc_etf {
2254 qcom,dump-size = <0x8000>;
2255 qcom,dump-id = <0xf0>;
2256 };
2257
2258 etr_reg {
2259 qcom,dump-size = <0x1000>;
2260 qcom,dump-id = <0x100>;
2261 };
2262
2263 etf_reg {
2264 qcom,dump-size = <0x1000>;
2265 qcom,dump-id = <0x101>;
2266 };
2267
2268 misc_data {
2269 qcom,dump-size = <0x1000>;
2270 qcom,dump-id = <0xe8>;
2271 };
2272 };
2273
2274 sdhc_1: sdhci@4744000 {
2275 compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";
2276 reg = <0x4744000 0x1000>, <0x4745000 0x1000>,
2277 <0x4748000 0x8000>;
2278 reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";
2279
2280 interrupts-extended = <&intc GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
2281 <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
2282 <&tlmm 19 IRQ_TYPE_EDGE_RISING>;
2283 interrupt-names = "hc_irq", "pwr_irq", "tb_trig_irq";
2284
2285 qcom,bus-width = <8>;
2286 qcom,large-address-bus;
2287
2288 qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
2289 192000000 384000000>;
2290 qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
2291
2292 qcom,devfreq,freq-table = <50000000 200000000>;
2293
2294 qcom,scaling-lower-bus-speed-mode = "DDR52";
2295
2296 qcom,msm-bus,name = "sdhc1";
2297 qcom,msm-bus,num-cases = <9>;
2298 qcom,msm-bus,num-paths = <2>;
2299 qcom,msm-bus,vectors-KBps =
2300 /* No vote */
2301 <78 512 0 0>, <1 606 0 0>,
2302 /* 400 KB/s*/
2303 <78 512 1046 1600>,
2304 <1 606 1600 1600>,
2305 /* 20 MB/s */
2306 <78 512 20480 80000>,
2307 <1 606 80000 80000>,
2308 /* 25 MB/s */
2309 <78 512 25600 250000>,
2310 <1 606 50000 133320>,
2311 /* 50 MB/s */
2312 <78 512 51200 250000>,
2313 <1 606 65000 133320>,
2314 /* 100 MB/s */
2315 <78 512 102400 250000>,
2316 <1 606 65000 133320>,
2317 /* 200 MB/s */
2318 <78 512 204800 800000>,
2319 <1 606 200000 300000>,
2320 /* 400 MB/s */
2321 <78 512 204800 800000>,
2322 <1 606 200000 300000>,
2323 /* Max. bandwidth */
2324 <78 512 1338562 4096000>,
2325 <1 606 1338562 4096000>;
2326 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
2327 100750000 200000000 400000000 4294967295>;
2328
2329 /* PM QoS */
2330 qcom,pm-qos-irq-type = "affine_irq";
2331 qcom,pm-qos-irq-latency = <26 26>;
2332 qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
2333 qcom,pm-qos-cmdq-latency-us = <26 26>, <26 26>;
2334 qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>;
2335
2336 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2337 <&gcc GCC_SDCC1_APPS_CLK>,
2338 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
2339 clock-names = "iface_clk", "core_clk", "ice_core_clk";
2340
2341 qcom,ice-clk-rates = <300000000 100000000>;
2342
2343 /* Add support for gcc hw reset */
2344 resets = <&gcc GCC_SDCC1_BCR>;
2345 reset-names = "core_reset";
2346
2347 /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
2348 qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>;
2349 qcom,nonremovable;
2350 status = "disabled";
2351 };
2352
2353 sdhc_2: sdhci@4784000 {
2354 compatible = "qcom,sdhci-msm-v5";
2355 reg = <0x4784000 0x1000>;
2356 reg-names = "hc_mem";
2357
2358 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
2359 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
2360 interrupt-names = "hc_irq", "pwr_irq";
2361
2362 qcom,bus-width = <4>;
2363 qcom,large-address-bus;
2364
2365 qcom,clk-rates = <400000 20000000 25000000
2366 50000000 100000000 202000000>;
2367 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
2368 "SDR104";
2369
2370 qcom,devfreq,freq-table = <50000000 202000000>;
2371
2372 qcom,msm-bus,name = "sdhc2";
2373 qcom,msm-bus,num-cases = <8>;
2374 qcom,msm-bus,num-paths = <2>;
2375 qcom,msm-bus,vectors-KBps =
2376 /* No vote */
2377 <81 512 0 0>, <1 608 0 0>,
2378 /* 400 KB/s*/
2379 <81 512 1046 3200>,
2380 <1 608 1600 1600>,
2381 /* 20 MB/s */
2382 <81 512 52286 250000>,
2383 <1 608 80000 133320>,
2384 /* 25 MB/s */
2385 <81 512 65360 250000>,
2386 <1 608 100000 133320>,
2387 /* 50 MB/s */
2388 <81 512 130718 250000>,
2389 <1 608 133320 133320>,
2390 /* 100 MB/s */
2391 <81 512 261438 250000>,
2392 <1 608 150000 133320>,
2393 /* 200 MB/s */
2394 <81 512 261438 800000>,
2395 <1 608 300000 300000>,
2396 /* Max. bandwidth */
2397 <81 512 1338562 4096000>,
2398 <1 608 1338562 4096000>;
2399 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
2400 100750000 200000000 4294967295>;
2401
2402 /* PM QoS */
2403 qcom,pm-qos-irq-type = "affine_irq";
2404 qcom,pm-qos-irq-latency = <26 26>;
2405 qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
2406 qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>;
2407
2408
2409 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2410 <&gcc GCC_SDCC2_APPS_CLK>;
2411 clock-names = "iface_clk", "core_clk";
2412
2413 /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
2414 qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
2415 qcom,vbias-skip-wa;
2416
2417 status = "disabled";
2418 };
2419
2420 ufsphy_mem: ufsphy_mem@4807000 {
2421 reg = <0x4807000 0xe00>; /* PHY regs */
2422 reg-names = "phy_mem";
2423 #phy-cells = <0>;
2424
2425 lanes-per-direction = <2>;
2426
2427 clock-names = "ref_clk_src",
2428 "ref_clk",
2429 "ref_aux_clk";
2430 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2431 <&gcc GCC_UFS_CLKREF_CLK>,
2432 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2433
2434 status = "disabled";
2435 };
2436
2437 ufshc_mem: ufshc@4804000 {
2438 compatible = "qcom,ufshc";
2439 reg = <0x4804000 0x3000>, <0x4810000 0x8000>;
2440 reg-names = "ufs_mem", "ufs_ice";
2441 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
2442 phys = <&ufsphy_mem>;
2443 phy-names = "ufsphy";
2444
2445 lanes-per-direction = <2>;
2446 dev-ref-clk-freq = <0>; /* 19.2 MHz */
2447 spm-level = <5>;
2448
2449 clock-names =
2450 "core_clk",
2451 "bus_aggr_clk",
2452 "iface_clk",
2453 "core_clk_unipro",
2454 "core_clk_ice",
2455 "ref_clk",
2456 "tx_lane0_sync_clk",
2457 "rx_lane0_sync_clk",
2458 "rx_lane1_sync_clk";
2459 clocks =
2460 <&gcc GCC_UFS_PHY_AXI_CLK>,
2461 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
2462 <&gcc GCC_UFS_PHY_AHB_CLK>,
2463 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2464 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
2465 <&rpmcc RPM_SMD_XO_CLK_SRC>,
2466 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2467 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2468 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2469 freq-table-hz =
2470 <50000000 200000000>,
2471 <0 0>,
2472 <0 0>,
2473 <37500000 150000000>,
2474 <75000000 300000000>,
2475 <0 0>,
2476 <0 0>,
2477 <0 0>,
2478 <0 0>;
2479
2480 qcom,msm-bus,name = "ufshc_mem";
2481 qcom,msm-bus,num-cases = <22>;
2482 qcom,msm-bus,num-paths = <2>;
2483 qcom,msm-bus,vectors-KBps =
2484 /*
2485 * During HS G3 UFS runs at nominal voltage corner, vote
2486 * higher bandwidth to push other buses in the data path
2487 * to run at nominal to achieve max throughput.
2488 * 4GBps pushes BIMC to run at nominal.
2489 * 200MBps pushes CNOC to run at nominal.
2490 * Vote for half of this bandwidth for HS G3 1-lane.
2491 * For max bandwidth, vote high enough to push the buses
2492 * to run in turbo voltage corner.
2493 */
2494 <123 512 0 0>, <1 757 0 0>, /* No vote */
2495 <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
2496 <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
2497 <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
2498 <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
2499 <123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */
2500 <123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */
2501 <123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */
2502 <123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */
2503 <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
2504 <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
2505 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
2506 <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */
2507 <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */
2508 <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */
2509 <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
2510 <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
2511 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
2512 <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */
2513 <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */
2514 /* As UFS working in HS G3 RB L2 mode, aggregated
2515 * bandwidth (AB) should take care of providing
2516 * optimum throughput requested. However, as tested,
2517 * in order to scale up CNOC clock, instantaneous
2518 * bindwidth (IB) needs to be given a proper value too.
2519 */
2520 <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */
2521 <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
2522
2523 qcom,bus-vector-names = "MIN",
2524 "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
2525 "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
2526 "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
2527 "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
2528 "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
2529 "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
2530 "MAX";
2531
2532 /* PM QoS */
2533 qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
2534 qcom,pm-qos-cpu-group-latency-us = <26 26>;
2535 qcom,pm-qos-default-cpu = <0>;
2536
2537 pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
2538 pinctrl-0 = <&ufs_dev_reset_assert>;
2539 pinctrl-1 = <&ufs_dev_reset_deassert>;
2540
2541 resets = <&gcc GCC_UFS_PHY_BCR>;
2542 reset-names = "core_reset";
2543 non-removable;
2544
2545 status = "disabled";
2546 };
2547
2548 thermal_zones: thermal-zones {};
2549
2550 tsens0:tsens@c222000 {
2551 compatible = "qcom,tsens24xx";
2552 reg = <0x04410000 0x8>,
2553 <0x04411000 0x1ff>;
2554 reg-names = "tsens_srot_physical",
2555 "tsens_tm_physical";
2556 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
2557 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
2558 interrupt-names = "tsens-upper-lower", "tsens-critical";
2559 tsens-reinit-wa;
2560 #thermal-sensor-cells = <1>;
2561 };
2562
2563 clocks {
2564 xo_board: xo_board {
2565 compatible = "fixed-clock";
2566 clock-frequency = <19200000>;
2567 clock-output-names = "xo_board";
2568 #clock-cells = <0>;
2569 };
2570
2571 sleep_clk: sleep_clk {
2572 compatible = "fixed-clock";
2573 clock-frequency = <32764>;
2574 clock-output-names = "sleep_clk";
2575 #clock-cells = <0>;
2576 };
2577
2578 usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
2579 compatible = "fixed-clock";
2580 clock-frequency = <1000>;
2581 clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
2582 #clock-cells = <0>;
2583 };
2584 };
2585
2586 rpmcc: clock-controller {
2587 compatible = "qcom,rpmcc-bengal";
2588 #clock-cells = <1>;
2589 };
2590
2591 qcom,rmtfs_sharedmem@0 {
2592 compatible = "qcom,sharedmem-uio";
2593 reg = <0x0 0x200000>;
2594 reg-names = "rmtfs";
2595 qcom,client-id = <0x00000001>;
2596 qcom,guard-memory;
2597 qcom,vm-nav-path;
2598 };
2599
2600 gcc: clock-controller@1400000 {
2601 compatible = "qcom,khaje-gcc", "syscon";
2602 reg = <0x1400000 0x1f0000>;
2603 reg-names = "cc_base";
2604 vdd_cx-supply = <&VDD_CX_LEVEL>;
2605 vdd_mx-supply = <&VDD_MX_LEVEL>;
2606 #clock-cells = <1>;
2607 #reset-cells = <1>;
2608 };
2609
2610 dispcc: clock-controller@5f00000 {
2611 compatible = "qcom,khaje-dispcc", "syscon";
2612 reg = <0x05f00000 0x20000>;
2613 reg-names = "cc_base";
2614 clock-names = "cfg_ahb_clk";
2615 clocks = <&gcc GCC_DISP_AHB_CLK>;
2616 vdd_cx-supply = <&VDD_CX_LEVEL>;
2617 #clock-cells = <1>;
2618 #reset-cells = <1>;
2619 };
2620
2621 gpucc: clock-controller@5990000 {
2622 compatible = "qcom,khaje-gpucc", "syscon";
2623 reg = <0x5990000 0x9000>;
2624 reg-names = "cc_base";
2625 vdd_cx-supply = <&VDD_CX_LEVEL>;
2626 vdd_mx-supply = <&VDD_MX_LEVEL>;
2627 qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;
2628 #clock-cells = <1>;
2629 #reset-cells = <1>;
2630 };
2631
2632 mccc_debug: syscon@447d200 {
2633 compatible = "syscon";
2634 reg = <0x447d200 0x100>;
2635 };
2636
2637 cpucc_debug: syscon@f11101c {
2638 compatible = "syscon";
2639 reg = <0xf11101c 0x4>;
2640 };
2641
2642 debugcc: clock-controller@0 {
2643 compatible = "qcom,khaje-debugcc";
2644 qcom,gcc = <&gcc>;
2645 qcom,dispcc = <&dispcc>;
2646 qcom,gpucc = <&gpucc>;
2647 qcom,mccc = <&mccc_debug>;
2648 qcom,cpucc = <&cpucc_debug>;
2649 clock-names = "xo_clk_src";
2650 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2651 #clock-cells = <1>;
2652 };
2653
2654 cpufreq_hw: qcom,cpufreq-hw {
2655 compatible = "qcom,cpufreq-hw";
2656 reg = <0xf521000 0x1000>, <0xf523000 0x1000>;
2657 reg-names = "freq-domain0", "freq-domain1";
2658 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
2659 clock-names = "xo", "alternate";
2660 qcom,no-accumulative-counter;
2661 qcom,max-lut-entries = <12>;
2662 #freq-domain-cells = <2>;
2663 };
2664
2665 qcom,cpufreq-hw-debug@0f521000 {
2666 compatible = "qcom,cpufreq-hw-debug";
2667 reg = <0x0f521000 0x800>;
2668 reg-names = "domain-top";
2669 qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
2670 };
2671
2672 tcsr_mutex_block: syscon@00340000 {
2673 compatible = "syscon";
2674 reg = <0x340000 0x20000>;
2675 };
2676
2677 tcsr_mutex: hwlock {
2678 compatible = "qcom,tcsr-mutex";
2679 syscon = <&tcsr_mutex_block 0 0x1000>;
2680 #hwlock-cells = <1>;
2681 };
2682
2683 smem: qcom,smem {
2684 compatible = "qcom,smem";
2685 memory-region = <&smem_mem>;
2686 hwlocks = <&tcsr_mutex 3>;
2687 };
2688
2689 rpm_msg_ram: memory@045f0000 {
2690 compatible = "qcom,rpm-msg-ram";
2691 reg = <0x45f0000 0x7000>;
2692 };
2693
2694 apcs_glb: mailbox@0f111000 {
2695 compatible = "qcom,bengal-apcs-hmss-global";
2696 reg = <0xF111000 0x1000>;
2697
2698 #mbox-cells = <1>;
2699 };
2700
2701 qcom,msm-cdsp-loader {
2702 compatible = "qcom,cdsp-loader";
2703 qcom,proc-img-to-load = "cdsp";
2704 };
2705
2706 qcom,msm-adsprpc-mem {
2707 compatible = "qcom,msm-adsprpc-mem-region";
2708 memory-region = <&adsp_mem>;
2709 restrict-access;
2710 };
2711
2712 qcom,msm_fastrpc {
2713 compatible = "qcom,msm-fastrpc-compute";
2714 qcom,rpc-latency-us = <611>;
2715 qcom,adsp-remoteheap-vmid = <22 37>;
2716 qcom,fastrpc-adsp-audio-pdr;
2717 qcom,fastrpc-adsp-sensors-pdr;
2718
2719 qcom,msm_fastrpc_compute_cb1 {
2720 compatible = "qcom,msm-fastrpc-compute-cb";
2721 label = "cdsprpc-smd";
2722 iommus = <&apps_smmu 0x0C01 0x0>;
2723 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
2724 qcom,iommu-faults = "stall-disable", "HUPCF";
2725 };
2726
2727 qcom,msm_fastrpc_compute_cb2 {
2728 compatible = "qcom,msm-fastrpc-compute-cb";
2729 label = "cdsprpc-smd";
2730 iommus = <&apps_smmu 0x0C02 0x0>;
2731 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
2732 qcom,iommu-faults = "stall-disable", "HUPCF";
2733 };
2734
2735 qcom,msm_fastrpc_compute_cb3 {
2736 compatible = "qcom,msm-fastrpc-compute-cb";
2737 label = "cdsprpc-smd";
2738 iommus = <&apps_smmu 0x0C03 0x0>;
2739 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
2740 qcom,iommu-faults = "stall-disable", "HUPCF";
2741 };
2742
2743 qcom,msm_fastrpc_compute_cb4 {
2744 compatible = "qcom,msm-fastrpc-compute-cb";
2745 label = "cdsprpc-smd";
2746 iommus = <&apps_smmu 0x0C04 0x0>;
2747 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
2748 qcom,iommu-faults = "stall-disable", "HUPCF";
2749 };
2750
2751 qcom,msm_fastrpc_compute_cb5 {
2752 compatible = "qcom,msm-fastrpc-compute-cb";
2753 label = "cdsprpc-smd";
2754 iommus = <&apps_smmu 0x0C05 0x0>;
2755 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
2756 qcom,iommu-faults = "stall-disable", "HUPCF";
2757 };
2758
2759 qcom,msm_fastrpc_compute_cb6 {
2760 compatible = "qcom,msm-fastrpc-compute-cb";
2761 label = "cdsprpc-smd";
2762 iommus = <&apps_smmu 0x0C06 0x0>;
2763 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
2764 qcom,iommu-faults = "stall-disable", "HUPCF";
2765 };
2766
2767 qcom,msm_fastrpc_compute_cb9 {
2768 compatible = "qcom,msm-fastrpc-compute-cb";
2769 label = "cdsprpc-smd";
2770 qcom,secure-context-bank;
2771 iommus = <&apps_smmu 0x0C09 0x0>;
2772 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
2773 qcom,iommu-faults = "stall-disable", "HUPCF";
2774 };
2775
2776 qcom,msm_fastrpc_compute_cb10 {
2777 compatible = "qcom,msm-fastrpc-compute-cb";
2778 label = "adsprpc-smd";
2779 iommus = <&apps_smmu 0x01C3 0x0>;
2780 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
2781 qcom,iommu-faults = "stall-disable", "HUPCF";
2782 };
2783
2784 qcom,msm_fastrpc_compute_cb11 {
2785 compatible = "qcom,msm-fastrpc-compute-cb";
2786 label = "adsprpc-smd";
2787 iommus = <&apps_smmu 0x01C4 0x0>;
2788 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
2789 qcom,iommu-faults = "stall-disable", "HUPCF";
2790 };
2791
2792 qcom,msm_fastrpc_compute_cb12 {
2793 compatible = "qcom,msm-fastrpc-compute-cb";
2794 label = "adsprpc-smd";
2795 iommus = <&apps_smmu 0x01C5 0x0>;
2796 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
2797 qcom,iommu-faults = "stall-disable", "HUPCF";
2798 };
2799
2800 qcom,msm_fastrpc_compute_cb13 {
2801 compatible = "qcom,msm-fastrpc-compute-cb";
2802 label = "adsprpc-smd";
2803 iommus = <&apps_smmu 0x01C6 0x0>;
2804 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
2805 qcom,iommu-faults = "stall-disable", "HUPCF";
2806 };
2807
2808 qcom,msm_fastrpc_compute_cb14 {
2809 compatible = "qcom,msm-fastrpc-compute-cb";
2810 label = "adsprpc-smd";
2811 iommus = <&apps_smmu 0x01C7 0x0>;
2812 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
2813 qcom,iommu-faults = "stall-disable", "HUPCF";
2814 };
2815
2816 };
2817
2818 rpm-glink {
2819 compatible = "qcom,glink-rpm";
2820 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
2821 qcom,rpm-msg-ram = <&rpm_msg_ram>;
2822 mboxes = <&apcs_glb 0>;
2823
2824 qcom,rpm_glink_ssr {
2825 qcom,glink-channels = "glink_ssr";
2826 qcom,notify-edges = <&glink_modem>,
2827 <&glink_adsp>,
2828 <&glink_cdsp>;
2829 };
2830
2831 };
2832
2833 qcom,glink {
2834 compatible = "qcom,glink";
2835 #address-cells = <1>;
2836 #size-cells = <1>;
2837 ranges;
2838
2839 glink_modem: modem {
2840 qcom,remote-pid = <1>;
2841 transport = "smem";
2842 mboxes = <&apcs_glb 12>;
2843 mbox-names = "mpss_smem";
2844 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
2845
2846 label = "modem";
2847 qcom,glink-label = "mpss";
2848
2849 qcom,modem_qrtr {
2850 qcom,glink-channels = "IPCRTR";
2851 qcom,low-latency;
2852 qcom,intents = <0x800 5
2853 0x2000 3
2854 0x4400 2>;
2855 };
2856
2857 qcom,msm_fastrpc_rpmsg {
2858 compatible = "qcom,msm-fastrpc-rpmsg";
2859 qcom,glink-channels = "fastrpcglink-apps-dsp";
2860 qcom,intents = <0x64 64>;
2861 };
2862
2863 qcom,modem_ds {
2864 qcom,glink-channels = "DS";
2865 qcom,intents = <0x4000 2>;
2866 };
2867
2868 qcom,modem_glink_ssr {
2869 qcom,glink-channels = "glink_ssr";
2870 qcom,notify-edges = <&glink_adsp>,
2871 <&glink_cdsp>;
2872 };
2873 };
2874
2875 glink_adsp: adsp {
2876 qcom,remote-pid = <2>;
2877 transport = "smem";
2878 mboxes = <&apcs_glb 8>;
2879 mbox-names = "adsp_smem";
2880 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
2881
2882 label = "adsp";
2883 qcom,glink-label = "lpass";
2884
2885 qcom,adsp_qrtr {
2886 qcom,glink-channels = "IPCRTR";
2887 qcom,low-latency;
2888 qcom,intents = <0x800 5
2889 0x2000 3
2890 0x4400 2>;
2891 };
2892
2893 qcom,apr_tal_rpmsg {
2894 qcom,glink-channels = "apr_audio_svc";
2895 qcom,intents = <0x200 20>;
2896 };
2897
2898 qcom,msm_fastrpc_rpmsg {
2899 compatible = "qcom,msm-fastrpc-rpmsg";
2900 qcom,glink-channels = "fastrpcglink-apps-dsp";
2901 qcom,intents = <0x64 64>;
2902 };
2903
2904 qcom,adsp_glink_ssr {
2905 qcom,glink-channels = "glink_ssr";
2906 qcom,notify-edges = <&glink_modem>,
2907 <&glink_cdsp>;
2908 };
2909 };
2910
2911 glink_cdsp: cdsp {
2912 qcom,remote-pid = <5>;
2913 transport = "smem";
2914 mboxes = <&apcs_glb 28>;
2915 mbox-names = "cdsp_smem";
2916 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;
2917
2918 label = "cdsp";
2919 qcom,glink-label = "cdsp";
2920
2921 qcom,cdsp_qrtr {
2922 qcom,glink-channels = "IPCRTR";
2923 qcom,intents = <0x800 5
2924 0x2000 3
2925 0x4400 2>;
2926 };
2927
2928 qcom,msm_fastrpc_rpmsg {
2929 compatible = "qcom,msm-fastrpc-rpmsg";
2930 qcom,glink-channels = "fastrpcglink-apps-dsp";
2931 qcom,intents = <0x64 64>;
2932 };
2933
2934 qcom,msm_cdsprm_rpmsg {
2935 compatible = "qcom,msm-cdsprm-rpmsg";
2936 qcom,glink-channels = "cdsprmglink-apps-dsp";
2937 qcom,intents = <0x20 12>;
2938
2939 msm_cdsp_rm: qcom,msm_cdsp_rm {
2940 compatible = "qcom,msm-cdsp-rm";
2941 qcom,qos-latency-us = <100>;
2942 qcom,qos-maxhold-ms = <20>;
2943 };
2944 };
2945
2946 qcom,cdsp_glink_ssr {
2947 qcom,glink-channels = "glink_ssr";
2948 qcom,notify-edges = <&glink_modem>,
2949 <&glink_adsp>;
2950 };
2951 };
2952 };
2953
2954 qcom,glinkpkt {
2955 compatible = "qcom,glinkpkt";
2956
2957 qcom,glinkpkt-at-mdm0 {
2958 qcom,glinkpkt-edge = "mpss";
2959 qcom,glinkpkt-ch-name = "DS";
2960 qcom,glinkpkt-dev-name = "at_mdm0";
2961 };
2962
2963 qcom,glinkpkt-apr-apps2 {
2964 qcom,glinkpkt-edge = "adsp";
2965 qcom,glinkpkt-ch-name = "apr_apps2";
2966 qcom,glinkpkt-dev-name = "apr_apps2";
2967 };
2968
2969 qcom,glinkpkt-data40-cntl {
2970 qcom,glinkpkt-edge = "mpss";
2971 qcom,glinkpkt-ch-name = "DATA40_CNTL";
2972 qcom,glinkpkt-dev-name = "smdcntl8";
2973 };
2974
2975 qcom,glinkpkt-data1 {
2976 qcom,glinkpkt-edge = "mpss";
2977 qcom,glinkpkt-ch-name = "DATA1";
2978 qcom,glinkpkt-dev-name = "smd7";
2979 };
2980
2981 qcom,glinkpkt-data4 {
2982 qcom,glinkpkt-edge = "mpss";
2983 qcom,glinkpkt-ch-name = "DATA4";
2984 qcom,glinkpkt-dev-name = "smd8";
2985 };
2986
2987 qcom,glinkpkt-data11 {
2988 qcom,glinkpkt-edge = "mpss";
2989 qcom,glinkpkt-ch-name = "DATA11";
2990 qcom,glinkpkt-dev-name = "smd11";
2991 };
2992 };
2993
2994 qcom,smp2p_sleepstate {
2995 compatible = "qcom,smp2p-sleepstate";
2996 qcom,smem-states = <&sleepstate_smp2p_out 0>;
2997 interrupt-parent = <&sleepstate_smp2p_in>;
2998 interrupts = <0 0>;
2999 interrupt-names = "smp2p-sleepstate-in";
3000 };
3001
3002 qcom,smp2p-modem {
3003 compatible = "qcom,smp2p";
3004 qcom,smem = <435>, <428>;
3005 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
3006 mboxes = <&apcs_glb 14>;
3007 qcom,local-pid = <0>;
3008 qcom,remote-pid = <1>;
3009
3010 modem_smp2p_out: master-kernel {
3011 qcom,entry-name = "master-kernel";
3012 #qcom,smem-state-cells = <1>;
3013 };
3014
3015 modem_smp2p_in: slave-kernel {
3016 qcom,entry-name = "slave-kernel";
3017 interrupt-controller;
3018 #interrupt-cells = <2>;
3019 };
3020
3021 smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
3022 qcom,entry-name = "ipa";
3023 #qcom,smem-state-cells = <1>;
3024 };
3025
3026 /* ipa - inbound entry from mss */
3027 smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
3028 qcom,entry-name = "ipa";
3029 interrupt-controller;
3030 #interrupt-cells = <2>;
3031 };
3032
3033 smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
3034 qcom,entry-name = "wlan";
3035 interrupt-controller;
3036 #interrupt-cells = <2>;
3037 };
3038
3039 };
3040
3041 qcom,smp2p-adsp {
3042 compatible = "qcom,smp2p";
3043 qcom,smem = <443>, <429>;
3044 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
3045 mboxes = <&apcs_glb 10>;
3046 qcom,local-pid = <0>;
3047 qcom,remote-pid = <2>;
3048
3049 adsp_smp2p_out: master-kernel {
3050 qcom,entry-name = "master-kernel";
3051 #qcom,smem-state-cells = <1>;
3052 };
3053
3054 adsp_smp2p_in: slave-kernel {
3055 qcom,entry-name = "slave-kernel";
3056 interrupt-controller;
3057 #interrupt-cells = <2>;
3058 };
3059
3060 smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
3061 qcom,entry-name = "rdbg";
3062 #qcom,smem-state-cells = <1>;
3063 };
3064
3065 smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
3066 qcom,entry-name = "rdbg";
3067 interrupt-controller;
3068 #interrupt-cells = <2>;
3069 };
3070
3071 sleepstate_smp2p_out: sleepstate-out {
3072 qcom,entry-name = "sleepstate";
3073 #qcom,smem-state-cells = <1>;
3074 };
3075
3076 sleepstate_smp2p_in: qcom,sleepstate-in {
3077 qcom,entry-name = "sleepstate_see";
3078 interrupt-controller;
3079 #interrupt-cells = <2>;
3080 };
3081 };
3082
3083 qcom,smp2p-cdsp {
3084 compatible = "qcom,smp2p";
3085 qcom,smem = <94>, <432>;
3086 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
3087 mboxes = <&apcs_glb 30>;
3088 qcom,local-pid = <0>;
3089 qcom,remote-pid = <5>;
3090
3091 cdsp_smp2p_out: master-kernel {
3092 qcom,entry-name = "master-kernel";
3093 #qcom,smem-state-cells = <1>;
3094 };
3095
3096 cdsp_smp2p_in: slave-kernel {
3097 qcom,entry-name = "slave-kernel";
3098 interrupt-controller;
3099 #interrupt-cells = <2>;
3100 };
3101
3102 smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
3103 qcom,entry-name = "rdbg";
3104 #qcom,smem-state-cells = <1>;
3105 };
3106
3107 smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
3108 qcom,entry-name = "rdbg";
3109 interrupt-controller;
3110 #interrupt-cells = <2>;
3111 };
3112 };
3113
3114 qcom,sps {
3115 compatible = "qcom,msm-sps-4k";
3116 qcom,pipe-attr-ee;
3117 };
3118
3119 qfprom: qfprom@1b40000 {
3120 compatible = "qcom,qfprom";
3121 reg = <0x1b40000 0x7000>;
3122 #address-cells = <1>;
3123 #size-cells = <1>;
3124 read-only;
3125 ranges;
3126
3127 stm_debug_fuse: stm@20f0 {
3128 reg = <0x20f0 0x4>;
3129 };
3130
3131 feat_conf5: feat_conf5@6018 {
3132 reg = <0x6018 0x4>;
3133 };
3134
3135 feat_conf10: feat_conf10@602c {
3136 reg = <0x602c 0x4>;
3137 };
3138
3139 adsp_variant: adsp_variant@6011 {
3140 reg = <0x6011 0x1>;
3141 bits = <3 1>;
3142 };
3143
3144 gpu_speed_bin: gpu_speed_bin@6006 {
3145 reg = <0x6006 0x2>;
3146 bits = <5 8>;
3147 };
3148
3149 gpu_gaming_bin: gpu_gaming_bin@602d {
3150 reg = <0x602d 0x1>;
3151 bits = <5 1>;
3152 };
3153
3154 feat_conf11: feat_conf11@6030 {
3155 reg = <0x6030 0x1>;
3156 bits = <0 8>;
3157 };
3158 };
3159
3160 spmi_bus: qcom,spmi@1c40000 {
3161 compatible = "qcom,spmi-pmic-arb";
3162 reg = <0x1c40000 0x1100>,
3163 <0x1e00000 0x2000000>,
3164 <0x3e00000 0x100000>,
3165 <0x3f00000 0xa0000>,
3166 <0x1c0a000 0x26000>;
3167 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3168 interrupt-names = "periph_irq";
3169 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
3170 qcom,ee = <0>;
3171 qcom,channel = <0>;
3172 #address-cells = <1>;
3173 #size-cells = <1>;
3174 interrupt-controller;
3175 #interrupt-cells = <4>;
3176 cell-index = <0>;
3177 };
3178
3179 icnss: qcom,icnss@C800000 {
3180 compatible = "qcom,icnss";
3181 reg = <0xC800000 0x800000>,
3182 <0xb0000000 0x10000>;
3183 reg-names = "membase", "smmu_iova_ipa";
3184 iommus = <&apps_smmu 0x1A0 0x1>;
3185 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3186 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3187 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3188 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3189 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3190 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3191 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3192 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3193 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3194 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3195 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,
3196 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;
3197 qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
3198 qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
3199 qcom,iommu-dma = "fastmap";
3200 qcom,iommu-faults = "stall-disable", "HUPCF";
3201 qcom,iommu-geometry = <0xa0000000 0x10010000>;
3202 vdd-cx-mx-supply = <&L8A>;
3203 vdd-1.8-xo-supply = <&L16A>;
3204 vdd-1.3-rfa-supply = <&L17A>;
3205 vdd-3.3-ch0-supply = <&L23A>;
3206 qcom,vdd-cx-mx-config = <640000 640000>;
3207 qcom,vdd-3.3-ch0-config = <3000000 3312000>;
3208 qcom,smp2p_map_wlan_1_in {
3209 interrupts-extended = <&smp2p_wlan_1_in 0 0>,
3210 <&smp2p_wlan_1_in 1 0>;
3211 interrupt-names = "qcom,smp2p-force-fatal-error",
3212 "qcom,smp2p-early-crash-ind";
3213 };
3214 };
3215
3216 qcom,venus@5ab0000 {
3217 compatible = "qcom,pil-tz-generic";
3218 reg = <0x5ab0000 0x20000>;
3219
3220 vdd-supply = <&gcc_venus_gdsc>;
3221 qcom,proxy-reg-names = "vdd";
3222
3223 clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
3224 <&gcc GCC_VENUS_CTL_AXI_CLK>,
3225 <&gcc GCC_VIDEO_AHB_CLK>,
3226 <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;
3227 clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
3228 qcom,proxy-clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
3229 qcom,mas-crypto = <&mas_crypto_c0>;
3230
3231 qcom,core-freq = <240000000>;
3232 qcom,ahb-freq = <240000000>;
3233
3234 qcom,pas-id = <9>;
3235 qcom,msm-bus,name = "pil-venus";
3236 qcom,msm-bus,num-cases = <2>;
3237 qcom,msm-bus,num-paths = <1>;
3238 qcom,msm-bus,vectors-KBps =
3239 <63 512 0 0>,
3240 <63 512 0 304000>;
3241 qcom,proxy-timeout-ms = <100>;
3242 qcom,firmware-name = "venus";
3243 memory-region = <&pil_video_mem>;
3244 };
3245
3246 cx_ipeak_lm: cx_ipeak@3ed000 {
3247 compatible = "qcom,cx-ipeak-v2";
3248 reg = <0x3ed000 0xe008>;
3249 };
3250
3251 pil_modem: qcom,mss@6080000 {
3252 compatible = "qcom,pil-tz-generic";
3253 reg = <0x6080000 0x100>;
3254
3255 clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>;
3256 clock-names = "xo";
3257 qcom,proxy-clock-names = "xo";
3258 qcom,mas-crypto = <&mas_crypto_c0>;
3259
3260 vdd_cx-supply = <&VDD_CX_LEVEL>;
3261 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
3262 qcom,proxy-reg-names = "vdd_cx";
3263
3264 qcom,firmware-name = "modem";
3265 memory-region = <&pil_modem_mem>;
3266 qcom,proxy-timeout-ms = <10000>;
3267 qcom,sysmon-id = <0>;
3268 qcom,ssctl-instance-id = <0x12>;
3269 qcom,pas-id = <4>;
3270 qcom,smem-id = <421>;
3271 qcom,minidump-id = <3>;
3272 qcom,aux-minidump-ids = <4>;
3273 qcom,complete-ramdump;
3274 qcom,sequential-fw-load;
3275
3276 qcom,msm-bus,name = "pil-modem";
3277 qcom,msm-bus,num-cases = <2>;
3278 qcom,msm-bus,num-paths = <1>;
3279 qcom,msm-bus,vectors-KBps =
3280 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0 0 0>,
3281 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0 0 8171520>;
3282
3283 /* Inputs from mss */
3284 interrupts-extended = <&intc 0 307 1>,
3285 <&modem_smp2p_in 0 0>,
3286 <&modem_smp2p_in 2 0>,
3287 <&modem_smp2p_in 1 0>,
3288 <&modem_smp2p_in 3 0>,
3289 <&modem_smp2p_in 7 0>;
3290
3291 interrupt-names = "qcom,wdog",
3292 "qcom,err-fatal",
3293 "qcom,proxy-unvote",
3294 "qcom,err-ready",
3295 "qcom,stop-ack",
3296 "qcom,shutdown-ack";
3297
3298 /* Outputs to mss */
3299 qcom,smem-states = <&modem_smp2p_out 0>;
3300 qcom,smem-state-names = "qcom,force-stop";
3301 };
3302
3303 ddr_bw_opp_table: ddr-bw-opp-table {
3304 compatible = "operating-points-v2";
3305 BW_OPP_ENTRY_DDR( 200, 8, 0x80); /* 1525 MB/s */
3306 BW_OPP_ENTRY_DDR( 547, 8, 0x80); /* 4173 MB/s */
3307 BW_OPP_ENTRY_DDR( 768, 8, 0x80); /* 5859 MB/s */
3308 BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */
3309 BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */
3310 BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */
3311 BW_OPP_ENTRY_DDR(2092, 8, 0x80); /*15960 MB/s */
3312 };
3313
3314 suspendable_ddr4_bw_opp_table: suspendable-ddr4-bw-opp-table {
3315 compatible = "operating-points-v2";
3316 BW_OPP_ENTRY_DDR( 0, 8, 0x80); /* 0 MB/s */
3317 BW_OPP_ENTRY_DDR( 200, 8, 0x80); /* 1525 MB/s */
3318 BW_OPP_ENTRY_DDR( 547, 8, 0x80); /* 4173 MB/s */
3319 BW_OPP_ENTRY_DDR( 768, 8, 0x80); /* 5859 MB/s */
3320 BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */
3321 BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */
3322 BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */
3323 BW_OPP_ENTRY_DDR(2092, 8, 0x80); /*15960 MB/s */
3324 };
3325
3326 cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw {
3327 compatible = "qcom,devbw-ddr";
3328 governor = "performance";
3329 qcom,src-dst-ports =
3330 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
3331 qcom,active-only;
3332 operating-points-v2 = <&ddr_bw_opp_table>;
3333 };
3334
3335 cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01b8e200 {
3336 compatible = "qcom,bimc-bwmon4";
3337 reg = <0x01b8e300 0x100>, <0x01b8e200 0x100>;
3338 reg-names = "base", "global_base";
3339 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
3340 qcom,mport = <0>;
3341 qcom,hw-timer-hz = <19200000>;
3342 qcom,target-dev = <&cpu_cpu_ddr_bw>;
3343 qcom,count-unit = <0x10000>;
3344 };
3345
3346 cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
3347 compatible = "qcom,devbw-ddr";
3348 governor = "performance";
3349 qcom,src-dst-ports =
3350 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
3351 qcom,active-only;
3352 operating-points-v2 = <&ddr_bw_opp_table>;
3353 };
3354
3355 cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {
3356 compatible = "qcom,devbw-ddr";
3357 governor = "performance";
3358 qcom,src-dst-ports =
3359 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
3360 qcom,active-only;
3361 operating-points-v2 = <&ddr_bw_opp_table>;
3362 };
3363
3364 cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
3365 compatible = "qcom,arm-memlat-cpugrp";
3366 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
3367
3368 cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon {
3369 compatible = "qcom,arm-memlat-mon";
3370 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
3371 qcom,target-dev = <&cpu0_cpu_ddr_lat>;
3372 qcom,cachemiss-ev = <0x17>;
3373 qcom,stall-cycle-ev = <0xE7>;
3374 qcom,core-dev-table =
3375 < 1190400 MHZ_TO_MBPS( 547, 8) >,
3376 < 1516800 MHZ_TO_MBPS( 768, 8) >,
3377 < 1804800 MHZ_TO_MBPS(1017, 8) >;
3378 };
3379
3380 cpu0_computemon: qcom,cpu0-computemon {
3381 compatible = "qcom,arm-compute-mon";
3382 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
3383 qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
3384 qcom,core-dev-table =
3385 < 1190400 MHZ_TO_MBPS( 547, 8) >,
3386 < 1516800 MHZ_TO_MBPS( 768, 8) >,
3387 < 1804800 MHZ_TO_MBPS(1017, 8) >;
3388 };
3389 };
3390
3391 cpu4_cpu_ddr_lat: qcom,cpu4-cpu-ddr-lat {
3392 compatible = "qcom,devbw-ddr";
3393 governor = "performance";
3394 qcom,src-dst-ports =
3395 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
3396 qcom,active-only;
3397 operating-points-v2 = <&ddr_bw_opp_table>;
3398 };
3399
3400 cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
3401 compatible = "qcom,devbw-ddr";
3402 governor = "performance";
3403 qcom,src-dst-ports =
3404 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
3405 qcom,active-only;
3406 operating-points-v2 = <&ddr_bw_opp_table>;
3407 };
3408
3409 cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
3410 compatible = "qcom,arm-memlat-cpugrp";
3411 qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
3412
3413 cpu4_cpu_ddr_latmon: qcom,cpu4-cpu-ddr-latmon {
3414 compatible = "qcom,arm-memlat-mon";
3415 qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
3416 qcom,target-dev = <&cpu4_cpu_ddr_lat>;
3417 qcom,cachemiss-ev = <0x17>;
3418 qcom,stall-cycle-ev = <0x24>;
3419 qcom,core-dev-table =
3420 < 1056000 MHZ_TO_MBPS( 547, 8) >,
3421 < 1344000 MHZ_TO_MBPS(1017, 8) >,
3422 < 1766400 MHZ_TO_MBPS(1555, 8) >,
3423 < 2208000 MHZ_TO_MBPS(1804, 8) >,
3424 < 2803200 MHZ_TO_MBPS(2092, 8) >;
3425 };
3426
3427 cpu4_computemon: qcom,cpu4-computemon {
3428 compatible = "qcom,arm-compute-mon";
3429 qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
3430 qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
3431 qcom,core-dev-table =
3432 < 1056000 MHZ_TO_MBPS( 547, 8) >,
3433 < 1344000 MHZ_TO_MBPS( 768, 8) >,
3434 < 1766400 MHZ_TO_MBPS(1017, 8) >,
3435 < 2208000 MHZ_TO_MBPS(1804, 8) >,
3436 < 2803200 MHZ_TO_MBPS(2092, 8) >;
3437 };
3438 };
3439
3440 qcom,msm_gsi {
3441 compatible = "qcom,msm_gsi";
3442 };
3443
3444 qcom,rmnet-ipa {
3445 compatible = "qcom,rmnet-ipa3";
3446 qcom,rmnet-ipa-ssr;
3447 qcom,ipa-platform-type-msm;
3448 qcom,ipa-advertise-sg-support;
3449 qcom,ipa-napi-enable;
3450 };
3451
3452 ipa_hw: qcom,ipa@0x5800000 {
3453 compatible = "qcom,ipa";
3454 reg = <0x5800000 0x34000>,
3455 <0x5804000 0x28000>;
3456 reg-names = "ipa-base", "gsi-base";
3457 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
3458 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
3459 interrupt-names = "ipa-irq", "gsi-irq";
3460 qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */
3461 qcom,ipa-hw-mode = <0>;
3462 qcom,platform-type = <1>; /* MSM platform */
3463 qcom,ee = <0>;
3464 qcom,use-ipa-tethering-bridge;
3465 qcom,modem-cfg-emb-pipe-flt;
3466 qcom,ipa-wdi2;
3467 qcom,ipa-wdi2_over_gsi;
3468 qcom,ipa-endp-delay-wa;
3469 qcom,ipa-fltrt-not-hashable;
3470 qcom,use-64-bit-dma-mask;
3471 qcom,arm-smmu;
3472 qcom,smmu-fast-map;
3473 qcom,use-ipa-pm;
3474 qcom,skip-ieob-mask-wa;
3475 clocks = <&rpmcc RPM_SMD_IPA_CLK>;
3476 clock-names = "core_clk";
3477 qcom,msm-bus,name = "ipa";
3478 qcom,msm-bus,num-cases = <5>;
3479 qcom,msm-bus,num-paths = <3>;
3480 qcom,msm-bus,vectors-KBps =
3481 /* No vote */
3482 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 0 0>,
3483 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,
3484 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,
3485 /* SVS2 */
3486 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 465000>,
3487 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 68570>,
3488 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 30>,
3489 /* SVS */
3490 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 2000000>,
3491 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 267461>,
3492 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 109890>,
3493 /* NOMINAL */
3494 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 4000000>,
3495 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 712961>,
3496 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>,
3497 /* TURBO */
3498 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 5598900>,
3499 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 1436481>,
3500 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>;
3501 qcom,bus-vector-names =
3502 "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
3503 qcom,throughput-threshold = <310 600 1000>;
3504 qcom,scaling-exceptions = <>;
3505
3506 /* smp2p information */
3507 qcom,smp2p_map_ipa_1_out {
3508 compatible = "qcom,smp2p-map-ipa-1-out";
3509 qcom,smem-states = <&smp2p_ipa_1_out 0>;
3510 qcom,smem-state-names = "ipa-smp2p-out";
3511 };
3512
3513 qcom,smp2p_map_ipa_1_in {
3514 compatible = "qcom,smp2p-map-ipa-1-in";
3515 interrupts-extended = <&smp2p_ipa_1_in 0 0>;
3516 interrupt-names = "ipa-smp2p-in";
3517 };
3518 };
3519
3520 ipa_smmu_ap: ipa_smmu_ap {
3521 compatible = "qcom,ipa-smmu-ap-cb";
3522 iommus = <&apps_smmu 0x0140 0x0>;
3523 qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>;
3524 /* modem tables in IMEM */
3525 qcom,iommu-dma = "fastmap";
3526 qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>;
3527 qcom,iommu-geometry = <0 0xB0000000>;
3528 };
3529
3530 ipa_smmu_wlan: ipa_smmu_wlan {
3531 compatible = "qcom,ipa-smmu-wlan-cb";
3532 iommus = <&apps_smmu 0x0141 0x0>;
3533 /* ipa-uc ram */
3534 qcom,iommu-dma = "atomic";
3535 };
3536
3537 ipa_smmu_uc: ipa_smmu_uc {
3538 compatible = "qcom,ipa-smmu-uc-cb";
3539 iommus = <&apps_smmu 0x0142 0x0>;
3540 qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>;
3541 };
3542
3543 qcom,ipa_fws {
3544 compatible = "qcom,pil-tz-generic";
3545 qcom,pas-id = <0xf>;
3546 qcom,firmware-name = "ipa_fws";
3547 qcom,pil-force-shutdown;
3548 memory-region = <&pil_ipa_fw_mem>;
3549 };
3550
3551 qcom,demux {
3552 compatible = "qcom,demux";
3553 };
3554
3555tpdm_turing_llm: tpdm@8861000 {
3556 compatible = "qcom,coresight-dummy";
3557
3558 coresight-name = "coresight-tpdm-turing_llm";
3559 qcom,dummy-source;
3560
3561 port {
3562 tpdm_turing_llm_out_funnel_turing: endpoint {
3563 remote-endpoint =
3564 <&funnel_turing_in_tpdm_turing_llm>;
3565 };
3566 };
3567 };
3568
3569 /delete-node/ tpdm@8a58000;
3570 tpdm_west: tpdm@8a58000 {
3571 compatible = "arm,primecell";
3572 arm,primecell-periphid = <0x000bb968>;
3573 reg = <0x8a58000 0x1000>;
3574 reg-names = "tpdm-base";
3575
3576 coresight-name = "coresight-tpdm-west";
3577
3578 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
3579 clock-names = "apb_pclk";
3580 port {
3581 tpdm_west_out_tpda11: endpoint {
3582 remote-endpoint =
3583 <&tpda11_in_tpdm_west>;
3584 };
3585 };
3586 };
3587
3588 tpdm_spdm: tpdm@800f000 {
3589 compatible = "arm,primecell";
3590 arm,primecell-periphid = <0x000bb968>;
3591 reg = <0x0800f000 0x1000>;
3592 reg-names = "tpdm-base";
3593
3594 coresight-name = "coresight-tpdm-spdm";
3595
3596 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
3597 clock-names = "apb_pclk";
3598 port {
3599 tpdm_spdm_out_tpda13: endpoint {
3600 remote-endpoint =
3601 <&tpda13_in_tpdm_spdm>;
3602 };
3603 };
3604 };
3605
3606 /delete-node/ funnel@8861000;
3607 funnel_turing: funnel@8863000 {
3608 compatible = "arm,primecell";
3609 arm,primecell-periphid = <0x000bb908>;
3610 reg = <0x8863000 0x1000>;
3611 reg-names = "funnel-base";
3612
3613 coresight-name = "coresight-funnel-turing";
3614
3615 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
3616 clock-names = "apb_pclk";
3617 ports {
3618 #address-cells = <1>;
3619 #size-cells = <0>;
3620
3621 port@0 {
3622 reg = <0>;
3623 funnel_turing_out_funnel_qatb: endpoint {
3624 remote-endpoint =
3625 <&funnel_qatb_in_funnel_turing>;
3626 source = <&turing_etm0>;
3627 };
3628 };
3629
3630 port@1 {
3631 reg = <1>;
3632 funnel_turing_out_tpda5: endpoint {
3633 remote-endpoint =
3634 <&tpda5_in_funnel_turing>;
3635 };
3636 };
3637
3638 port@2 {
3639 reg = <0>;
3640 funnel_turing_in_tpdm_turing: endpoint {
3641 slave-mode;
3642 remote-endpoint =
3643 <&tpdm_turing_out_funnel_turing>;
3644 };
3645 };
3646
3647 port@3 {
3648 reg = <1>;
3649 funnel_turing_in_tpdm_turing_llm: endpoint {
3650 slave-mode;
3651 remote-endpoint =
3652 <&tpdm_turing_llm_out_funnel_turing>;
3653 };
3654 };
3655
3656 port@4 {
3657 reg = <2>;
3658 funnel_turing_in_turing_etm0: endpoint {
3659 slave-mode;
3660 remote-endpoint =
3661 <&turing_etm0_out_funnel_turing>;
3662 };
3663 };
3664 };
3665 };
3666
3667 /delete-node/ tpda@8004000;
3668 tpda: tpda@8004000 {
3669 compatible = "arm,primecell";
3670 arm,primecell-periphid = <0x000bb969>;
3671 reg = <0x8004000 0x1000>;
3672 reg-names = "tpda-base";
3673
3674 coresight-name = "coresight-tpda";
3675
3676 qcom,tpda-atid = <65>;
3677 qcom,dsb-elem-size = <0 32>,
3678 <1 32>,
3679 <5 32>,
3680 <11 32>,
3681 <12 32>,
3682 <15 32>;
3683 qcom,cmb-elem-size = <7 32>,
3684 <8 32>,
3685 <10 32>,
3686 <15 64>;
3687
3688 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
3689 clock-names = "apb_pclk";
3690
3691 ports {
3692 #address-cells = <1>;
3693 #size-cells = <0>;
3694 port@0 {
3695 reg = <0>;
3696 tpda_out_funnel_qatb: endpoint {
3697 remote-endpoint =
3698 <&funnel_qatb_in_tpda>;
3699 };
3700 };
3701
3702 port@1 {
3703 reg = <0>;
3704 tpda0_in_tpdm_dl_ct: endpoint {
3705 slave-mode;
3706 remote-endpoint =
3707 <&tpdm_dl_ct_out_tpda0>;
3708 };
3709 };
3710
3711 port@2 {
3712 reg = <1>;
3713 tpda1_in_funnel_gpu: endpoint {
3714 slave-mode;
3715 remote-endpoint =
3716 <&funnel_gpu_out_tpda1>;
3717 };
3718 };
3719
3720 port@3 {
3721 reg = <5>;
3722 tpda5_in_funnel_turing: endpoint {
3723 slave-mode;
3724 remote-endpoint =
3725 <&funnel_turing_out_tpda5>;
3726 };
3727 };
3728
3729 port@4 {
3730 reg = <7>;
3731 tpda7_in_tpdm_vsense: endpoint {
3732 slave-mode;
3733 remote-endpoint =
3734 <&tpdm_vsense_out_tpda7>;
3735 };
3736 };
3737
3738 port@5 {
3739 reg = <8>;
3740 tpda8_in_tpdm_dcc: endpoint {
3741 slave-mode;
3742 remote-endpoint =
3743 <&tpdm_dcc_out_tpda8>;
3744 };
3745 };
3746
3747 port@6 {
3748 reg = <10>;
3749 tpda10_in_tpdm_prng: endpoint {
3750 slave-mode;
3751 remote-endpoint =
3752 <&tpdm_prng_out_tpda10>;
3753 };
3754 };
3755
3756 port@7 {
3757 reg = <11>;
3758 tpda11_in_tpdm_west: endpoint {
3759 slave-mode;
3760 remote-endpoint =
3761 <&tpdm_west_out_tpda11>;
3762 };
3763 };
3764
3765 port@8 {
3766 reg = <12>;
3767 tpda12_in_tpdm_qm: endpoint {
3768 slave-mode;
3769 remote-endpoint =
3770 <&tpdm_qm_out_tpda12>;
3771 };
3772 };
3773
3774 port@9 {
3775 reg = <13>;
3776 tpda13_in_tpdm_spdm: endpoint {
3777 slave-mode;
3778 remote-endpoint =
3779 <&tpdm_spdm_out_tpda13>;
3780 };
3781 };
3782
3783 port@10 {
3784 reg = <15>;
3785 tpda15_in_tpdm_pimem: endpoint {
3786 slave-mode;
3787 remote-endpoint =
3788 <&tpdm_pimem_out_tpda15>;
3789 };
3790 };
3791
3792 };
3793 };
3794
3795 /delete-node/ cti@8867000;
3796 cti_turing_q6: cti@8862000 {
3797 compatible = "arm,primecell";
3798 arm,primecell-periphid = <0x000bb966>;
3799 reg = <0x8862000 0x1000>;
3800 reg-names = "cti-base";
3801
3802 coresight-name = "coresight-cti-turing-q6";
3803
3804 clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
3805 clock-names = "apb_pclk";
3806 };
3807};
3808
3809#include "bengal-gdsc.dtsi"
3810#include "khaje-usb.dtsi"
3811#include "bengal-ion.dtsi"
3812#include "bengal-bus.dtsi"
3813#include "bengal-vidc.dtsi"
3814#include "pm6125.dtsi"
3815
3816&gcc_camss_top_gdsc {
3817 status = "ok";
3818};
3819
3820&gcc_ufs_phy_gdsc {
3821 status = "ok";
3822};
3823
3824&gcc_usb30_prim_gdsc {
3825 status = "ok";
3826};
3827
3828&gcc_vcodec0_gdsc {
3829 qcom,support-hw-trigger;
3830 status = "ok";
3831};
3832
3833&gcc_venus_gdsc {
3834 status = "ok";
3835};
3836
3837&hlos1_vote_turing_mmu_tbu1_gdsc {
3838 status = "ok";
3839};
3840
3841&hlos1_vote_turing_mmu_tbu0_gdsc {
3842 status = "ok";
3843};
3844
3845&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {
3846 status = "ok";
3847};
3848
3849&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {
3850 status = "ok";
3851};
3852
3853&mdss_core_gdsc {
3854 reg = <0x5f01004 0x4>;
3855 qcom,support-hw-trigger;
3856 status = "ok";
3857};
3858
3859&gpu_cx_gdsc {
3860 parent-supply = <&VDD_CX_LEVEL>;
3861 status = "ok";
3862};
3863
3864&gpu_gx_gdsc {
3865 parent-supply = <&VDD_CX_LEVEL>;
3866 status = "ok";
3867};
3868
3869#include "msm-arm-smmu-bengal.dtsi"
3870#include "pm6125-rpm-regulator.dtsi"
3871#include "khaje-regulator.dtsi"
3872#include "bengal-pm.dtsi"
3873#include "khaje-pinctrl.dtsi"
3874#include "bengal-qupv3.dtsi"
3875#include "bengal-gpu.dtsi"
3876#include "bengal-audio.dtsi"
3877#include "khaje-sde-pll.dtsi"
3878#include "khaje-sde.dtsi"
3879
3880&soc {
3881 /delete-node/ gpu_bw_tbl;
3882 /delete-node/ gpubw;
3883 /delete-node/ gpu_opp_table;
3884
3885 gpu_bw_tbl: gpu-bw-tbl {
3886 compatible = "operating-points-v2";
3887 BW_OPP_ENTRY( 0, 8); /* 0 MB/s */
3888 BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */
3889 BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */
3890 BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */
3891 BW_OPP_ENTRY(1017, 8); /* 7759 MB/s */
3892 BW_OPP_ENTRY(1555, 8); /*11863 MB/s */
3893 BW_OPP_ENTRY(1804, 8); /*13763 MB/s */
3894 BW_OPP_ENTRY(2092, 8); /*15960 MB/s */
3895 };
3896
3897 gpubw: qcom,gpubw {
3898 compatible = "qcom,devbw";
3899 governor = "bw_vbif";
3900 qcom,src-dst-ports = <26 512>;
3901 operating-points-v2 = <&gpu_bw_tbl>;
3902 };
3903
3904 gpu_opp_table: gpu-opp-table {
3905 compatible = "operating-points-v2";
3906
3907 opp-1114800000 {
3908 opp-hz = /bits/ 64 <1114800000>;
3909 opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3910 };
3911
3912 opp-1025000000 {
3913 opp-hz = /bits/ 64 <1025000000>;
3914 opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
3915 };
3916
3917 opp-785000000 {
3918 opp-hz = /bits/ 64 <785000000>;
3919 opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
3920 };
3921
3922 opp-600000000 {
3923 opp-hz = /bits/ 64 <600000000>;
3924 opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3925 };
3926
3927 opp-465000000 {
3928 opp-hz = /bits/ 64 <465000000>;
3929 opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
3930 };
3931
3932 opp-320000000 {
3933 opp-hz = /bits/ 64 <320000000>;
3934 opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3935 };
3936 };
3937};
3938
3939&msm_gpu {
3940 qcom,chipid = <0x06010001>;
3941 qcom,msm-bus,num-cases = <8>;
3942 qcom,msm-bus,vectors-KBps =
3943 <26 512 0 0>,
3944 <26 512 0 1600000>, /* 1 bus=200 (LOW SVS) */
3945 <26 512 0 4376000>, /* 2 bus=547 (LOW SVS) */
3946 <26 512 0 6144000>, /* 3 bus=768 (SVS) */
3947 <26 512 0 8136000>, /* 4 bus=1017 (SVS_L1) */
3948 <26 512 0 12440000>, /* 5 bus=1555 (NOM) */
3949 <26 512 0 14432000>, /* 6 bus=1804 (TURBO) */
3950 <26 512 0 16736000>; /* 7 bus=2092 (TURBO_L1) */
3951
3952 /delete-node/ qcom,gpu-pwrlevel-bins;
3953 /*
3954 * Speed-bin zero is default speed bin.
3955 * For rest of the speed bins, speed-bin value
3956 * is calculated as FMAX/4.8 MHz round up to zero
3957 * decimal places plus two margin to account for
3958 * clock jitters.
3959 */
3960 qcom,gpu-pwrlevel-bins {
3961 #address-cells = <1>;
3962 #size-cells = <0>;
3963
3964 compatible = "qcom,gpu-pwrlevel-bins";
3965
3966 qcom,gpu-pwrlevels-0 {
3967 #address-cells = <1>;
3968 #size-cells = <0>;
3969
3970 qcom,speed-bin = <0>;
3971
3972 qcom,initial-pwrlevel = <6>;
3973 qcom,ca-target-pwrlevel = <5>;
3974
3975 /* TURBO_L1 */
3976 qcom,gpu-pwrlevel@0 {
3977 reg = <0>;
3978 qcom,gpu-freq = <1260000000>;
3979 qcom,bus-freq = <7>;
3980 qcom,bus-min = <7>;
3981 qcom,bus-max = <7>;
3982 };
3983
3984 /* TURBO_L1 */
3985 qcom,gpu-pwrlevel@1 {
3986 reg = <1>;
3987 qcom,gpu-freq = <1114800000>;
3988 qcom,bus-freq = <7>;
3989 qcom,bus-min = <7>;
3990 qcom,bus-max = <7>;
3991 };
3992
3993 /* TURBO */
3994 qcom,gpu-pwrlevel@2 {
3995 reg = <2>;
3996 qcom,gpu-freq = <1025000000>;
3997 qcom,bus-freq = <6>;
3998 qcom,bus-min = <5>;
3999 qcom,bus-max = <7>;
4000 };
4001
4002 /* NOM */
4003 qcom,gpu-pwrlevel@3 {
4004 reg = <3>;
4005 qcom,gpu-freq = <785000000>;
4006 qcom,bus-freq = <5>;
4007 qcom,bus-min = <4>;
4008 qcom,bus-max = <5>;
4009 };
4010
4011 /* SVS_L1 */
4012 qcom,gpu-pwrlevel@4 {
4013 reg = <4>;
4014 qcom,gpu-freq = <600000000>;
4015 qcom,bus-freq = <4>;
4016 qcom,bus-min = <3>;
4017 qcom,bus-max = <5>;
4018 };
4019
4020 /* SVS */
4021 qcom,gpu-pwrlevel@5 {
4022 reg = <5>;
4023 qcom,gpu-freq = <465000000>;
4024 qcom,bus-freq = <3>;
4025 qcom,bus-min = <2>;
4026 qcom,bus-max = <4>;
4027 };
4028
4029 /* LOW SVS */
4030 qcom,gpu-pwrlevel@6 {
4031 reg = <6>;
4032 qcom,gpu-freq = <320000000>;
4033 qcom,bus-freq = <2>;
4034 qcom,bus-min = <1>;
4035 qcom,bus-max = <2>;
4036 };
4037
4038 /* XO */
4039 qcom,gpu-pwrlevel@7 {
4040 reg = <7>;
4041 qcom,gpu-freq = <0>;
4042 qcom,bus-freq = <0>;
4043 qcom,bus-min = <0>;
4044 qcom,bus-max = <0>;
4045 };
4046 };
4047
4048 qcom,gpu-pwrlevels-1 {
4049 #address-cells = <1>;
4050 #size-cells = <0>;
4051
4052 qcom,speed-bin = <235>;
4053
4054 qcom,initial-pwrlevel = <5>;
4055 qcom,ca-target-pwrlevel = <4>;
4056
4057 /* TURBO_L1 */
4058 qcom,gpu-pwrlevel@0 {
4059 reg = <0>;
4060 qcom,gpu-freq = <1114800000>;
4061 qcom,bus-freq = <7>;
4062 qcom,bus-min = <7>;
4063 qcom,bus-max = <7>;
4064 };
4065
4066 /* TURBO */
4067 qcom,gpu-pwrlevel@1 {
4068 reg = <1>;
4069 qcom,gpu-freq = <1025000000>;
4070 qcom,bus-freq = <6>;
4071 qcom,bus-min = <5>;
4072 qcom,bus-max = <7>;
4073 };
4074
4075 /* NOM */
4076 qcom,gpu-pwrlevel@2 {
4077 reg = <2>;
4078 qcom,gpu-freq = <785000000>;
4079 qcom,bus-freq = <5>;
4080 qcom,bus-min = <4>;
4081 qcom,bus-max = <5>;
4082 };
4083
4084 /* SVS_L1 */
4085 qcom,gpu-pwrlevel@3 {
4086 reg = <3>;
4087 qcom,gpu-freq = <600000000>;
4088 qcom,bus-freq = <4>;
4089 qcom,bus-min = <3>;
4090 qcom,bus-max = <5>;
4091 };
4092
4093 /* SVS */
4094 qcom,gpu-pwrlevel@4 {
4095 reg = <4>;
4096 qcom,gpu-freq = <465000000>;
4097 qcom,bus-freq = <3>;
4098 qcom,bus-min = <2>;
4099 qcom,bus-max = <4>;
4100 };
4101
4102 /* LOW SVS */
4103 qcom,gpu-pwrlevel@5 {
4104 reg = <5>;
4105 qcom,gpu-freq = <320000000>;
4106 qcom,bus-freq = <2>;
4107 qcom,bus-min = <1>;
4108 qcom,bus-max = <2>;
4109 };
4110
4111 /* XO */
4112 qcom,gpu-pwrlevel@6 {
4113 reg = <6>;
4114 qcom,gpu-freq = <0>;
4115 qcom,bus-freq = <0>;
4116 qcom,bus-min = <0>;
4117 qcom,bus-max = <0>;
4118 };
4119 };
4120
4121 qcom,gpu-pwrlevels-2 {
4122 #address-cells = <1>;
4123 #size-cells = <0>;
4124
4125 qcom,speed-bin = <216>;
4126
4127 qcom,initial-pwrlevel = <4>;
4128 qcom,ca-target-pwrlevel = <3>;
4129
4130 /* TURBO */
4131 qcom,gpu-pwrlevel@0 {
4132 reg = <0>;
4133 qcom,gpu-freq = <1025000000>;
4134 qcom,bus-freq = <6>;
4135 qcom,bus-min = <5>;
4136 qcom,bus-max = <7>;
4137 };
4138
4139 /* NOM */
4140 qcom,gpu-pwrlevel@1 {
4141 reg = <1>;
4142 qcom,gpu-freq = <785000000>;
4143 qcom,bus-freq = <5>;
4144 qcom,bus-min = <4>;
4145 qcom,bus-max = <5>;
4146 };
4147
4148 /* SVS_L1 */
4149 qcom,gpu-pwrlevel@2 {
4150 reg = <2>;
4151 qcom,gpu-freq = <600000000>;
4152 qcom,bus-freq = <4>;
4153 qcom,bus-min = <3>;
4154 qcom,bus-max = <5>;
4155 };
4156
4157 /* SVS */
4158 qcom,gpu-pwrlevel@3 {
4159 reg = <3>;
4160 qcom,gpu-freq = <465000000>;
4161 qcom,bus-freq = <3>;
4162 qcom,bus-min = <2>;
4163 qcom,bus-max = <4>;
4164 };
4165
4166 /* LOW SVS */
4167 qcom,gpu-pwrlevel@4 {
4168 reg = <4>;
4169 qcom,gpu-freq = <320000000>;
4170 qcom,bus-freq = <2>;
4171 qcom,bus-min = <1>;
4172 qcom,bus-max = <2>;
4173 };
4174
4175 /* XO */
4176 qcom,gpu-pwrlevel@5 {
4177 reg = <5>;
4178 qcom,gpu-freq = <0>;
4179 qcom,bus-freq = <0>;
4180 qcom,bus-min = <0>;
4181 qcom,bus-max = <0>;
4182 };
4183 };
4184 };
4185};
4186
4187&qupv3_se1_i2c {
4188 status = "ok";
4189 #include "pm8008.dtsi"
4190};
4191
4192&pm8008_regulators {
4193 /delete-property/ qcom,enable-ocp-broadcast;
4194};
4195
4196&pm8008_8 {
4197 /* PM8008 IRQ STAT */
4198 interrupt-parent = <&tlmm>;
4199 interrupts = <25 IRQ_TYPE_EDGE_RISING>;
4200
4201 pinctrl-names = "default";
4202 pinctrl-0 = <&pm8008_active &pm8008_interrupt>;
4203};
4204
4205&pm8008_regulators {
4206 vdd_l1_l2-supply = <&S6A>;
4207 vdd_l7-supply = <&S7A>;
4208};
4209
4210&L1P {
4211 regulator-min-microvolt = <1100000>;
4212 regulator-max-microvolt = <1300000>;
4213 qcom,min-dropout-voltage = <56000>;
4214};
4215
4216&L2P {
4217 regulator-min-microvolt = <950000>;
4218 regulator-max-microvolt = <1150000>;
4219 qcom,min-dropout-voltage = <88000>;
4220};
4221
4222&L3P {
4223 regulator-min-microvolt = <2700000>;
4224 regulator-max-microvolt = <2900000>;
4225 qcom,min-dropout-voltage = <96000>;
4226};
4227
4228&L4P {
4229 regulator-min-microvolt = <2700000>;
4230 regulator-max-microvolt = <2900000>;
4231 qcom,min-dropout-voltage = <136000>;
4232};
4233
4234&L5P {
4235 regulator-min-microvolt = <2700000>;
4236 regulator-max-microvolt = <2900000>;
4237 qcom,min-dropout-voltage = <240000>;
4238};
4239
4240&L6P {
4241 regulator-min-microvolt = <2700000>;
4242 regulator-max-microvolt = <2900000>;
4243 qcom,min-dropout-voltage = <168000>;
4244};
4245
4246&L7P {
4247 regulator-min-microvolt = <1650000>;
4248 regulator-max-microvolt = <1800000>;
4249 qcom,min-dropout-voltage = <112000>;
4250};
4251
4252&qupv3_se4_2uart {
4253 status = "ok";
4254};
4255
4256&qupv3_se3_4uart {
4257 status = "ok";
4258};
4259
4260&pm6125_vadc {
4261 #address-cells = <1>;
4262 #size-cells = <0>;
4263 pinctrl-names = "default";
4264 pinctrl-0 = <&camera_therm_default &emmc_therm_default>;
4265
4266 pa_therm0 {
4267 reg = <ADC_AMUX_THM1_PU2>;
4268 label = "pa_therm0";
4269 qcom,ratiometric;
4270 qcom,hw-settle-time = <200>;
4271 qcom,pre-scaling = <1 1>;
4272 };
4273
4274 quiet_therm {
4275 reg = <ADC_AMUX_THM2_PU2>;
4276 label = "quiet_therm";
4277 qcom,ratiometric;
4278 qcom,hw-settle-time = <200>;
4279 qcom,pre-scaling = <1 1>;
4280 };
4281
4282 camera_flash_therm {
4283 reg = <ADC_GPIO1_PU2>;
4284 label = "camera_flash_therm";
4285 qcom,ratiometric;
4286 qcom,hw-settle-time = <200>;
4287 qcom,pre-scaling = <1 1>;
4288 };
4289
4290 emmc_ufs_therm {
4291 reg = <ADC_GPIO2_PU2>;
4292 label = "emmc_ufs_therm";
4293 qcom,ratiometric;
4294 qcom,hw-settle-time = <200>;
4295 qcom,pre-scaling = <1 1>;
4296 };
4297};
4298
4299&pm6125_gpios {
4300 camera_therm {
4301 camera_therm_default: camera_therm_default {
4302 pins = "gpio3";
4303 bias-high-impedance;
4304 };
4305 };
4306
4307 emmc_therm {
4308 emmc_therm_default: emmc_therm_default {
4309 pins = "gpio4";
4310 bias-high-impedance;
4311 };
4312 };
4313
4314};
4315
4316&spmi_bus {
4317 qcom,pm6125@0 {
4318 pm6125_adc_tm_iio: adc_tm@3400 {
4319 compatible = "qcom,adc-tm5-iio";
4320 reg = <0x3400 0x100>;
4321 #thermal-sensor-cells = <1>;
4322 #address-cells = <1>;
4323 #size-cells = <0>;
4324 io-channels = <&pm6125_vadc ADC_GPIO1_PU2>,
4325 <&pm6125_vadc ADC_GPIO2_PU2>;
4326
4327 camera_flash_therm {
4328 reg = <ADC_GPIO1_PU2>;
4329 qcom,ratiometric;
4330 qcom,hw-settle-time = <200>;
4331 };
4332
4333 emmc_ufs_therm {
4334 reg = <ADC_GPIO2_PU2>;
4335 qcom,ratiometric;
4336 qcom,hw-settle-time = <200>;
4337 };
4338 };
4339 };
4340};
4341
4342&pm6125_adc_tm {
4343 #address-cells = <1>;
4344 #size-cells = <0>;
4345 io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>,
4346 <&pm6125_vadc ADC_AMUX_THM2_PU2>,
4347 <&pm6125_vadc ADC_XO_THERM_PU2>;
4348
4349 /* Channel nodes */
4350 pa_therm0 {
4351 reg = <ADC_AMUX_THM1_PU2>;
4352 qcom,ratiometric;
4353 qcom,hw-settle-time = <200>;
4354 };
4355
4356 quiet_therm {
4357 reg = <ADC_AMUX_THM2_PU2>;
4358 qcom,ratiometric;
4359 qcom,hw-settle-time = <200>;
4360 };
4361
4362 xo_therm {
4363 reg = <ADC_XO_THERM_PU2>;
4364 qcom,ratiometric;
4365 qcom,hw-settle-time = <200>;
4366 };
4367};
4368
4369&msm_vidc {
4370 qcom,cx-ipeak-data = <&cx_ipeak_lm 6>;
4371 qcom,clock-freq-threshold = <300000000>;
4372};
4373
4374#include "bengal-thermal.dtsi"
4375#include "camera/khaje-camera.dtsi"
4376#include "msm-rdbg.dtsi"
4377
4378&cxip_cdev {
4379 status = "disabled";
4380};
4381
4382&rpm_bus {
4383 rpm_smd_cdev: rpm-smd-cdev {
4384 compatible = "qcom,rpm-smd-cooling-device";
4385 #cooling-cells = <2>;
4386 };
4387};
4388
4389&thermal_zones {
4390 mapss-lowc {
4391 cooling-maps {
4392 rpm_smd_vdd_cdev {
4393 trip = <&mapss_cap_trip>;
4394 cooling-device = <&rpm_smd_cdev 2 2>;
4395 };
4396 };
4397 };
4398
4399 camera-lowc {
4400 cooling-maps {
4401 rpm_smd_vdd_cdev {
4402 trip = <&camera_cap_trip>;
4403 cooling-device = <&rpm_smd_cdev 2 2>;
4404 };
4405 };
4406 };
4407};