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gerrit-public.fairphone.software / kernel / msm-4.19 / 9b0224459fa8ee7c60d16a0b710ebf039da9f365 / . / arch / arm64 / boot / dts / vendor / qcom / kona-audio-overlay-ar.dtsi
blob: 8cc61d5db1f466e28de9937ea363ca377457d7ee [file] [log] [blame]
Luca Weiss9b022442023-04-14 14:47:36 +0200[diff] [blame^]1#include "kona-lpi-ar.dtsi"
2#include "kona-va-bolero-ar.dtsi"
3
4&bolero_ar {
5 qcom,num-macros = <4>;
6 bolero-clk-rsc-mngr-ar {
7 compatible = "qcom,bolero-clk-rsc-mngr";
8 qcom,fs-gen-sequence = <0x3000 0x1>,
9 <0x3004 0x1>, <0x3080 0x2>;
10 qcom,rx_mclk_mode_muxsel = <0x033240D8>;
11 qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
12 qcom,va_mclk_mode_muxsel = <0x033A0000>;
13 clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
14 "wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk";
15 clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
16 <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
17 <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
18 <&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
19 };
20
21 tx_macro_ar: tx-macro-ar@3220000 {
22 compatible = "qcom,tx-macro";
23 reg = <0x3220000 0x0>;
24 clock-names = "tx_core_clk", "tx_npl_clk";
25 clocks = <&clock_audio_tx_1 0>,
26 <&clock_audio_tx_2 0>;
27 qcom,tx-swr-gpios = <&tx_swr_gpios_ar>;
28 qcom,tx-dmic-sample-rate = <2400000>;
29 swr_ar2: tx_swr_master_ar {
30 compatible = "qcom,swr-mstr";
31 #address-cells = <2>;
32 #size-cells = <0>;
33 clock-names = "lpass_core_hw_vote",
34 "lpass_audio_hw_vote";
35 clocks = <&lpass_core_hw_vote_ar 0>,
36 <&lpass_audio_hw_vote_ar 0>;
37 qcom,swr-master-version = <0x01050001>;
38 qcom,swr_master_id = <3>;
39 qcom,mipi-sdw-block-packing-mode = <1>;
40 swrm-io-base = <0x3230000 0x0>;
41 interrupts-extended =
42 <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
43 <&pdc 109 IRQ_TYPE_LEVEL_HIGH>;
44 interrupt-names = "swr_master_irq", "swr_wake_irq";
45 qcom,swr-wakeup-required = <1>;
46 qcom,swr-num-ports = <5>;
47 qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,
48 <2 ADC1 0x1>, <2 ADC2 0x2>,
49 <3 ADC3 0x1>, <3 ADC4 0x2>,
50 <4 DMIC0 0x1>, <4 DMIC1 0x2>,
51 <4 DMIC2 0x4>, <4 DMIC3 0x8>,
52 <5 DMIC4 0x1>, <5 DMIC5 0x2>,
53 <5 DMIC6 0x4>, <5 DMIC7 0x8>;
54 qcom,swr-num-dev = <1>;
55 qcom,swr-clock-stop-mode0 = <1>;
56 qcom,swr-mstr-irq-wakeup-capable = <1>;
57 wcd938x_tx_slave_ar: wcd938x-tx-slave_ar {
58 compatible = "qcom,wcd938x-slave";
59 reg = <0x0D 0x01170223>;
60 };
61 };
62 };
63
64 rx_macro_ar: rx-macro-ar@3200000 {
65 compatible = "qcom,rx-macro";
66 reg = <0x3200000 0x0>;
67 clock-names = "rx_core_clk", "rx_npl_clk";
68 clocks = <&clock_audio_rx_1 0>,
69 <&clock_audio_rx_2 0>;
70 qcom,rx-swr-gpios = <&rx_swr_gpios_ar>;
71 qcom,rx_mclk_mode_muxsel = <0x033240D8>;
72 qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
73 qcom,default-clk-id = <TX_CORE_CLK>;
74 swr_ar1: rx_swr_master_ar {
75 compatible = "qcom,swr-mstr";
76 #address-cells = <2>;
77 #size-cells = <0>;
78 clock-names = "lpass_core_hw_vote",
79 "lpass_audio_hw_vote";
80 clocks = <&lpass_core_hw_vote_ar 0>,
81 <&lpass_audio_hw_vote_ar 0>;
82 qcom,swr-master-version = <0x01050001>;
83 qcom,swr_master_id = <2>;
84 qcom,mipi-sdw-block-packing-mode = <1>;
85 swrm-io-base = <0x3210000 0x0>;
86 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
87 interrupt-names = "swr_master_irq";
88 qcom,swr-num-ports = <5>;
89 qcom,disable-div2-clk-switch = <1>;
90 qcom,swr-port-mapping = <1 HPH_L 0x1>,
91 <1 HPH_R 0x2>, <2 CLSH 0x1>,
92 <3 COMP_L 0x1>, <3 COMP_R 0x2>,
93 <4 LO 0x1>, <5 DSD_L 0x1>,
94 <5 DSD_R 0x2>;
95 qcom,swr-num-dev = <1>;
96 qcom,swr-clock-stop-mode0 = <1>;
97 wcd938x_rx_slave_ar: wcd938x-rx-slave-ar {
98 compatible = "qcom,wcd938x-slave";
99 reg = <0x0D 0x01170224>;
100 };
101 };
102 };
103
104 wsa_macro_ar: wsa-macro-ar@3240000 {
105 compatible = "qcom,wsa-macro";
106 reg = <0x3240000 0x0>;
107 clock-names = "wsa_core_clk", "wsa_npl_clk";
108 clocks = <&clock_audio_wsa_1 0>,
109 <&clock_audio_wsa_2 0>;
110 qcom,wsa-swr-gpios = <&wsa_swr_gpios_ar>;
111 qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
112 qcom,default-clk-id = <TX_CORE_CLK>;
113 swr_ar0: wsa_swr_master_ar {
114 compatible = "qcom,swr-mstr";
115 #address-cells = <2>;
116 #size-cells = <0>;
117 clock-names = "lpass_core_hw_vote",
118 "lpass_audio_hw_vote";
119 clocks = <&lpass_core_hw_vote_ar 0>,
120 <&lpass_audio_hw_vote_ar 0>;
121 qcom,swr-master-version = <0x01050001>;
122 qcom,swr_master_id = <1>;
123 qcom,mipi-sdw-block-packing-mode = <0>;
124 swrm-io-base = <0x3250000 0x0>;
125 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
126 interrupt-names = "swr_master_irq";
127 qcom,swr-num-ports = <8>;
128 qcom,swr-port-mapping = <1 SPKR_L 0x1>,
129 <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
130 <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
131 <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
132 <8 SPKR_R_VI 0x3>;
133 qcom,swr-num-dev = <2>;
134 wsa881x_0211_ar: wsa881x_ar@20170211 {
135 compatible = "qcom,wsa881x";
136 reg = <0x10 0x20170211>;
137 qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
138 qcom,bolero-handle = <&bolero_ar>;
139 };
140
141 wsa881x_0212_ar: wsa881x_ar@20170212 {
142 compatible = "qcom,wsa881x";
143 reg = <0x10 0x20170212>;
144 qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
145 qcom,bolero-handle = <&bolero_ar>;
146 };
147
148 wsa881x_0213_ar: wsa881x_ar@21170213 {
149 compatible = "qcom,wsa881x";
150 reg = <0x10 0x21170213>;
151 qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
152 qcom,bolero-handle = <&bolero_ar>;
153 };
154
155 wsa881x_0214_ar: wsa881x_ar@21170214 {
156 compatible = "qcom,wsa881x";
157 reg = <0x10 0x21170214>;
158 qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
159 qcom,bolero-handle = <&bolero_ar>;
160 };
161 };
162
163 };
164
165 wcd938x_codec_ar: wcd938x-codec-ar {
166 compatible = "qcom,wcd938x-codec";
167 qcom,split-codec = <1>;
168 qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
169 <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
170 <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
171 <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
172 <4 DSD_R 0x2 0 DSD_R>;
173 qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
174 <0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,
175 <1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,
176 <2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,
177 <2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,
178 <3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,
179 <3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;
180
181 qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
182 qcom,rx-slave = <&wcd938x_rx_slave_ar>;
183 qcom,tx-slave = <&wcd938x_tx_slave_ar>;
184
185 cdc-vdd-rxtx-supply = <&S4A>;
186 qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
187 qcom,cdc-vdd-rxtx-current = <30000>;
188
189 cdc-vddio-supply = <&S4A>;
190 qcom,cdc-vddio-voltage = <1800000 1800000>;
191 qcom,cdc-vddio-current = <30000>;
192
193 cdc-vdd-buck-supply = <&S4A>;
194 qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
195 qcom,cdc-vdd-buck-current = <650000>;
196
197 cdc-vdd-mic-bias-supply = <&BOB>;
198 qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
199 qcom,cdc-vdd-mic-bias-current = <30000>;
200
201 qcom,cdc-micbias1-mv = <1800>;
202 qcom,cdc-micbias2-mv = <1800>;
203 qcom,cdc-micbias3-mv = <1800>;
204 qcom,cdc-micbias4-mv = <1800>;
205
206 qcom,cdc-static-supplies = "cdc-vdd-rxtx",
207 "cdc-vddio",
208 "cdc-vdd-buck",
209 "cdc-vdd-mic-bias";
210 };
211
212};
213
214&kona_snd_ar {
215 qcom,model = "kona-mtp-snd-card";
216 qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
217 qcom,mi2s-tdm-is-hw-vote-needed = <1>, <0>, <1>, <0>, <0>, <0>;
218 qcom,wcn-bt = <0>;
219 qcom,ext-disp-audio-rx = <1>;
220 qcom,tdm-max-slots = <8>;
221 qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
222 qcom,mi2s-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
223 qcom,audio-routing =
224 "AMIC1", "MIC BIAS1",
225 "MIC BIAS1", "Analog Mic1",
226 "AMIC2", "MIC BIAS2",
227 "MIC BIAS2", "Analog Mic2",
228 "AMIC3", "MIC BIAS3",
229 "MIC BIAS3", "Analog Mic3",
230 "AMIC4", "MIC BIAS3",
231 "MIC BIAS3", "Analog Mic4",
232 "AMIC5", "MIC BIAS4",
233 "MIC BIAS4", "Analog Mic5",
234 "TX DMIC0", "MIC BIAS3",
235 "MIC BIAS3", "Digital Mic0",
236 "TX DMIC1", "MIC BIAS3",
237 "MIC BIAS3", "Digital Mic1",
238 "TX DMIC2", "MIC BIAS1",
239 "MIC BIAS1", "Digital Mic2",
240 "TX DMIC3", "MIC BIAS1",
241 "MIC BIAS1", "Digital Mic3",
242 "TX DMIC4", "MIC BIAS4",
243 "MIC BIAS4", "Digital Mic4",
244 "TX DMIC5", "MIC BIAS4",
245 "MIC BIAS4", "Digital Mic5",
246 "IN1_HPHL", "HPHL_OUT",
247 "IN2_HPHR", "HPHR_OUT",
248 "IN3_AUX", "AUX_OUT",
249 "TX SWR_ADC0", "ADC1_OUTPUT",
250 "TX SWR_ADC1", "ADC2_OUTPUT",
251 "TX SWR_ADC2", "ADC3_OUTPUT",
252 "TX SWR_ADC3", "ADC4_OUTPUT",
253 "TX SWR_DMIC0", "DMIC1_OUTPUT",
254 "TX SWR_DMIC1", "DMIC2_OUTPUT",
255 "TX SWR_DMIC2", "DMIC3_OUTPUT",
256 "TX SWR_DMIC3", "DMIC4_OUTPUT",
257 "TX SWR_DMIC4", "DMIC5_OUTPUT",
258 "TX SWR_DMIC5", "DMIC6_OUTPUT",
259 "TX SWR_DMIC6", "DMIC7_OUTPUT",
260 "TX SWR_DMIC7", "DMIC8_OUTPUT",
261 "WSA SRC0_INP", "SRC0",
262 "WSA_TX DEC0_INP", "TX DEC0 MUX",
263 "WSA_TX DEC1_INP", "TX DEC1 MUX",
264 "RX_TX DEC0_INP", "TX DEC0 MUX",
265 "RX_TX DEC1_INP", "TX DEC1 MUX",
266 "RX_TX DEC2_INP", "TX DEC2 MUX",
267 "RX_TX DEC3_INP", "TX DEC3 MUX",
268 "SpkrLeft IN", "WSA_SPK1 OUT",
269 "SpkrRight IN", "WSA_SPK2 OUT",
270 "VA_AIF1 CAP", "VA_SWR_CLK",
271 "VA_AIF2 CAP", "VA_SWR_CLK",
272 "VA_AIF3 CAP", "VA_SWR_CLK",
273 "VA MIC BIAS3", "Digital Mic0",
274 "VA MIC BIAS3", "Digital Mic1",
275 "VA MIC BIAS1", "Digital Mic2",
276 "VA MIC BIAS1", "Digital Mic3",
277 "VA MIC BIAS4", "Digital Mic4",
278 "VA MIC BIAS4", "Digital Mic5",
279 "VA DMIC0", "VA MIC BIAS3",
280 "VA DMIC1", "VA MIC BIAS3",
281 "VA DMIC2", "VA MIC BIAS1",
282 "VA DMIC3", "VA MIC BIAS1",
283 "VA DMIC4", "VA MIC BIAS4",
284 "VA DMIC5", "VA MIC BIAS4",
285 "VA SWR_ADC0", "VA_SWR_CLK",
286 "VA SWR_ADC1", "VA_SWR_CLK",
287 "VA SWR_ADC2", "VA_SWR_CLK",
288 "VA SWR_ADC3", "VA_SWR_CLK",
289 "VA SWR_MIC0", "VA_SWR_CLK",
290 "VA SWR_MIC1", "VA_SWR_CLK",
291 "VA SWR_MIC2", "VA_SWR_CLK",
292 "VA SWR_MIC3", "VA_SWR_CLK",
293 "VA SWR_MIC4", "VA_SWR_CLK",
294 "VA SWR_MIC5", "VA_SWR_CLK",
295 "VA SWR_MIC6", "VA_SWR_CLK",
296 "VA SWR_MIC7", "VA_SWR_CLK",
297 "VA SWR_ADC0", "ADC1_OUTPUT",
298 "VA SWR_ADC1", "ADC2_OUTPUT",
299 "VA SWR_ADC2", "ADC3_OUTPUT",
300 "VA SWR_ADC3", "ADC4_OUTPUT",
301 "VA SWR_MIC0", "DMIC1_OUTPUT",
302 "VA SWR_MIC1", "DMIC2_OUTPUT",
303 "VA SWR_MIC2", "DMIC3_OUTPUT",
304 "VA SWR_MIC3", "DMIC4_OUTPUT",
305 "VA SWR_MIC4", "DMIC5_OUTPUT",
306 "VA SWR_MIC5", "DMIC6_OUTPUT",
307 "VA SWR_MIC6", "DMIC7_OUTPUT",
308 "VA SWR_MIC7", "DMIC8_OUTPUT";
309 qcom,msm-mbhc-hphl-swh = <1>;
310 qcom,msm-mbhc-gnd-swh = <1>;
311 qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios_ar>;
312 qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios_ar>;
313 qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios_ar>;
314 asoc-codec = <&stub_codec>, <&bolero_ar>, <&ext_disp_audio_codec>;
315 asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
316 "msm-ext-disp-audio-codec-rx";
317 qcom,wsa-max-devs = <2>;
318 qcom,wsa-devs = <&wsa881x_0211_ar>, <&wsa881x_0212_ar>,
319 <&wsa881x_0213_ar>, <&wsa881x_0214_ar>;
320 qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
321 "SpkrLeft", "SpkrRight";
322 qcom,codec-max-aux-devs = <1>;
323 qcom,codec-aux-devs = <&wcd938x_codec_ar>;
324 qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm_ar>,
325 <&bolero_ar>;
326};
327
328&spf_core_platform {
329 cdc_dmic01_gpios_ar: cdc_dmic01_pinctrl_ar {
330 compatible = "qcom,msm-cdc-pinctrl";
331 pinctrl-names = "aud_active", "aud_sleep";
332 pinctrl-0 = <&cdc_dmic01_clk_active_ar &cdc_dmic01_data_active_ar>;
333 pinctrl-1 = <&cdc_dmic01_clk_sleep_ar &cdc_dmic01_data_sleep_ar>;
334 qcom,lpi-gpios;
335 };
336
337 cdc_dmic23_gpios_ar: cdc_dmic23_pinctrl_ar {
338 compatible = "qcom,msm-cdc-pinctrl";
339 pinctrl-names = "aud_active", "aud_sleep";
340 pinctrl-0 = <&cdc_dmic23_clk_active_ar &cdc_dmic23_data_active_ar>;
341 pinctrl-1 = <&cdc_dmic23_clk_sleep_ar &cdc_dmic23_data_sleep_ar>;
342 qcom,lpi-gpios;
343 };
344
345 cdc_dmic45_gpios_ar: cdc_dmic45_pinctrl_ar {
346 compatible = "qcom,msm-cdc-pinctrl";
347 pinctrl-names = "aud_active", "aud_sleep";
348 pinctrl-0 = <&cdc_dmic45_clk_active_ar &cdc_dmic45_data_active_ar>;
349 pinctrl-1 = <&cdc_dmic45_clk_sleep_ar &cdc_dmic45_data_sleep_ar>;
350 qcom,lpi-gpios;
351 qcom,tlmm-gpio = <158>;
352 };
353
354 wsa_swr_gpios_ar: wsa_swr_clk_data_pinctrl_ar {
355 compatible = "qcom,msm-cdc-pinctrl";
356 pinctrl-names = "aud_active", "aud_sleep";
357 pinctrl-0 = <&wsa_swr_clk_active_ar &wsa_swr_data_active_ar>;
358 pinctrl-1 = <&wsa_swr_clk_sleep_ar &wsa_swr_data_sleep_ar>;
359 qcom,lpi-gpios;
360 };
361
362 rx_swr_gpios_ar: rx_swr_clk_data_pinctrl_ar {
363 compatible = "qcom,msm-cdc-pinctrl";
364 pinctrl-names = "aud_active", "aud_sleep";
365 pinctrl-0 = <&rx_swr_clk_active_ar &rx_swr_data_active_ar
366 &rx_swr_data1_active_ar>;
367 pinctrl-1 = <&rx_swr_clk_sleep_ar &rx_swr_data_sleep_ar
368 &rx_swr_data1_sleep_ar>;
369 qcom,lpi-gpios;
370 };
371
372 tx_swr_gpios_ar: tx_swr_clk_data_pinctrl_ar {
373 compatible = "qcom,msm-cdc-pinctrl";
374 pinctrl-names = "aud_active", "aud_sleep";
375 pinctrl-0 = <&tx_swr_clk_active_ar &tx_swr_data1_active_ar
376 &tx_swr_data2_active_ar>;
377 pinctrl-1 = <&tx_swr_clk_sleep_ar &tx_swr_data1_sleep_ar
378 &tx_swr_data2_sleep_ar>;
379 qcom,lpi-gpios;
380 qcom,tlmm-gpio = <147>;
381 };
382};