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gerrit-public.fairphone.software / kernel / msm-4.19 / 9b0224459fa8ee7c60d16a0b710ebf039da9f365 / . / arch / arm64 / boot / dts / vendor / qcom / kona-iot-rb5-audio.dtsi
blob: 7d658cf4cb11ce0c3e7b4608114cf0329dd6a5e2 [file] [log] [blame]
Luca Weiss9b022442023-04-14 14:47:36 +0200[diff] [blame^]1
2&spkr_2_sd_n_sleep {
3 mux {
4 pins = "gpio130";
5 };
6
7 config {
8 pins = "gpio130";
9 };
10};
11
12&spkr_2_sd_n_active {
13 mux {
14 pins = "gpio130";
15 };
16
17 config {
18 pins = "gpio130";
19 };
20};
21
22
23&bolero {
24 qcom,num-macros = <4>;
25 bolero-clk-rsc-mngr {
26 compatible = "qcom,bolero-clk-rsc-mngr";
27 qcom,fs-gen-sequence = <0x3000 0x1>,
28 <0x3004 0x1>, <0x3080 0x2>;
29 qcom,rx_mclk_mode_muxsel = <0x033240D8>;
30 qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
31 qcom,va_mclk_mode_muxsel = <0x033A0000>;
32 clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
33 "wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk";
34 clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
35 <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
36 <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
37 <&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
38 };
39
40 tx_macro: tx-macro@3220000 {
41 compatible = "qcom,tx-macro";
42 reg = <0x3220000 0x0>;
43 clock-names = "tx_core_clk", "tx_npl_clk";
44 clocks = <&clock_audio_tx_1 0>,
45 <&clock_audio_tx_2 0>;
46 qcom,tx-swr-gpios = <&tx_swr_gpios>;
47 qcom,tx-dmic-sample-rate = <2400000>;
48 swr2: tx_swr_master {
49 status = "disabled";
50 compatible = "qcom,swr-mstr";
51 #address-cells = <2>;
52 #size-cells = <0>;
53 clock-names = "lpass_core_hw_vote",
54 "lpass_audio_hw_vote";
55 clocks = <&lpass_core_hw_vote 0>,
56 <&lpass_audio_hw_vote 0>;
57 qcom,swr_master_id = <3>;
58 qcom,mipi-sdw-block-packing-mode = <1>;
59 swrm-io-base = <0x3230000 0x0>;
60 interrupts-extended =
61 <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
62 <&pdc 109 IRQ_TYPE_LEVEL_HIGH>;
63 interrupt-names = "swr_master_irq", "swr_wake_irq";
64 qcom,swr-wakeup-required = <1>;
65 qcom,swr-num-ports = <5>;
66 qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,
67 <2 ADC1 0x1>, <2 ADC2 0x2>,
68 <3 ADC3 0x1>, <3 ADC4 0x2>,
69 <4 DMIC0 0x1>, <4 DMIC1 0x2>,
70 <4 DMIC2 0x4>, <4 DMIC3 0x8>,
71 <5 DMIC4 0x1>, <5 DMIC5 0x2>,
72 <5 DMIC6 0x4>, <5 DMIC7 0x8>;
73 qcom,swr-num-dev = <1>;
74 qcom,swr-clock-stop-mode0 = <1>;
75 qcom,swr-mstr-irq-wakeup-capable = <1>;
76 wcd938x_tx_slave: wcd938x-tx-slave {
77 compatible = "qcom,wcd938x-slave";
78 reg = <0x0D 0x01170223>;
79 };
80 };
81 };
82
83 rx_macro: rx-macro@3200000 {
84 compatible = "qcom,rx-macro";
85 reg = <0x3200000 0x0>;
86 clock-names = "rx_core_clk", "rx_npl_clk";
87 clocks = <&clock_audio_rx_1 0>,
88 <&clock_audio_rx_2 0>;
89 qcom,rx-swr-gpios = <&rx_swr_gpios>;
90 qcom,rx_mclk_mode_muxsel = <0x033240D8>;
91 qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
92 qcom,default-clk-id = <TX_CORE_CLK>;
93 swr1: rx_swr_master {
94 status = "disabled";
95 compatible = "qcom,swr-mstr";
96 #address-cells = <2>;
97 #size-cells = <0>;
98 clock-names = "lpass_core_hw_vote",
99 "lpass_audio_hw_vote";
100 clocks = <&lpass_core_hw_vote 0>,
101 <&lpass_audio_hw_vote 0>;
102 qcom,swr_master_id = <2>;
103 qcom,mipi-sdw-block-packing-mode = <1>;
104 swrm-io-base = <0x3210000 0x0>;
105 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
106 interrupt-names = "swr_master_irq";
107 qcom,swr-num-ports = <5>;
108 qcom,swr-port-mapping = <1 HPH_L 0x1>,
109 <1 HPH_R 0x2>, <2 CLSH 0x1>,
110 <3 COMP_L 0x1>, <3 COMP_R 0x2>,
111 <4 LO 0x1>, <5 DSD_L 0x1>,
112 <5 DSD_R 0x2>;
113 qcom,swr-num-dev = <1>;
114 qcom,swr-clock-stop-mode0 = <1>;
115 wcd938x_rx_slave: wcd938x-rx-slave {
116 compatible = "qcom,wcd938x-slave";
117 reg = <0x0D 0x01170224>;
118 };
119 };
120 };
121
122 wsa_macro: wsa-macro@3240000 {
123 compatible = "qcom,wsa-macro";
124 reg = <0x3240000 0x0>;
125 clock-names = "wsa_core_clk", "wsa_npl_clk";
126 clocks = <&clock_audio_wsa_1 0>,
127 <&clock_audio_wsa_2 0>;
128 qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
129 qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
130 qcom,default-clk-id = <TX_CORE_CLK>;
131 swr0: wsa_swr_master {
132 compatible = "qcom,swr-mstr";
133 #address-cells = <2>;
134 #size-cells = <0>;
135 clock-names = "lpass_core_hw_vote",
136 "lpass_audio_hw_vote";
137 clocks = <&lpass_core_hw_vote 0>,
138 <&lpass_audio_hw_vote 0>;
139 qcom,swr_master_id = <1>;
140 qcom,mipi-sdw-block-packing-mode = <0>;
141 swrm-io-base = <0x3250000 0x0>;
142 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
143 interrupt-names = "swr_master_irq";
144 qcom,swr-num-ports = <8>;
145 qcom,swr-port-mapping = <1 SPKR_L 0x1>,
146 <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
147 <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
148 <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
149 <8 SPKR_R_VI 0x3>;
150 qcom,swr-num-dev = <2>;
151 wsa881x_0211: wsa881x@20170211 {
152 compatible = "qcom,wsa881x";
153 reg = <0x10 0x20170211>;
154 qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
155 qcom,bolero-handle = <&bolero>;
156 };
157
158 wsa881x_0212: wsa881x@20170212 {
159 compatible = "qcom,wsa881x";
160 reg = <0x10 0x20170212>;
161 qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
162 qcom,bolero-handle = <&bolero>;
163 };
164
165 wsa881x_0213: wsa881x@21170213 {
166 compatible = "qcom,wsa881x";
167 reg = <0x10 0x21170213>;
168 qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
169 qcom,bolero-handle = <&bolero>;
170 };
171
172 wsa881x_0214: wsa881x@21170214 {
173 compatible = "qcom,wsa881x";
174 reg = <0x10 0x21170214>;
175 qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
176 qcom,bolero-handle = <&bolero>;
177 };
178 };
179
180 };
181
182 wcd938x_codec: wcd938x-codec {
183 status = "disabled";
184 compatible = "qcom,wcd938x-codec";
185 qcom,split-codec = <1>;
186 qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
187 <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
188 <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
189 <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
190 <4 DSD_R 0x2 0 DSD_R>;
191 qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
192 <0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,
193 <1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,
194 <2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,
195 <2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,
196 <3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,
197 <3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;
198
199 qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
200 qcom,rx-slave = <&wcd938x_rx_slave>;
201 qcom,tx-slave = <&wcd938x_tx_slave>;
202
203 cdc-vdd-rxtx-supply = <&S4A>;
204 qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
205 qcom,cdc-vdd-rxtx-current = <30000>;
206
207 cdc-vddio-supply = <&S4A>;
208 qcom,cdc-vddio-voltage = <1800000 1800000>;
209 qcom,cdc-vddio-current = <30000>;
210
211 cdc-vdd-buck-supply = <&S4A>;
212 qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
213 qcom,cdc-vdd-buck-current = <650000>;
214
215 cdc-vdd-mic-bias-supply = <&BOB>;
216 qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
217 qcom,cdc-vdd-mic-bias-current = <30000>;
218
219 qcom,cdc-micbias1-mv = <1800>;
220 qcom,cdc-micbias2-mv = <1800>;
221 qcom,cdc-micbias3-mv = <1800>;
222 qcom,cdc-micbias4-mv = <1800>;
223
224 qcom,cdc-static-supplies = "cdc-vdd-rxtx",
225 "cdc-vddio",
226 "cdc-vdd-buck",
227 "cdc-vdd-mic-bias";
228 };
229
230};
231
232&kona_snd {
233 qcom,model = "kona-iot-snd-card";
234 qcom,audio-routing =
235 "TX DMIC0", "Digital Mic0",
236 "TX DMIC1", "Digital Mic1",
237 "TX DMIC2", "Digital Mic2",
238 "TX DMIC3", "Digital Mic3",
239 "TX DMIC4", "Digital Mic4",
240 "TX DMIC5", "Digital Mic5",
241 "IN1_HPHL", "HPHL_OUT",
242 "IN2_HPHR", "HPHR_OUT",
243 "IN3_AUX", "AUX_OUT",
244 "TX SWR_ADC0", "ADC1_OUTPUT",
245 "TX SWR_ADC1", "ADC2_OUTPUT",
246 "TX SWR_ADC2", "ADC3_OUTPUT",
247 "TX SWR_ADC3", "ADC4_OUTPUT",
248 "TX SWR_DMIC0", "DMIC1_OUTPUT",
249 "TX SWR_DMIC1", "DMIC2_OUTPUT",
250 "TX SWR_DMIC2", "DMIC3_OUTPUT",
251 "TX SWR_DMIC3", "DMIC4_OUTPUT",
252 "TX SWR_DMIC4", "DMIC5_OUTPUT",
253 "TX SWR_DMIC5", "DMIC6_OUTPUT",
254 "TX SWR_DMIC6", "DMIC7_OUTPUT",
255 "TX SWR_DMIC7", "DMIC8_OUTPUT",
256 "WSA SRC0_INP", "SRC0",
257 "WSA_TX DEC0_INP", "TX DEC0 MUX",
258 "WSA_TX DEC1_INP", "TX DEC1 MUX",
259 "RX_TX DEC0_INP", "TX DEC0 MUX",
260 "RX_TX DEC1_INP", "TX DEC1 MUX",
261 "RX_TX DEC2_INP", "TX DEC2 MUX",
262 "RX_TX DEC3_INP", "TX DEC3 MUX",
263 "SpkrRight IN", "WSA_SPK2 OUT",
264 "VA_AIF1 CAP", "VA_SWR_CLK",
265 "VA_AIF2 CAP", "VA_SWR_CLK",
266 "VA_AIF3 CAP", "VA_SWR_CLK",
267 "VA DMIC0", "Digital Mic0",
268 "VA DMIC1", "Digital Mic1",
269 "VA DMIC2", "Digital Mic2",
270 "VA DMIC3", "Digital Mic3",
271 "VA DMIC4", "Digital Mic4",
272 "VA DMIC5", "Digital Mic5",
273 "VA SWR_ADC1", "VA_SWR_CLK",
274 "VA SWR_MIC0", "VA_SWR_CLK",
275 "VA SWR_MIC1", "VA_SWR_CLK",
276 "VA SWR_MIC2", "VA_SWR_CLK",
277 "VA SWR_MIC3", "VA_SWR_CLK",
278 "VA SWR_MIC4", "VA_SWR_CLK",
279 "VA SWR_MIC5", "VA_SWR_CLK",
280 "VA SWR_MIC6", "VA_SWR_CLK",
281 "VA SWR_MIC7", "VA_SWR_CLK",
282 "VA SWR_MIC0", "DMIC1_OUTPUT",
283 "VA SWR_MIC1", "DMIC2_OUTPUT",
284 "VA SWR_MIC2", "DMIC3_OUTPUT",
285 "VA SWR_MIC3", "DMIC4_OUTPUT",
286 "VA SWR_MIC4", "DMIC5_OUTPUT",
287 "VA SWR_MIC5", "DMIC6_OUTPUT",
288 "VA SWR_MIC6", "DMIC7_OUTPUT",
289 "VA SWR_MIC7", "DMIC8_OUTPUT",
290 "VA SWR_ADC1", "ADC2_OUTPUT";
291 qcom,msm-mbhc-usbc-audio-supported = <1>;
292 qcom,msm-mbhc-hphl-swh = <0>;
293 qcom,msm-mbhc-gnd-swh = <0>;
294 qcom,wsa-max-devs = <2>;
295 qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
296 <&wsa881x_0213>, <&wsa881x_0214>;
297 qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
298 "SpkrLeft", "SpkrRight";
299 qcom,codec-max-aux-devs = <0>;
300};