blob: 11b8f950b3759b7888170f3690cc1638ee2f1435 [file] [log] [blame]
Luca Weiss9b022442023-04-14 14:47:36 +02001#include <dt-bindings/interrupt-controller/arm-gic.h>
2#include <dt-bindings/soc/qcom,ipcc.h>
3
4&soc {
5
6 qcom,smp2p-adsp {
7 compatible = "qcom,smp2p";
8 qcom,smem = <443>, <429>;
9 interrupt-parent = <&ipcc_mproc>;
10 interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
11 IRQ_TYPE_EDGE_RISING>;
12 mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
13 IPCC_MPROC_SIGNAL_SMP2P>;
14 qcom,local-pid = <0>;
15 qcom,remote-pid = <2>;
16
17 adsp_smp2p_out: master-kernel {
18 qcom,entry-name = "master-kernel";
19 #qcom,smem-state-cells = <1>;
20 };
21
22 adsp_smp2p_in: slave-kernel {
23 qcom,entry-name = "slave-kernel";
24 interrupt-controller;
25 #interrupt-cells = <2>;
26 };
27
28 smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
29 qcom,entry-name = "rdbg";
30 #qcom,smem-state-cells = <1>;
31 };
32
33 smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
34 qcom,entry-name = "rdbg";
35 interrupt-controller;
36 #interrupt-cells = <2>;
37 };
38 };
39
40 qcom,smp2p-dsps {
41 compatible = "qcom,smp2p";
42 qcom,smem = <481>, <430>;
43 interrupt-parent = <&ipcc_mproc>;
44 interrupts = <IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P
45 IRQ_TYPE_EDGE_RISING>;
46 mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P>;
47 qcom,local-pid = <0>;
48 qcom,remote-pid = <3>;
49
50 dsps_smp2p_out: master-kernel {
51 qcom,entry-name = "master-kernel";
52 #qcom,smem-state-cells = <1>;
53 };
54
55 dsps_smp2p_in: slave-kernel {
56 qcom,entry-name = "slave-kernel";
57 interrupt-controller;
58 #interrupt-cells = <2>;
59 };
60
61 sleepstate_smp2p_out: sleepstate-out {
62 qcom,entry-name = "sleepstate";
63 #qcom,smem-state-cells = <1>;
64 };
65
66 sleepstate_smp2p_in: qcom,sleepstate-in {
67 qcom,entry-name = "sleepstate_see";
68 interrupt-controller;
69 #interrupt-cells = <2>;
70 };
71 };
72
73 qcom,smp2p-cdsp {
74 compatible = "qcom,smp2p";
75 qcom,smem = <94>, <432>;
76 interrupt-parent = <&ipcc_mproc>;
77 interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
78 IRQ_TYPE_EDGE_RISING>;
79 mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
80 qcom,local-pid = <0>;
81 qcom,remote-pid = <5>;
82
83 cdsp_smp2p_out: master-kernel {
84 qcom,entry-name = "master-kernel";
85 #qcom,smem-state-cells = <1>;
86 };
87
88 cdsp_smp2p_in: slave-kernel {
89 qcom,entry-name = "slave-kernel";
90 interrupt-controller;
91 #interrupt-cells = <2>;
92 };
93
94 smp2p_qvrexternal5_out: qcom,smp2p-qvrexternal5-out {
95 qcom,entry-name = "qvrexternal";
96 #qcom,smem-state-cells = <1>;
97 };
98
99 smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
100 qcom,entry-name = "rdbg";
101 #qcom,smem-state-cells = <1>;
102 };
103
104 smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
105 qcom,entry-name = "rdbg";
106 interrupt-controller;
107 #interrupt-cells = <2>;
108 };
109 };
110
111 qcom,smp2p-npu {
112 compatible = "qcom,smp2p";
113 qcom,smem = <617>, <616>;
114 interrupt-parent = <&ipcc_mproc>;
115 interrupts = <IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P
116 IRQ_TYPE_EDGE_RISING>;
117 mboxes = <&msm_npu IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P>;
118 qcom,local-pid = <0>;
119 qcom,remote-pid = <10>;
120
121 npu_smp2p_out: master-kernel {
122 qcom,entry-name = "master-kernel";
123 #qcom,smem-state-cells = <1>;
124 };
125
126 npu_smp2p_in: slave-kernel {
127 qcom,entry-name = "slave-kernel";
128 interrupt-controller;
129 #interrupt-cells = <2>;
130 };
131 };
132};
133