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gerrit-public.fairphone.software / kernel / msm-4.19 / 9b0224459fa8ee7c60d16a0b710ebf039da9f365 / . / arch / arm64 / boot / dts / vendor / qcom / kona.dtsi
blob: 86300eda2df7ad733e121053896edbd2d4e3bb31 [file] [log] [blame]
Luca Weiss9b022442023-04-14 14:47:36 +0200[diff] [blame^]1#include <dt-bindings/clock/qcom,aop-qmp.h>
2#include <dt-bindings/clock/qcom,camcc-kona.h>
3#include <dt-bindings/clock/qcom,cpucc-kona.h>
4#include <dt-bindings/clock/qcom,dispcc-kona.h>
5#include <dt-bindings/clock/qcom,gcc-kona.h>
6#include <dt-bindings/clock/qcom,gpucc-kona.h>
7#include <dt-bindings/clock/qcom,npucc-kona.h>
8#include <dt-bindings/clock/qcom,rpmh.h>
9#include <dt-bindings/clock/qcom,videocc-kona.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/msm/msm-bus-ids.h>
12#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
13#include <dt-bindings/soc/qcom,ipcc.h>
14#include <dt-bindings/soc/qcom,dcc_v2.h>
15#include <dt-bindings/soc/qcom,rpmh-rsc.h>
16#include <dt-bindings/spmi/spmi.h>
17#include <dt-bindings/gpio/gpio.h>
18
19#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
20#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
21
22#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
23 opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
24 opp-supported-hw = <ddrtype>;}
25
26#define DDR_TYPE_LPDDR4X 7
27#define DDR_TYPE_LPDDR5 8
28
29/ {
30 model = "Qualcomm Technologies, Inc. kona";
31 compatible = "qcom,kona";
32 qcom,msm-id = <356 0x10000>;
33 interrupt-parent = <&intc>;
34
35 #address-cells = <2>;
36 #size-cells = <2>;
37 memory { device_type = "memory"; reg = <0 0 0 0>; };
38
39 mem-offline {
40 compatible = "qcom,mem-offline";
41 offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
42 <0x1 0xc0000000 0x0 0x80000000>,
43 <0x2 0xc0000000 0x1 0x40000000>;
44 granule = <512>;
45 mboxes = <&qmp_aop 0>;
46 };
47
48 aliases {
49 ufshc1 = &ufshc_mem; /* Embedded UFS slot */
50 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
51 pci-domain0 = &pcie0; /* PCIe0 domain */
52 pci-domain1 = &pcie1; /* PCIe1 domain */
53 pci-domain2 = &pcie2; /* PCIe2 domain */
54 serial0 = &qupv3_se2_2uart; /* RUMI */
55 swr0 = &swr0;
56 swr1 = &swr1;
57 swr2 = &swr2;
58 swr_ar0 = &swr_ar0;
59 swr_ar1 = &swr_ar1;
60 swr_ar2 = &swr_ar2;
61 mhi-netdev0 = &mhi_netdev_0;
62 };
63
64 cpus {
65 #address-cells = <2>;
66 #size-cells = <0>;
67
68 CPU0: cpu@0 {
69 device_type = "cpu";
70 compatible = "qcom,kryo";
71 reg = <0x0 0x0>;
72 enable-method = "psci";
73 cpu-release-addr = <0x0 0x90000000>;
74 next-level-cache = <&L2_0>;
75 qcom,freq-domain = <&cpufreq_hw 0 4>;
76 capacity-dmips-mhz = <1024>;
77 dynamic-power-coefficient = <100>;
78 #cooling-cells = <2>;
79 L2_0: l2-cache {
80 compatible = "arm,arch-cache";
81 cache-level = <2>;
82 next-level-cache = <&L3_0>;
83
84 L3_0: l3-cache {
85 compatible = "arm,arch-cache";
86 cache-level = <3>;
87 };
88 };
89
90 L1_I_0: l1-icache {
91 compatible = "arm,arch-cache";
92 };
93
94 L1_D_0: l1-dcache {
95 compatible = "arm,arch-cache";
96 };
97 };
98
99 CPU1: cpu@100 {
100 device_type = "cpu";
101 compatible = "qcom,kryo";
102 reg = <0x0 0x100>;
103 enable-method = "psci";
104 cpu-release-addr = <0x0 0x90000000>;
105 next-level-cache = <&L2_1>;
106 qcom,freq-domain = <&cpufreq_hw 0 4>;
107 capacity-dmips-mhz = <1024>;
108 dynamic-power-coefficient = <100>;
109 L2_1: l2-cache {
110 compatible = "arm,arch-cache";
111 cache-level = <2>;
112 next-level-cache = <&L3_0>;
113 };
114
115 L1_I_100: l1-icache {
116 compatible = "arm,arch-cache";
117 };
118
119 L1_D_100: l1-dcache {
120 compatible = "arm,arch-cache";
121 };
122 };
123
124 CPU2: cpu@200 {
125 device_type = "cpu";
126 compatible = "qcom,kryo";
127 reg = <0x0 0x200>;
128 enable-method = "psci";
129 cpu-release-addr = <0x0 0x90000000>;
130 next-level-cache = <&L2_2>;
131 qcom,freq-domain = <&cpufreq_hw 0 4>;
132 capacity-dmips-mhz = <1024>;
133 dynamic-power-coefficient = <100>;
134 L2_2: l2-cache {
135 compatible = "arm,arch-cache";
136 cache-level = <2>;
137 next-level-cache = <&L3_0>;
138 };
139
140 L1_I_200: l1-icache {
141 compatible = "arm,arch-cache";
142 };
143
144 L1_D_200: l1-dcache {
145 compatible = "arm,arch-cache";
146 };
147 };
148
149 CPU3: cpu@300 {
150 device_type = "cpu";
151 compatible = "qcom,kryo";
152 reg = <0x0 0x300>;
153 enable-method = "psci";
154 cpu-release-addr = <0x0 0x90000000>;
155 next-level-cache = <&L2_3>;
156 qcom,freq-domain = <&cpufreq_hw 0 4>;
157 capacity-dmips-mhz = <1024>;
158 dynamic-power-coefficient = <100>;
159 L2_3: l2-cache {
160 compatible = "arm,arch-cache";
161 cache-level = <2>;
162 next-level-cache = <&L3_0>;
163 };
164
165 L1_I_300: l1-icache {
166 compatible = "arm,arch-cache";
167 };
168
169 L1_D_300: l1-dcache {
170 compatible = "arm,arch-cache";
171 };
172 };
173
174 CPU4: cpu@400 {
175 device_type = "cpu";
176 compatible = "qcom,kryo";
177 reg = <0x0 0x400>;
178 enable-method = "psci";
179 cpu-release-addr = <0x0 0x90000000>;
180 next-level-cache = <&L2_4>;
181 qcom,freq-domain = <&cpufreq_hw 1 4>;
182 capacity-dmips-mhz = <1894>;
183 dynamic-power-coefficient = <514>;
184 #cooling-cells = <2>;
185 L2_4: l2-cache {
186 compatible = "arm,arch-cache";
187 cache-level = <2>;
188 next-level-cache = <&L3_0>;
189 };
190
191 L1_I_400: l1-icache {
192 compatible = "arm,arch-cache";
193 };
194
195 L1_D_400: l1-dcache {
196 compatible = "arm,arch-cache";
197 };
198 };
199
200 CPU5: cpu@500 {
201 device_type = "cpu";
202 compatible = "qcom,kryo";
203 reg = <0x0 0x500>;
204 enable-method = "psci";
205 cpu-release-addr = <0x0 0x90000000>;
206 next-level-cache = <&L2_5>;
207 qcom,freq-domain = <&cpufreq_hw 1 4>;
208 capacity-dmips-mhz = <1894>;
209 dynamic-power-coefficient = <514>;
210 L2_5: l2-cache {
211 compatible = "arm,arch-cache";
212 cache-level = <2>;
213 next-level-cache = <&L3_0>;
214 };
215
216 L1_I_500: l1-icache {
217 compatible = "arm,arch-cache";
218 };
219
220 L1_D_500: l1-dcache {
221 compatible = "arm,arch-cache";
222 };
223 };
224
225 CPU6: cpu@600 {
226 device_type = "cpu";
227 compatible = "qcom,kryo";
228 reg = <0x0 0x600>;
229 enable-method = "psci";
230 cpu-release-addr = <0x0 0x90000000>;
231 next-level-cache = <&L2_6>;
232 qcom,freq-domain = <&cpufreq_hw 1 4>;
233 capacity-dmips-mhz = <1894>;
234 dynamic-power-coefficient = <514>;
235 L2_6: l2-cache {
236 compatible = "arm,arch-cache";
237 cache-level = <2>;
238 next-level-cache = <&L3_0>;
239 };
240
241 L1_I_600: l1-icache {
242 compatible = "arm,arch-cache";
243 };
244
245 L1_D_600: l1-dcache {
246 compatible = "arm,arch-cache";
247 };
248 };
249
250 CPU7: cpu@700 {
251 device_type = "cpu";
252 compatible = "qcom,kryo";
253 reg = <0x0 0x700>;
254 enable-method = "psci";
255 cpu-release-addr = <0x0 0x90000000>;
256 next-level-cache = <&L2_7>;
257 qcom,freq-domain = <&cpufreq_hw 2 4>;
258 capacity-dmips-mhz = <1894>;
259 dynamic-power-coefficient = <598>;
260 #cooling-cells = <2>;
261 L2_7: l2-cache {
262 compatible = "arm,arch-cache";
263 cache-level = <2>;
264 next-level-cache = <&L3_0>;
265 };
266
267 L1_I_700: l1-icache {
268 compatible = "arm,arch-cache";
269 };
270
271 L1_D_700: l1-dcache {
272 compatible = "arm,arch-cache";
273 };
274 };
275
276 cpu-map {
277 cluster0 {
278 core0 {
279 cpu = <&CPU0>;
280 };
281
282 core1 {
283 cpu = <&CPU1>;
284 };
285
286 core2 {
287 cpu = <&CPU2>;
288 };
289
290 core3 {
291 cpu = <&CPU3>;
292 };
293 };
294
295 cluster1 {
296 core0 {
297 cpu = <&CPU4>;
298 };
299
300 core1 {
301 cpu = <&CPU5>;
302 };
303
304 core2 {
305 cpu = <&CPU6>;
306 };
307 };
308
309 cluster2 {
310 core0 {
311 cpu = <&CPU7>;
312 };
313 };
314 };
315 };
316
317
318 cpu_pmu: cpu-pmu {
319 compatible = "arm,armv8-pmuv3";
320 qcom,irq-is-percpu;
321 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
322 };
323
324 soc: soc {
325 cpufreq_hw: qcom,cpufreq-hw {
326 compatible = "qcom,cpufreq-hw-epss";
327 reg = <0x18591000 0x1000>, <0x18592000 0x1000>,
328 <0x18593000 0x1000>;
329 reg-names = "freq-domain0", "freq-domain1",
330 "freq-domain2";
331
332 clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GPLL0>;
333 clock-names = "xo", "alternate";
334
335 qcom,lut-row-size = <4>;
336 qcom,skip-enable-check;
337
338 #freq-domain-cells = <2>;
339
340 cpu7_notify: cpu7-notify {
341 qcom,cooling-cpu = <&CPU7>;
342 #cooling-cells = <2>;
343 };
344 };
345 };
346
347 psci {
348 compatible = "arm,psci-1.0";
349 method = "smc";
350 };
351
352 chosen {
353 bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
354 };
355
356 firmware: firmware {
357 android {
358 compatible = "android,firmware";
359 vbmeta {
360 compatible = "android,vbmeta";
361 parts = "vbmeta,boot,system,vendor,dtbo";
362 };
363
364 fstab {
365 compatible = "android,fstab";
366 vendor {
367 compatible = "android,vendor";
368 dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
369 type = "ext4";
370 mnt_flags = "ro,barrier=1,discard";
371 fsmgr_flags = "wait,slotselect,avb";
372 status = "ok";
373 };
374 };
375 };
376 };
377
378 reserved_memory: reserved-memory {
379 #address-cells = <2>;
380 #size-cells = <2>;
381 ranges;
382
383 hyp_mem: hyp_region@80000000 {
384 no-map;
385 reg = <0x0 0x80000000 0x0 0x600000>;
386 };
387
388 xbl_aop_mem: xbl_aop_region@80700000 {
389 no-map;
390 reg = <0x0 0x80700000 0x0 0x160000>;
391 };
392
393 cmd_db: reserved-memory@80860000 {
394 reg = <0x0 0x80860000 0x0 0x20000>;
395 compatible = "qcom,cmd-db";
396 no-map;
397 };
398
399 reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 {
400 compatible = "removed-dma-pool";
401 no-map;
402 reg = <0x0 0x80880000 0x0 0x14000>;
403 };
404
405 smem_mem: smem_region@80900000 {
406 no-map;
407 reg = <0x0 0x80900000 0x0 0x200000>;
408 };
409
410 removed_mem: removed_region@80b00000 {
411 no-map;
412 reg = <0x0 0x80b00000 0x0 0x5300000>;
413 };
414
415 pil_camera_mem: pil_camera_region@86200000 {
416 compatible = "removed-dma-pool";
417 no-map;
418 reg = <0x0 0x86200000 0x0 0x500000>;
419 };
420
421 pil_wlan_fw_mem: pil_wlan_fw_region@86700000 {
422 compatible = "removed-dma-pool";
423 no-map;
424 reg = <0x0 0x86700000 0x0 0x100000>;
425 };
426
427 pil_ipa_fw_mem: pil_ipa_fw_region@86800000 {
428 compatible = "removed-dma-pool";
429 no-map;
430 reg = <0x0 0x86800000 0x0 0x10000>;
431 };
432
433 pil_ipa_gsi_mem: pil_ipa_gsi_region@86810000 {
434 compatible = "removed-dma-pool";
435 no-map;
436 reg = <0x0 0x86810000 0x0 0xa000>;
437 };
438
439 pil_gpu_mem: pil_gpu_region@8681a000 {
440 compatible = "removed-dma-pool";
441 no-map;
442 reg = <0x0 0x8681a000 0x0 0x2000>;
443 };
444
445 pil_npu_mem: pil_npu_region@86900000 {
446 compatible = "removed-dma-pool";
447 no-map;
448 reg = <0x0 0x86900000 0x0 0x500000>;
449 };
450
451 pil_video_mem: pil_video_region@86e00000 {
452 compatible = "removed-dma-pool";
453 no-map;
454 reg = <0x0 0x86e00000 0x0 0x500000>;
455 };
456
457 pil_cvp_mem: pil_cvp_region@87300000 {
458 compatible = "removed-dma-pool";
459 no-map;
460 reg = <0x0 0x87300000 0x0 0x500000>;
461 };
462
463 pil_cdsp_mem: pil_cdsp_region@87800000 {
464 compatible = "removed-dma-pool";
465 no-map;
466 reg = <0x0 0x87800000 0x0 0x1400000>;
467 };
468
469 pil_slpi_mem: pil_slpi_region@88c00000 {
470 compatible = "removed-dma-pool";
471 no-map;
472 reg = <0x0 0x88c00000 0x0 0x1500000>;
473 };
474
475 pil_adsp_mem: pil_adsp_region@8a100000 {
476 compatible = "removed-dma-pool";
477 no-map;
478 reg = <0x0 0x8a100000 0x0 0x1d00000>;
479 };
480
481 pil_spss_mem: pil_spss_region@8be00000 {
482 compatible = "removed-dma-pool";
483 no-map;
484 reg = <0x0 0x8be00000 0x0 0x100000>;
485 };
486
487 cdsp_secure_heap: cdsp_secure_heap@8bf00000 {
488 compatible = "removed-dma-pool";
489 no-map;
490 reg = <0x0 0x8bf00000 0x0 0x4600000>;
491 };
492
493 adsp_mem: adsp_region {
494 compatible = "shared-dma-pool";
495 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
496 reusable;
497 alignment = <0x0 0x400000>;
498 size = <0x0 0xC00000>;
499 };
500
501 sdsp_mem: sdsp_region {
502 compatible = "shared-dma-pool";
503 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
504 reusable;
505 alignment = <0x0 0x400000>;
506 size = <0x0 0x800000>;
507 };
508
509 cdsp_mem: cdsp_region {
510 compatible = "shared-dma-pool";
511 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
512 reusable;
513 alignment = <0x0 0x400000>;
514 size = <0x0 0x400000>;
515 };
516
517 cont_splash_memory: cont_splash_region@9c000000 {
518 reg = <0x0 0x9c000000 0x0 0x02300000>;
519 label = "cont_splash_region";
520 };
521
522 disp_rdump_memory: disp_rdump_region@9c000000 {
523 reg = <0x0 0x9c000000 0x0 0x00800000>;
524 label = "disp_rdump_region";
525 };
526
527 dfps_data_memory: dfps_data_region@9e300000 {
528 reg = <0x0 0x9e300000 0x0 0x0100000>;
529 label = "dfps_data_region";
530 };
531
532 dump_mem: mem_dump_region {
533 compatible = "shared-dma-pool";
534 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
535 reusable;
536 size = <0 0x2800000>;
537 };
538 sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
539 compatible = "shared-dma-pool";
540 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
541 reusable;
542 alignment = <0x0 0x400000>;
543 size = <0x0 0x1000000>;
544 };
545
546 user_contig_mem: user_contig_region {
547 compatible = "shared-dma-pool";
548 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
549 reusable;
550 alignment = <0x0 0x400000>;
551 size = <0x0 0x1000000>;
552 };
553
554 qseecom_mem: qseecom_region {
555 compatible = "shared-dma-pool";
556 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
557 reusable;
558 alignment = <0x0 0x400000>;
559 size = <0x0 0x1400000>;
560 };
561
562 qseecom_ta_mem: qseecom_ta_region {
563 compatible = "shared-dma-pool";
564 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
565 reusable;
566 alignment = <0x0 0x400000>;
567 size = <0x0 0x1000000>;
568 };
569
570 secure_display_memory: secure_display_region { /* Secure UI */
571 compatible = "shared-dma-pool";
572 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
573 reusable;
574 alignment = <0x0 0x400000>;
575 size = <0x0 0xA400000>;
576 };
577
578 cnss_wlan_mem: cnss_wlan_region {
579 compatible = "shared-dma-pool";
580 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
581 reusable;
582 alignment = <0x0 0x400000>;
583 size = <0x0 0x1400000>;
584 };
585
586 /* global autoconfigured region for contiguous allocations */
587 linux,cma {
588 compatible = "shared-dma-pool";
589 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
590 reusable;
591 alignment = <0x0 0x400000>;
592 size = <0x0 0x2000000>;
593 linux,cma-default;
594 };
595
596 mailbox_mem: mailbox_region {
597 compatible = "shared-dma-pool";
598 no-map;
599 alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
600 alignment = <0x0 0x400000>;
601 size = <0x0 0x20000>;
602 };
603 };
604
605 vendor: vendor {
606 #address-cells = <1>;
607 #size-cells = <1>;
608 ranges = <0 0 0 0xffffffff>;
609 compatible = "simple-bus";
610 };
611};
612
613&soc {
614 #address-cells = <1>;
615 #size-cells = <1>;
616 ranges = <0 0 0 0xffffffff>;
617 compatible = "simple-bus";
618
619 thermal_zones: thermal-zones {
620 };
621
622 slim_aud: slim@3ac0000 {
623 cell-index = <1>;
624 compatible = "qcom,slim-ngd";
625 reg = <0x3ac0000 0x2c000>,
626 <0x3a84000 0x2c000>;
627 reg-names = "slimbus_physical", "slimbus_bam_physical";
628 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
630 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
631 qcom,apps-ch-pipes = <0x700000>;
632 qcom,ea-pc = <0x2d0>;
633 iommus = <&apps_smmu 0x1826 0x0>,
634 <&apps_smmu 0x182f 0x0>,
635 <&apps_smmu 0x1830 0x1>;
636 qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
637 qcom,iommu-dma = "atomic";
638 status = "ok";
639
640 /* Slimbus Slave DT for QCA6390 */
641 btfmslim_codec: qca6390 {
642 compatible = "qcom,btfmslim_slave";
643 elemental-addr = [00 01 20 02 17 02];
644 qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
645 qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
646 };
647 };
648
649 intc: interrupt-controller@17a00000 {
650 compatible = "arm,gic-v3";
651 #interrupt-cells = <3>;
652 interrupt-controller;
653 #redistributor-regions = <1>;
654 redistributor-stride = <0x0 0x20000>;
655 reg = <0x17a00000 0x10000>, /* GICD */
656 <0x17a60000 0x100000>; /* GICR * 8 */
657 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
658 };
659
660 qcom,chd_silver {
661 compatible = "qcom,core-hang-detect";
662 label = "silver";
663 qcom,threshold-arr = <0x18000058 0x18010058
664 0x18020058 0x18030058>;
665 qcom,config-arr = <0x18000060 0x18010060
666 0x18020060 0x18030060>;
667 };
668
669 dsu_pmu@0 {
670 compatible = "arm,dsu-pmu";
671 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
672 cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
673 <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
674 };
675
676 qcom,chd_gold {
677 compatible = "qcom,core-hang-detect";
678 label = "gold";
679 qcom,threshold-arr = <0x18040058 0x18050058
680 0x18060058 0x18070058>;
681 qcom,config-arr = <0x18040060 0x18050060
682 0x18060060 0x18070060>;
683 };
684
685 cache-controller@9200000 {
686 compatible = "qcom,llcc-v2";
687 reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
688 reg-names = "llcc_base", "llcc_broadcast_base";
689 cap-based-alloc-and-pwr-collapse;
690 };
691
692 wdog: qcom,wdt@17c10000 {
693 compatible = "qcom,msm-watchdog";
694 reg = <0x17c10000 0x1000>;
695 reg-names = "wdt-base";
696 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
697 <0 1 IRQ_TYPE_LEVEL_HIGH>;
698 qcom,bark-time = <11000>;
699 qcom,pet-time = <9360>;
700 qcom,wakeup-enable;
701 qcom,ipi-ping;
702 };
703
704 arch_timer: timer {
705 compatible = "arm,armv8-timer";
706 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
707 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
708 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
709 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
710 clock-frequency = <19200000>;
711 };
712
713 memtimer: timer@17c20000 {
714 #address-cells = <1>;
715 #size-cells = <1>;
716 ranges;
717 compatible = "arm,armv7-timer-mem";
718 reg = <0x17c20000 0x1000>;
719 clock-frequency = <19200000>;
720
721 frame@17c21000 {
722 frame-number = <0>;
723 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
725 reg = <0x17c21000 0x1000>,
726 <0x17c22000 0x1000>;
727 };
728
729 frame@17c23000 {
730 frame-number = <1>;
731 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
732 reg = <0x17c23000 0x1000>;
733 status = "disabled";
734 };
735
736 frame@17c25000 {
737 frame-number = <2>;
738 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
739 reg = <0x17c25000 0x1000>;
740 status = "disabled";
741 };
742
743 frame@17c27000 {
744 frame-number = <3>;
745 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
746 reg = <0x17c27000 0x1000>;
747 status = "disabled";
748 };
749
750 frame@17c29000 {
751 frame-number = <4>;
752 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
753 reg = <0x17c29000 0x1000>;
754 status = "disabled";
755 };
756
757 frame@17c2b000 {
758 frame-number = <5>;
759 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
760 reg = <0x17c2b000 0x1000>;
761 status = "disabled";
762 };
763
764 frame@17c2d000 {
765 frame-number = <6>;
766 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
767 reg = <0x17c2d000 0x1000>;
768 status = "disabled";
769 };
770 };
771
772 jtag_mm0: jtagmm@7040000 {
773 compatible = "qcom,jtagv8-mm";
774 reg = <0x7040000 0x1000>;
775 reg-names = "etm-base";
776
777 clocks = <&clock_aop QDSS_CLK>;
778 clock-names = "core_clk";
779
780 qcom,coresight-jtagmm-cpu = <&CPU0>;
781 };
782
783 jtag_mm1: jtagmm@7140000 {
784 compatible = "qcom,jtagv8-mm";
785 reg = <0x7140000 0x1000>;
786 reg-names = "etm-base";
787
788 clocks = <&clock_aop QDSS_CLK>;
789 clock-names = "core_clk";
790
791 qcom,coresight-jtagmm-cpu = <&CPU1>;
792 };
793
794 jtag_mm2: jtagmm@7240000 {
795 compatible = "qcom,jtagv8-mm";
796 reg = <0x7240000 0x1000>;
797 reg-names = "etm-base";
798
799 clocks = <&clock_aop QDSS_CLK>;
800 clock-names = "core_clk";
801
802 qcom,coresight-jtagmm-cpu = <&CPU2>;
803 };
804
805 jtag_mm3: jtagmm@7340000 {
806 compatible = "qcom,jtagv8-mm";
807 reg = <0x7340000 0x1000>;
808 reg-names = "etm-base";
809
810 clocks = <&clock_aop QDSS_CLK>;
811 clock-names = "core_clk";
812
813 qcom,coresight-jtagmm-cpu = <&CPU3>;
814 };
815
816 jtag_mm4: jtagmm@7440000 {
817 compatible = "qcom,jtagv8-mm";
818 reg = <0x7440000 0x1000>;
819 reg-names = "etm-base";
820
821 clocks = <&clock_aop QDSS_CLK>;
822 clock-names = "core_clk";
823
824 qcom,coresight-jtagmm-cpu = <&CPU4>;
825 };
826
827 jtag_mm5: jtagmm@7540000 {
828 compatible = "qcom,jtagv8-mm";
829 reg = <0x7540000 0x1000>;
830 reg-names = "etm-base";
831
832 clocks = <&clock_aop QDSS_CLK>;
833 clock-names = "core_clk";
834
835 qcom,coresight-jtagmm-cpu = <&CPU5>;
836 };
837
838 jtag_mm6: jtagmm@7640000 {
839 compatible = "qcom,jtagv8-mm";
840 reg = <0x7640000 0x1000>;
841 reg-names = "etm-base";
842
843 clocks = <&clock_aop QDSS_CLK>;
844 clock-names = "core_clk";
845
846 qcom,coresight-jtagmm-cpu = <&CPU6>;
847 };
848
849 jtag_mm7: jtagmm@7740000 {
850 compatible = "qcom,jtagv8-mm";
851 reg = <0x7740000 0x1000>;
852 reg-names = "etm-base";
853
854 clocks = <&clock_aop QDSS_CLK>;
855 clock-names = "core_clk";
856
857 qcom,coresight-jtagmm-cpu = <&CPU7>;
858 };
859
860 qcom,devfreq-l3 {
861 compatible = "qcom,devfreq-fw";
862 reg = <0x18590000 0x4>, <0x18590100 0xa0>, <0x18590320 0x4>;
863 reg-names = "en-base", "ftbl-base", "perf-base";
864
865 cpu0_l3: qcom,cpu0-cpu-l3-lat {
866 compatible = "qcom,devfreq-fw-voter";
867 };
868
869 cpu4_l3: qcom,cpu4-cpu-l3-lat {
870 compatible = "qcom,devfreq-fw-voter";
871 };
872
873 cpu7_l3: qcom,cpu7-cpu-l3-lat {
874 compatible = "qcom,devfreq-fw-voter";
875 };
876
877 cdsp_l3: qcom,cdsp-cdsp-l3-lat {
878 compatible = "qcom,devfreq-fw-voter";
879 };
880 };
881
882 bus_proxy_client: qcom,bus_proxy_client {
883 compatible = "qcom,bus-proxy-client";
884 qcom,msm-bus,name = "bus-proxy-client";
885 qcom,msm-bus,num-cases = <2>;
886 qcom,msm-bus,num-paths = <2>;
887 qcom,msm-bus,vectors-KBps =
888 <22 512 0 0>, <23 512 0 0>,
889 <22 512 1500000 1500000>, <23 512 1500000 1500000>;
890 qcom,msm-bus,active-only;
891 status = "ok";
892 };
893
894 keepalive_opp_table: keepalive-opp-table {
895 compatible = "operating-points-v2";
896 opp-1 {
897 opp-hz = /bits/ 64 < 1 >;
898 };
899 };
900
901 snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive {
902 compatible = "qcom,devbw";
903 governor = "powersave";
904 qcom,src-dst-ports = <MSM_BUS_MASTER_AMPSS_M0
905 MSM_BUS_SLAVE_IMEM_CFG>;
906 qcom,active-only;
907 status = "ok";
908 operating-points-v2 = <&keepalive_opp_table>;
909 };
910
911 llcc_bw_opp_table: llcc-bw-opp-table {
912 compatible = "operating-points-v2";
913 BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
914 BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
915 BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
916 BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
917 BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
918 BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
919 BW_OPP_ENTRY( 1000, 16); /* 15258 MB/s */
920 };
921
922 suspendable_llcc_bw_opp_table: suspendable-llcc-bw-opp-table {
923 compatible = "operating-points-v2";
924 BW_OPP_ENTRY( 0, 16); /* 0 MB/s */
925 BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
926 BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
927 BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
928 BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
929 BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
930 BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
931 BW_OPP_ENTRY( 1000, 16); /* 15258 MB/s */
932 };
933
934 ddr_bw_opp_table: ddr-bw-opp-table {
935 compatible = "operating-points-v2";
936 BW_OPP_ENTRY_DDR( 200, 4, 0x180); /* 762 MB/s */
937 BW_OPP_ENTRY_DDR( 300, 4, 0x180); /* 1144 MB/s */
938 BW_OPP_ENTRY_DDR( 451, 4, 0x180); /* 1720 MB/s */
939 BW_OPP_ENTRY_DDR( 547, 4, 0x180); /* 2086 MB/s */
940 BW_OPP_ENTRY_DDR( 681, 4, 0x180); /* 2597 MB/s */
941 BW_OPP_ENTRY_DDR( 768, 4, 0x180); /* 2929 MB/s */
942 BW_OPP_ENTRY_DDR( 1017, 4, 0x180); /* 3879 MB/s */
943 BW_OPP_ENTRY_DDR( 1353, 4, 0x80); /* 5161 MB/s */
944 BW_OPP_ENTRY_DDR( 1555, 4, 0x180); /* 5931 MB/s */
945 BW_OPP_ENTRY_DDR( 1804, 4, 0x180); /* 6881 MB/s */
946 BW_OPP_ENTRY_DDR( 2092, 4, 0x180); /* 7980 MB/s */
947 BW_OPP_ENTRY_DDR( 2736, 4, 0x100); /* 10437 MB/s */
948 };
949
950 suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table {
951 compatible = "operating-points-v2";
952 BW_OPP_ENTRY_DDR( 0, 4, 0x180); /* 0 MB/s */
953 BW_OPP_ENTRY_DDR( 200, 4, 0x180); /* 762 MB/s */
954 BW_OPP_ENTRY_DDR( 300, 4, 0x180); /* 1144 MB/s */
955 BW_OPP_ENTRY_DDR( 451, 4, 0x180); /* 1720 MB/s */
956 BW_OPP_ENTRY_DDR( 547, 4, 0x180); /* 2086 MB/s */
957 BW_OPP_ENTRY_DDR( 681, 4, 0x180); /* 2597 MB/s */
958 BW_OPP_ENTRY_DDR( 768, 4, 0x180); /* 2929 MB/s */
959 BW_OPP_ENTRY_DDR( 1017, 4, 0x180); /* 3879 MB/s */
960 BW_OPP_ENTRY_DDR( 1353, 4, 0x80); /* 5161 MB/s */
961 BW_OPP_ENTRY_DDR( 1555, 4, 0x180); /* 5931 MB/s */
962 BW_OPP_ENTRY_DDR( 1804, 4, 0x180); /* 6881 MB/s */
963 BW_OPP_ENTRY_DDR( 2092, 4, 0x180); /* 7980 MB/s */
964 BW_OPP_ENTRY_DDR( 2736, 4, 0x100); /* 10437 MB/s */
965 };
966
967 llcc_pmu: llcc-pmu@9095000 {
968 compatible = "qcom,llcc-pmu-ver2";
969 reg = <0x09095000 0x300>;
970 reg-names = "lagg-base";
971 };
972
973 cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
974 compatible = "qcom,devbw";
975 governor = "performance";
976 qcom,src-dst-ports =
977 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;
978 qcom,active-only;
979 operating-points-v2 = <&llcc_bw_opp_table>;
980 };
981
982 cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
983 compatible = "qcom,bimc-bwmon4";
984 reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
985 reg-names = "base", "global_base";
986 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
987 qcom,mport = <0>;
988 qcom,hw-timer-hz = <19200000>;
989 qcom,target-dev = <&cpu_cpu_llcc_bw>;
990 qcom,count-unit = <0x10000>;
991 };
992
993 cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
994 compatible = "qcom,devbw-ddr";
995 governor = "performance";
996 qcom,src-dst-ports =
997 <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
998 qcom,active-only;
999 operating-points-v2 = <&ddr_bw_opp_table>;
1000 };
1001
1002 cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@9091000 {
1003 compatible = "qcom,bimc-bwmon5";
1004 reg = <0x9091000 0x1000>;
1005 reg-names = "base";
1006 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1007 qcom,hw-timer-hz = <19200000>;
1008 qcom,target-dev = <&cpu_llcc_ddr_bw>;
1009 qcom,count-unit = <0x10000>;
1010 };
1011
1012 npu_npu_llcc_bw: qcom,npu-npu-llcc-bw {
1013 compatible = "qcom,devbw";
1014 governor = "performance";
1015 qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_LLCC>;
1016 operating-points-v2 = <&suspendable_llcc_bw_opp_table>;
1017 };
1018
1019 npu_npu_llcc_bwmon: qcom,npu-npu-llcc-bwmon@60300 {
1020 compatible = "qcom,bimc-bwmon4";
1021 reg = <0x00060400 0x300>, <0x00060300 0x200>;
1022 reg-names = "base", "global_base";
1023 qcom,msm_bus = <154 10070>;
1024 qcom,msm_bus_name = "npu_bwmon_cdsp";
1025 clocks = <&clock_gcc GCC_NPU_BWMON_CFG_AHB_CLK>,
1026 <&clock_gcc GCC_NPU_BWMON_AXI_CLK>;
1027 clock-names = "npu_bwmon_ahb", "npu_bwmon_axi";
1028 qcom,bwmon_clks = "npu_bwmon_ahb", "npu_bwmon_axi";
1029 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
1030 qcom,mport = <0>;
1031 qcom,hw-timer-hz = <19200000>;
1032 qcom,target-dev = <&npu_npu_llcc_bw>;
1033 qcom,count-unit = <0x10000>;
1034 };
1035
1036 npu_llcc_ddr_bw: qcom,npu-llcc-ddr-bw {
1037 compatible = "qcom,devbw-ddr";
1038 governor = "performance";
1039 qcom,src-dst-ports = <MSM_BUS_SLAVE_LLCC MSM_BUS_SLAVE_EBI_CH0>;
1040 operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
1041 };
1042
1043 npu_llcc_ddr_bwmon: qcom,npu-llcc-ddr-bwmon@0x9093000 {
1044 compatible = "qcom,bimc-bwmon5";
1045 reg = <0x9093000 0x1000>;
1046 reg-names = "base";
1047 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1048 qcom,hw-timer-hz = <19200000>;
1049 qcom,target-dev = <&npu_llcc_ddr_bw>;
1050 qcom,count-unit = <0x10000>;
1051 };
1052
1053 npudsp_npu_ddr_bw: qcom,npudsp-npu-ddr-bw {
1054 compatible = "qcom,devbw-ddr";
1055 governor = "performance";
1056 qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;
1057 operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
1058 };
1059
1060 npudsp_npu_ddr_bwmon: qcom,npudsp-npu-ddr-bwmon@70200 {
1061 compatible = "qcom,bimc-bwmon4";
1062 reg = <0x00070300 0x300>, <0x00070200 0x200>;
1063 reg-names = "base", "global_base";
1064 qcom,msm_bus = <154 10070>;
1065 qcom,msm_bus_name = "npudsp_bwmon_cdsp";
1066 clocks = <&clock_gcc GCC_NPU_BWMON_CFG_AHB_CLK>,
1067 <&clock_gcc GCC_NPU_BWMON_AXI_CLK>;
1068 clock-names = "npu_bwmon_ahb", "npu_bwmon_axi";
1069 qcom,bwmon_clks = "npu_bwmon_ahb", "npu_bwmon_axi";
1070 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1071 qcom,mport = <0>;
1072 qcom,hw-timer-hz = <19200000>;
1073 qcom,target-dev = <&npudsp_npu_ddr_bw>;
1074 qcom,count-unit = <0x10000>;
1075 };
1076
1077 npu_npu_ddr_latfloor: qcom,npu-npu-ddr-latfloor {
1078 compatible = "qcom,devbw-ddr";
1079 governor = "powersave";
1080 qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;
1081 operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
1082 };
1083
1084 npu_staticmap_mon: qcom,npu-staticmap-mon {
1085 compatible = "qcom,static-map";
1086 qcom,target-dev = <&npu_npu_ddr_latfloor>;
1087 clocks = <&clock_npucc NPU_CC_CAL_HM0_CLK>;
1088 clock-names = "cal_hm0_clk";
1089 qcom,dev_clk = "cal_hm0_clk";
1090 qcom,core-dev-table =
1091 < 0 MHZ_TO_MBPS( 0, 4) >,
1092 < 300000 MHZ_TO_MBPS( 451, 4) >,
1093 < 406000 MHZ_TO_MBPS( 768, 4) >,
1094 < 533000 MHZ_TO_MBPS( 1555, 4) >,
1095 < 730000 MHZ_TO_MBPS( 1804, 4) >,
1096 < 920000 MHZ_TO_MBPS( 2092, 4) >,
1097 < 1000000 MHZ_TO_MBPS( 2736, 4) >;
1098 };
1099
1100 cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
1101 compatible = "qcom,devbw";
1102 governor = "performance";
1103 qcom,src-dst-ports =
1104 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;
1105 qcom,active-only;
1106 operating-points-v2 = <&llcc_bw_opp_table>;
1107 };
1108
1109 cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {
1110 compatible = "qcom,devbw";
1111 governor = "performance";
1112 qcom,src-dst-ports =
1113 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;
1114 qcom,active-only;
1115 operating-points-v2 = <&llcc_bw_opp_table>;
1116 };
1117
1118 cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
1119 compatible = "qcom,devbw-ddr";
1120 governor = "performance";
1121 qcom,src-dst-ports =
1122 <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
1123 qcom,active-only;
1124 operating-points-v2 = <&ddr_bw_opp_table>;
1125 };
1126
1127 cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {
1128 compatible = "qcom,devbw-ddr";
1129 governor = "performance";
1130 qcom,src-dst-ports =
1131 <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
1132 qcom,active-only;
1133 operating-points-v2 = <&ddr_bw_opp_table>;
1134 };
1135
1136 cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
1137 compatible = "qcom,devbw-ddr";
1138 governor = "performance";
1139 qcom,src-dst-ports =
1140 <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
1141 qcom,active-only;
1142 operating-points-v2 = <&ddr_bw_opp_table>;
1143 };
1144
1145 qoslat_opp_table: qoslat-opp-table {
1146 compatible = "operating-points-v2";
1147 opp-0 {
1148 opp-hz = /bits/ 64 < 1 >;
1149 };
1150
1151 opp-1 {
1152 opp-hz = /bits/ 64 < 2 >;
1153 };
1154 };
1155
1156 cpu4_cpu_ddr_qoslat: qcom,cpu4-cpu-ddr-qoslat {
1157 compatible = "qcom,devfreq-qoslat";
1158 governor = "powersave";
1159 operating-points-v2 = <&qoslat_opp_table>;
1160 mboxes = <&qmp_aop 0>;
1161 };
1162
1163 cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
1164 compatible = "qcom,arm-memlat-cpugrp";
1165 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
1166
1167 cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
1168 compatible = "qcom,arm-memlat-mon";
1169 qcom,target-dev = <&cpu0_l3>;
1170 qcom,cachemiss-ev = <0x17>;
1171 qcom,core-dev-table =
1172 < 300000 300000000 >,
1173 < 403200 403200000 >,
1174 < 518400 518400000 >,
1175 < 633600 614400000 >,
1176 < 825600 729600000 >,
1177 < 921600 825600000 >,
1178 < 1036800 921600000 >,
1179 < 1132800 1036800000 >,
1180 < 1228800 1132800000 >,
1181 < 1401600 1228800000 >,
1182 < 1497600 1305600000 >,
1183 < 1670400 1382400000 >;
1184 };
1185
1186 cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
1187 compatible = "qcom,arm-memlat-mon";
1188 qcom,target-dev = <&cpu0_cpu_llcc_lat>;
1189 qcom,cachemiss-ev = <0x2A>;
1190 qcom,core-dev-table =
1191 < 300000 MHZ_TO_MBPS( 150, 16) >,
1192 < 729600 MHZ_TO_MBPS( 300, 16) >,
1193 < 1497600 MHZ_TO_MBPS( 466, 16) >,
1194 < 1670400 MHZ_TO_MBPS( 600, 16) >;
1195 };
1196
1197 cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
1198 compatible = "qcom,arm-memlat-mon";
1199 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
1200 qcom,target-dev = <&cpu0_llcc_ddr_lat>;
1201 qcom,cachemiss-ev = <0x2A>;
1202 ddr4-map {
1203 qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
1204 qcom,core-dev-table =
1205 < 300000 MHZ_TO_MBPS( 200, 4) >,
1206 < 729600 MHZ_TO_MBPS( 451, 4) >,
1207 < 1132800 MHZ_TO_MBPS( 547, 4) >,
1208 < 1497600 MHZ_TO_MBPS( 768, 4) >,
1209 < 1670400 MHZ_TO_MBPS( 1017, 4) >;
1210 };
1211
1212 ddr5-map {
1213 qcom,ddr-type = <DDR_TYPE_LPDDR5>;
1214 qcom,core-dev-table =
1215 < 300000 MHZ_TO_MBPS( 200, 4) >,
1216 < 729600 MHZ_TO_MBPS( 451, 4) >,
1217 < 1132800 MHZ_TO_MBPS( 547, 4) >,
1218 < 1497600 MHZ_TO_MBPS( 768, 4) >,
1219 < 1670400 MHZ_TO_MBPS( 1017, 4) >;
1220 };
1221 };
1222
1223 };
1224
1225 cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
1226 compatible = "qcom,arm-memlat-cpugrp";
1227 qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
1228
1229 cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {
1230 compatible = "qcom,arm-memlat-mon";
1231 qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
1232 qcom,target-dev = <&cpu4_l3>;
1233 qcom,cachemiss-ev = <0x17>;
1234 qcom,core-dev-table =
1235 < 300000 300000000 >,
1236 < 806400 614400000 >,
1237 < 1017600 729600000 >,
1238 < 1228800 921600000 >,
1239 < 1689600 1228800000 >,
1240 < 1804800 1305600000 >,
1241 < 2227200 1382400000 >;
1242 };
1243
1244 cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon {
1245 compatible = "qcom,arm-memlat-mon";
1246 qcom,cpulist = <&CPU7>;
1247 qcom,target-dev = <&cpu7_l3>;
1248 qcom,cachemiss-ev = <0x17>;
1249 qcom,core-dev-table =
1250 < 300000 300000000 >,
1251 < 806400 614400000 >,
1252 < 1017600 729600000 >,
1253 < 1228800 921600000 >,
1254 < 1689600 1228800000 >,
1255 < 1804800 1305600000 >,
1256 < 2227200 1382400000 >;
1257 };
1258
1259 cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon {
1260 compatible = "qcom,arm-memlat-mon";
1261 qcom,target-dev = <&cpu4_cpu_llcc_lat>;
1262 qcom,cachemiss-ev = <0x2A>;
1263 qcom,core-dev-table =
1264 < 300000 MHZ_TO_MBPS( 150, 16) >,
1265 < 691200 MHZ_TO_MBPS( 300, 16) >,
1266 < 1017600 MHZ_TO_MBPS( 466, 16) >,
1267 < 1228800 MHZ_TO_MBPS( 600, 16) >,
1268 < 1804800 MHZ_TO_MBPS( 806, 16) >,
1269 < 2227200 MHZ_TO_MBPS( 933, 16) >,
1270 < 2476800 MHZ_TO_MBPS( 1000, 16) >;
1271 };
1272
1273 cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {
1274 compatible = "qcom,arm-memlat-mon";
1275 qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
1276 qcom,target-dev = <&cpu4_llcc_ddr_lat>;
1277 qcom,cachemiss-ev = <0x2A>;
1278 ddr4-map {
1279 qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
1280 qcom,core-dev-table =
1281 < 300000 MHZ_TO_MBPS( 200, 4) >,
1282 < 691200 MHZ_TO_MBPS( 451, 4) >,
1283 < 806400 MHZ_TO_MBPS( 547, 4) >,
1284 < 1017600 MHZ_TO_MBPS( 768, 4) >,
1285 < 1228800 MHZ_TO_MBPS(1017, 4) >,
1286 < 1574400 MHZ_TO_MBPS(1353, 4) >,
1287 < 1804800 MHZ_TO_MBPS(1555, 4) >,
1288 < 2227200 MHZ_TO_MBPS(1804, 4) >,
1289 < 2380800 MHZ_TO_MBPS(2092, 4) >;
1290 };
1291
1292 ddr5-map {
1293 qcom,ddr-type = <DDR_TYPE_LPDDR5>;
1294 qcom,core-dev-table =
1295 < 300000 MHZ_TO_MBPS( 200, 4) >,
1296 < 691200 MHZ_TO_MBPS( 451, 4) >,
1297 < 806400 MHZ_TO_MBPS( 547, 4) >,
1298 < 1017600 MHZ_TO_MBPS( 768, 4) >,
1299 < 1228800 MHZ_TO_MBPS(1017, 4) >,
1300 < 1804800 MHZ_TO_MBPS(1555, 4) >,
1301 < 2227200 MHZ_TO_MBPS(1804, 4) >,
1302 < 2380800 MHZ_TO_MBPS(2092, 4) >,
1303 < 2476800 MHZ_TO_MBPS(2736, 4) >;
1304 };
1305 };
1306
1307 cpu4_computemon: qcom,cpu4-computemon {
1308 compatible = "qcom,arm-compute-mon";
1309 qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
1310 ddr4-map {
1311 qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
1312 qcom,core-dev-table =
1313 < 1804800 MHZ_TO_MBPS( 200, 4) >,
1314 < 2380800 MHZ_TO_MBPS(1017, 4) >,
1315 < 2500000 MHZ_TO_MBPS(2092, 4) >;
1316 };
1317
1318 ddr5-map {
1319 qcom,ddr-type = <DDR_TYPE_LPDDR5>;
1320 qcom,core-dev-table =
1321 < 1804800 MHZ_TO_MBPS( 200, 4) >,
1322 < 2380800 MHZ_TO_MBPS(1017, 4) >,
1323 < 2500000 MHZ_TO_MBPS(2736, 4) >;
1324 };
1325 };
1326
1327 cpu4_qoslatmon: qcom,cpu4-qoslatmon {
1328 compatible = "qcom,arm-memlat-mon";
1329 qcom,target-dev = <&cpu4_cpu_ddr_qoslat>;
1330 qcom,cachemiss-ev = <0x2A>;
1331 qcom,core-dev-table =
1332 < 300000 1 >,
1333 < 3000000 2 >;
1334 };
1335 };
1336
1337 keepalive_opp_table: keepalive-opp-table {
1338 compatible = "operating-points-v2";
1339 opp-1 {
1340 opp-hz = /bits/ 64 < 1 >;
1341 };
1342 };
1343
1344 snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive {
1345 compatible = "qcom,devbw";
1346 governor = "powersave";
1347 qcom,src-dst-ports = <1 627>;
1348 qcom,active-only;
1349 status = "ok";
1350 operating-points-v2 = <&keepalive_opp_table>;
1351 };
1352
1353 qcom,msm-imem@146bf000 {
1354 compatible = "qcom,msm-imem";
1355 reg = <0x146bf000 0x1000>;
1356 ranges = <0x0 0x146bf000 0x1000>;
1357 #address-cells = <1>;
1358 #size-cells = <1>;
1359
1360 mem_dump_table@10 {
1361 compatible = "qcom,msm-imem-mem_dump_table";
1362 reg = <0x10 0x8>;
1363 };
1364
1365 restart_reason@65c {
1366 compatible = "qcom,msm-imem-restart_reason";
1367 reg = <0x65c 0x4>;
1368 };
1369
1370 dload_type@1c {
1371 compatible = "qcom,msm-imem-dload-type";
1372 reg = <0x1c 0x4>;
1373 };
1374
1375 boot_stats@6b0 {
1376 compatible = "qcom,msm-imem-boot_stats";
1377 reg = <0x6b0 0x20>;
1378 };
1379
1380 kaslr_offset@6d0 {
1381 compatible = "qcom,msm-imem-kaslr_offset";
1382 reg = <0x6d0 0xc>;
1383 };
1384
1385 pil@94c {
1386 compatible = "qcom,msm-imem-pil";
1387 reg = <0x94c 0xc8>;
1388 };
1389
1390 diag_dload@c8 {
1391 compatible = "qcom,msm-imem-diag-dload";
1392 reg = <0xc8 0xc8>;
1393 };
1394 };
1395
1396 restart@c264000 {
1397 compatible = "qcom,pshold";
1398 reg = <0xc264000 0x4>,
1399 <0x1fd3000 0x4>;
1400 reg-names = "pshold-base", "tcsr-boot-misc-detect";
1401 };
1402
1403 dcc: dcc_v2@1023000 {
1404 compatible = "qcom,dcc-v2";
1405 reg = <0x1023000 0x1000>,
1406 <0x103a000 0x6000>;
1407 reg-names = "dcc-base", "dcc-ram-base";
1408
1409 dcc-ram-offset = <0x1a000>;
1410
1411 link_list1 {
1412 qcom,curr-link-list = <3>;
1413 qcom,data-sink = "sram";
1414 qcom,link-list = <DCC_READ 0x18220d14 3 0>,
1415 <DCC_READ 0x18220d30 4 0>,
1416 <DCC_READ 0x18220d44 4 0>,
1417 <DCC_READ 0x18220d58 4 0>,
1418 <DCC_READ 0x18220fb4 3 0>,
1419 <DCC_READ 0x18220fd0 4 0>,
1420 <DCC_READ 0x18220fe4 4 0>,
1421 <DCC_READ 0x18220ff8 4 0>,
1422 <DCC_READ 0x18220d04 1 0>,
1423 <DCC_READ 0x18220d00 1 0>,
1424 <DCC_READ 0x18000024 1 0>,
1425 <DCC_READ 0x18000040 4 0>,
1426 <DCC_READ 0x18010024 1 0>,
1427 <DCC_READ 0x18010040 4 0>,
1428 <DCC_READ 0x18020024 1 0>,
1429 <DCC_READ 0x18020040 4 0>,
1430 <DCC_READ 0x18030024 1 0>,
1431 <DCC_READ 0x18030040 4 0>,
1432 <DCC_READ 0x18040024 1 0>,
1433 <DCC_READ 0x18040040 4 0>,
1434 <DCC_READ 0x18050024 1 0>,
1435 <DCC_READ 0x18050040 4 0>,
1436 <DCC_READ 0x18060024 1 0>,
1437 <DCC_READ 0x18060040 4 0>,
1438 <DCC_READ 0x18070024 1 0>,
1439 <DCC_READ 0x18070040 4 0>,
1440 <DCC_READ 0x18080104 1 0>,
1441 <DCC_READ 0x18080168 1 0>,
1442 <DCC_READ 0x18080198 1 0>,
1443 <DCC_READ 0x18080128 1 0>,
1444 <DCC_READ 0x18080024 1 0>,
1445 <DCC_READ 0x18080040 3 0>,
1446 <DCC_READ 0x18200400 3 0>,
1447 <DCC_READ 0x0b201020 2 0>,
1448 <DCC_READ 0x0b204520 1 0>,
1449 <DCC_READ 0x1800005c 1 0>,
1450 <DCC_READ 0x1801005c 1 0>,
1451 <DCC_READ 0x1802005c 1 0>,
1452 <DCC_READ 0x1803005c 1 0>,
1453 <DCC_READ 0x1804005c 1 0>,
1454 <DCC_READ 0x1805005c 1 0>,
1455 <DCC_READ 0x1806005c 1 0>,
1456 <DCC_READ 0x1807005c 1 0>,
1457 <DCC_READ 0x18101908 1 0>,
1458 <DCC_READ 0x18101c18 1 0>,
1459 <DCC_READ 0x18390810 1 0>,
1460 <DCC_READ 0x18390c50 1 0>,
1461 <DCC_READ 0x18390814 1 0>,
1462 <DCC_READ 0x18390c54 1 0>,
1463 <DCC_READ 0x18390818 1 0>,
1464 <DCC_READ 0x18390c58 1 0>,
1465 <DCC_READ 0x18393a84 2 0>,
1466 <DCC_READ 0x18100908 1 0>,
1467 <DCC_READ 0x18100c18 1 0>,
1468 <DCC_READ 0x183a0810 1 0>,
1469 <DCC_READ 0x183a0c50 1 0>,
1470 <DCC_READ 0x183a0814 1 0>,
1471 <DCC_READ 0x183a0c54 1 0>,
1472 <DCC_READ 0x183a0818 1 0>,
1473 <DCC_READ 0x183a0c58 1 0>,
1474 <DCC_READ 0x183a3a84 2 0>,
1475 <DCC_READ 0x18393500 1 0>,
1476 <DCC_READ 0x18393580 1 0>,
1477 <DCC_READ 0x183a3500 1 0>,
1478 <DCC_READ 0x183a3580 1 0>,
1479 <DCC_READ 0x18282000 4 0>,
1480 <DCC_READ 0x18282028 1 0>,
1481 <DCC_READ 0x18282038 1 0>,
1482 <DCC_READ 0x18282080 5 0>,
1483 <DCC_READ 0x18286000 4 0>,
1484 <DCC_READ 0x18286028 1 0>,
1485 <DCC_READ 0x18286038 1 0>,
1486 <DCC_READ 0x18286080 5 0>,
1487 <DCC_READ 0x0c201244 1 0>,
1488 <DCC_READ 0x0c202244 1 0>,
1489 <DCC_READ 0x18300000 1 0>,
1490 <DCC_READ 0x1829208c 1 0>,
1491 <DCC_READ 0x18292098 1 0>,
1492 <DCC_READ 0x18292098 1 0>,
1493 <DCC_READ 0x1829608c 1 0>,
1494 <DCC_READ 0x18296098 1 0>,
1495 <DCC_READ 0x18296098 1 0>,
1496 <DCC_READ 0x091a9020 1 0>,
1497 <DCC_READ_WRITE 0x5 0x1 0>,
1498 <DCC_READ 0x09102008 1 0>,
1499 <DCC_READ_WRITE 0x2 0x2 0>,
1500 <DCC_READ 0x09142008 1 0>,
1501 <DCC_READ_WRITE 0x2 0x2 0>,
1502 <DCC_READ 0x09102408 1 0>,
1503 <DCC_READ_WRITE 0x2 0x2 0>,
1504 <DCC_READ 0x09142408 1 0>,
1505 <DCC_READ_WRITE 0x2 0x2 0>,
1506 <DCC_READ 0x09103808 1 0>,
1507 <DCC_LOOP 3 0 0>,
1508 <DCC_READ 0x09103810 1 0>,
1509 <DCC_READ 0x09103814 1 0>,
1510 <DCC_LOOP 1 0 0>,
1511 <DCC_READ 0x09103888 1 0>,
1512 <DCC_LOOP 2 0 0>,
1513 <DCC_READ 0x09103890 1 0>,
1514 <DCC_READ 0x09103894 1 0>,
1515 <DCC_LOOP 1 0 0>,
1516 <DCC_READ 0x09143808 1 0>,
1517 <DCC_LOOP 3 0 0>,
1518 <DCC_READ 0x09143810 1 0>,
1519 <DCC_READ 0x09143814 1 0>,
1520 <DCC_LOOP 1 0 0>,
1521 <DCC_READ 0x09143888 1 0>,
1522 <DCC_LOOP 2 0 0>,
1523 <DCC_READ 0x09143890 1 0>,
1524 <DCC_READ 0x09143894 1 0>,
1525 <DCC_LOOP 1 0 0>,
1526 <DCC_READ 0x09182808 1 0>,
1527 <DCC_LOOP 2 0 0>,
1528 <DCC_READ 0x09182810 1 0>,
1529 <DCC_READ 0x09182814 1 0>,
1530 <DCC_LOOP 1 0 0>,
1531 <DCC_READ 0x09182888 1 0>,
1532 <DCC_LOOP 3 0 0>,
1533 <DCC_READ 0x09182890 1 0>,
1534 <DCC_READ 0x09182894 1 0>,
1535 <DCC_LOOP 1 0 0>,
1536 <DCC_READ 0x09103008 1 0>,
1537 <DCC_READ 0x0910300c 1 0>,
1538 <DCC_WRITE 0x09103028 0x00000001 1>,
1539 <DCC_LOOP 41 0 0>,
1540 <DCC_READ 0x09103010 1 0>,
1541 <DCC_READ 0x09103014 1 0>,
1542 <DCC_LOOP 1 0 0>,
1543 <DCC_READ 0x09103408 1 0>,
1544 <DCC_READ 0x0910340c 1 0>,
1545 <DCC_WRITE 0x09103428 0x00000001 1>,
1546 <DCC_LOOP 41 0 0>,
1547 <DCC_READ 0x09103410 1 0>,
1548 <DCC_READ 0x09103414 1 0>,
1549 <DCC_LOOP 1 0 0>,
1550 <DCC_READ 0x09143008 1 0>,
1551 <DCC_READ 0x0914300c 1 0>,
1552 <DCC_WRITE 0x09143028 0x00000001 1>,
1553 <DCC_LOOP 41 0 0>,
1554 <DCC_READ 0x09143010 1 0>,
1555 <DCC_READ 0x09143014 1 0>,
1556 <DCC_LOOP 1 0 0>,
1557 <DCC_READ 0x09143408 1 0>,
1558 <DCC_READ 0x0914340c 1 0>,
1559 <DCC_WRITE 0x09143428 0x00000001 1>,
1560 <DCC_LOOP 41 0 0>,
1561 <DCC_READ 0x09143410 1 0>,
1562 <DCC_READ 0x09143414 1 0>,
1563 <DCC_LOOP 1 0 0>,
1564 <DCC_READ 0x09182008 1 0>,
1565 <DCC_READ 0x0918200c 1 0>,
1566 <DCC_WRITE 0x09182028 0x00000001 1>,
1567 <DCC_LOOP 11 0 0>,
1568 <DCC_READ 0x09182010 1 0>,
1569 <DCC_READ 0x09182014 1 0>,
1570 <DCC_LOOP 1 0 0>,
1571 <DCC_READ 0x09182408 1 0>,
1572 <DCC_READ 0x0918240c 1 0>,
1573 <DCC_WRITE 0x09182428 0x00000001 1>,
1574 <DCC_LOOP 11 0 0>,
1575 <DCC_READ 0x09182410 1 0>,
1576 <DCC_READ 0x09182414 1 0>,
1577 <DCC_LOOP 1 0 0>;
1578 };
1579
1580 link_list2 {
1581 qcom,curr-link-list = <6>;
1582 qcom,data-sink = "sram";
1583 qcom,link-list = <DCC_READ 0x9050078 1 0>,
1584 <DCC_READ 0x9050110 8 0>,
1585 <DCC_READ 0x9080058 2 0>,
1586 <DCC_READ 0x90800c8 1 0>,
1587 <DCC_READ 0x90800d4 1 0>,
1588 <DCC_READ 0x90800e0 1 0>,
1589 <DCC_READ 0x90800ec 1 0>,
1590 <DCC_READ 0x90800f8 1 0>,
1591 <DCC_READ 0x908401c 1 0>,
1592 <DCC_READ 0x908403c 1 0>,
1593 <DCC_READ 0x908404c 2 0>,
1594 <DCC_READ 0x90840d4 1 0>,
1595 <DCC_READ 0x9084204 1 0>,
1596 <DCC_READ 0x908420c 1 0>,
1597 <DCC_READ 0x9084250 2 0>,
1598 <DCC_READ 0x9084260 3 0>,
1599 <DCC_READ 0x9084280 1 0>,
1600 <DCC_READ 0x90ba280 1 0>,
1601 <DCC_READ 0x90ba288 7 0>,
1602 <DCC_READ 0x9258610 4 0>,
1603 <DCC_READ 0x92d8610 4 0>,
1604 <DCC_READ 0x9358610 4 0>,
1605 <DCC_READ 0x93d8610 4 0>,
1606 <DCC_READ 0x9220344 8 0>,
1607 <DCC_READ 0x9220370 6 0>,
1608 <DCC_READ 0x9220480 1 0>,
1609 <DCC_READ 0x9222400 1 0>,
1610 <DCC_READ 0x922240c 1 0>,
1611 <DCC_READ 0x9223214 2 0>,
1612 <DCC_READ 0x9223220 3 0>,
1613 <DCC_READ 0x9223308 1 0>,
1614 <DCC_READ 0x9223318 1 0>,
1615 <DCC_READ 0x9232100 1 0>,
1616 <DCC_READ 0x9236040 6 0>,
1617 <DCC_READ 0x92360b0 1 0>,
1618 <DCC_READ 0x923e030 2 0>,
1619 <DCC_READ 0x9241000 1 0>,
1620 <DCC_READ 0x9242028 1 0>,
1621 <DCC_READ 0x9242044 3 0>,
1622 <DCC_READ 0x9242070 1 0>,
1623 <DCC_READ 0x9248030 1 0>,
1624 <DCC_READ 0x9248048 8 0>,
1625 <DCC_READ 0x92a0344 8 0>,
1626 <DCC_READ 0x92a0370 6 0>,
1627 <DCC_READ 0x92a0480 1 0>,
1628 <DCC_READ 0x92a2400 1 0>,
1629 <DCC_READ 0x92a240c 1 0>,
1630 <DCC_READ 0x92a3214 2 0>,
1631 <DCC_READ 0x92a3220 3 0>,
1632 <DCC_READ 0x92a3308 1 0>,
1633 <DCC_READ 0x92a3318 1 0>,
1634 <DCC_READ 0x92b2100 1 0>,
1635 <DCC_READ 0x92b6040 6 0>,
1636 <DCC_READ 0x92b60b0 1 0>,
1637 <DCC_READ 0x92be030 2 0>,
1638 <DCC_READ 0x92c1000 1 0>,
1639 <DCC_READ 0x92c2028 1 0>,
1640 <DCC_READ 0x92c2044 3 0>,
1641 <DCC_READ 0x92c2070 1 0>,
1642 <DCC_READ 0x92c8030 1 0>,
1643 <DCC_READ 0x92c8048 8 0>,
1644 <DCC_READ 0x9320344 8 0>,
1645 <DCC_READ 0x9320370 6 0>,
1646 <DCC_READ 0x9320480 1 0>,
1647 <DCC_READ 0x9322400 1 0>,
1648 <DCC_READ 0x932240c 1 0>,
1649 <DCC_READ 0x9323214 2 0>,
1650 <DCC_READ 0x9323220 3 0>,
1651 <DCC_READ 0x9323308 1 0>,
1652 <DCC_READ 0x9323318 1 0>,
1653 <DCC_READ 0x9332100 1 0>,
1654 <DCC_READ 0x9336040 6 0>,
1655 <DCC_READ 0x93360b0 1 0>,
1656 <DCC_READ 0x933e030 2 0>,
1657 <DCC_READ 0x9341000 1 0>,
1658 <DCC_READ 0x9342028 1 0>,
1659 <DCC_READ 0x9342044 3 0>,
1660 <DCC_READ 0x9342070 1 0>,
1661 <DCC_READ 0x9348030 1 0>,
1662 <DCC_READ 0x9348048 8 0>,
1663 <DCC_READ 0x93a0344 8 0>,
1664 <DCC_READ 0x93a0370 6 0>,
1665 <DCC_READ 0x93a0480 1 0>,
1666 <DCC_READ 0x93a2400 1 0>,
1667 <DCC_READ 0x93a240c 1 0>,
1668 <DCC_READ 0x93a3214 2 0>,
1669 <DCC_READ 0x93a3220 3 0>,
1670 <DCC_READ 0x93a3308 1 0>,
1671 <DCC_READ 0x93a3318 1 0>,
1672 <DCC_READ 0x93b2100 1 0>,
1673 <DCC_READ 0x93b6040 6 0>,
1674 <DCC_READ 0x93b60b0 1 0>,
1675 <DCC_READ 0x93be030 2 0>,
1676 <DCC_READ 0x93c1000 1 0>,
1677 <DCC_READ 0x93c2028 1 0>,
1678 <DCC_READ 0x93c2044 3 0>,
1679 <DCC_READ 0x93c2070 1 0>,
1680 <DCC_READ 0x93c8030 1 0>,
1681 <DCC_READ 0x93c8048 8 0>,
1682 <DCC_READ 0x9270080 1 0>,
1683 <DCC_READ 0x9270400 1 0>,
1684 <DCC_READ 0x9270410 6 0>,
1685 <DCC_READ 0x9270430 1 0>,
1686 <DCC_READ 0x9270440 1 0>,
1687 <DCC_READ 0x9270448 1 0>,
1688 <DCC_READ 0x92704a0 1 0>,
1689 <DCC_READ 0x92704b0 1 0>,
1690 <DCC_READ 0x92704b8 2 0>,
1691 <DCC_READ 0x92704d0 1 0>,
1692 <DCC_READ 0x9271400 1 0>,
1693 <DCC_READ 0x92753b0 1 0>,
1694 <DCC_READ 0x9275c1c 1 0>,
1695 <DCC_READ 0x9275c2c 1 0>,
1696 <DCC_READ 0x9275c38 1 0>,
1697 <DCC_READ 0x9276418 2 0>,
1698 <DCC_READ 0x92f0080 1 0>,
1699 <DCC_READ 0x92f0400 1 0>,
1700 <DCC_READ 0x92f0410 6 0>,
1701 <DCC_READ 0x92f0430 1 0>,
1702 <DCC_READ 0x92f0440 1 0>,
1703 <DCC_READ 0x92f0448 1 0>,
1704 <DCC_READ 0x92f04a0 1 0>,
1705 <DCC_READ 0x92f04b0 1 0>,
1706 <DCC_READ 0x92f04b8 2 0>,
1707 <DCC_READ 0x92f04d0 1 0>,
1708 <DCC_READ 0x92f1400 1 0>,
1709 <DCC_READ 0x92f53b0 1 0>,
1710 <DCC_READ 0x92f5c1c 1 0>,
1711 <DCC_READ 0x92f5c2c 1 0>,
1712 <DCC_READ 0x92f5c38 1 0>,
1713 <DCC_READ 0x92f6418 2 0>,
1714 <DCC_READ 0x9370080 1 0>,
1715 <DCC_READ 0x9370400 1 0>,
1716 <DCC_READ 0x9370410 6 0>,
1717 <DCC_READ 0x9370430 1 0>,
1718 <DCC_READ 0x9370440 1 0>,
1719 <DCC_READ 0x9370448 1 0>,
1720 <DCC_READ 0x93704a0 1 0>,
1721 <DCC_READ 0x93704b0 1 0>,
1722 <DCC_READ 0x93704b8 2 0>,
1723 <DCC_READ 0x93704d0 1 0>,
1724 <DCC_READ 0x9371400 1 0>,
1725 <DCC_READ 0x93753b0 1 0>,
1726 <DCC_READ 0x9375c1c 1 0>,
1727 <DCC_READ 0x9375c2c 1 0>,
1728 <DCC_READ 0x9375c38 1 0>,
1729 <DCC_READ 0x9376418 2 0>,
1730 <DCC_READ 0x93f0080 1 0>,
1731 <DCC_READ 0x93f0400 1 0>,
1732 <DCC_READ 0x93f0410 6 0>,
1733 <DCC_READ 0x93f0430 1 0>,
1734 <DCC_READ 0x93f0440 1 0>,
1735 <DCC_READ 0x93f0448 1 0>,
1736 <DCC_READ 0x93f04a0 1 0>,
1737 <DCC_READ 0x93f04b0 1 0>,
1738 <DCC_READ 0x93f04b8 2 0>,
1739 <DCC_READ 0x93f04d0 1 0>,
1740 <DCC_READ 0x93f1400 1 0>,
1741 <DCC_READ 0x93f53b0 1 0>,
1742 <DCC_READ 0x93f5c1c 1 0>,
1743 <DCC_READ 0x93f5c2c 1 0>,
1744 <DCC_READ 0x93f5c38 1 0>,
1745 <DCC_READ 0x93f6418 2 0>,
1746 <DCC_READ 0x9260080 1 0>,
1747 <DCC_READ 0x9260400 1 0>,
1748 <DCC_READ 0x9260410 3 0>,
1749 <DCC_READ 0x9260420 2 0>,
1750 <DCC_READ 0x9260430 1 0>,
1751 <DCC_READ 0x9260440 1 0>,
1752 <DCC_READ 0x9260448 1 0>,
1753 <DCC_READ 0x92604a0 1 0>,
1754 <DCC_READ 0x92604b0 1 0>,
1755 <DCC_READ 0x92604b8 2 0>,
1756 <DCC_READ 0x92604d0 2 0>,
1757 <DCC_READ 0x9261400 1 0>,
1758 <DCC_READ 0x9263410 1 0>,
1759 <DCC_READ 0x92653b0 1 0>,
1760 <DCC_READ 0x9265804 1 0>,
1761 <DCC_READ 0x9265b1c 1 0>,
1762 <DCC_READ 0x9265b2c 1 0>,
1763 <DCC_READ 0x9265b38 1 0>,
1764 <DCC_READ 0x9269100 1 0>,
1765 <DCC_READ 0x9269110 1 0>,
1766 <DCC_READ 0x9269120 1 0>,
1767 <DCC_READ 0x92e0080 1 0>,
1768 <DCC_READ 0x92e0400 1 0>,
1769 <DCC_READ 0x92e0410 3 0>,
1770 <DCC_READ 0x92e0420 2 0>,
1771 <DCC_READ 0x92e0430 1 0>,
1772 <DCC_READ 0x92e0440 1 0>,
1773 <DCC_READ 0x92e0448 1 0>,
1774 <DCC_READ 0x92e04a0 1 0>,
1775 <DCC_READ 0x92e04b0 1 0>,
1776 <DCC_READ 0x92e04b8 2 0>,
1777 <DCC_READ 0x92e04d0 2 0>,
1778 <DCC_READ 0x92e1400 1 0>,
1779 <DCC_READ 0x92e3410 1 0>,
1780 <DCC_READ 0x92e53b0 1 0>,
1781 <DCC_READ 0x92e5804 1 0>,
1782 <DCC_READ 0x92e5b1c 1 0>,
1783 <DCC_READ 0x92e5b2c 1 0>,
1784 <DCC_READ 0x92e5b38 1 0>,
1785 <DCC_READ 0x92e9100 1 0>,
1786 <DCC_READ 0x92e9110 1 0>,
1787 <DCC_READ 0x92e9120 1 0>,
1788 <DCC_READ 0x9360080 1 0>,
1789 <DCC_READ 0x9360400 1 0>,
1790 <DCC_READ 0x9360410 3 0>,
1791 <DCC_READ 0x9360420 2 0>,
1792 <DCC_READ 0x9360430 1 0>,
1793 <DCC_READ 0x9360440 1 0>,
1794 <DCC_READ 0x9360448 1 0>,
1795 <DCC_READ 0x93604a0 1 0>,
1796 <DCC_READ 0x93604b0 1 0>,
1797 <DCC_READ 0x93604b8 2 0>,
1798 <DCC_READ 0x93604d0 2 0>,
1799 <DCC_READ 0x9361400 1 0>,
1800 <DCC_READ 0x9363410 1 0>,
1801 <DCC_READ 0x93653b0 1 0>,
1802 <DCC_READ 0x9365804 1 0>,
1803 <DCC_READ 0x9365b1c 1 0>,
1804 <DCC_READ 0x9365b2c 1 0>,
1805 <DCC_READ 0x9365b38 1 0>,
1806 <DCC_READ 0x9369100 1 0>,
1807 <DCC_READ 0x9369110 1 0>,
1808 <DCC_READ 0x9369120 1 0>,
1809 <DCC_READ 0x93e0080 1 0>,
1810 <DCC_READ 0x93e0400 1 0>,
1811 <DCC_READ 0x93e0410 3 0>,
1812 <DCC_READ 0x93e0420 2 0>,
1813 <DCC_READ 0x93e0430 1 0>,
1814 <DCC_READ 0x93e0440 1 0>,
1815 <DCC_READ 0x93e0448 1 0>,
1816 <DCC_READ 0x93e04a0 1 0>,
1817 <DCC_READ 0x93e04b0 1 0>,
1818 <DCC_READ 0x93e04b8 2 0>,
1819 <DCC_READ 0x93e04d0 2 0>,
1820 <DCC_READ 0x93e1400 1 0>,
1821 <DCC_READ 0x93e3410 1 0>,
1822 <DCC_READ 0x93e53b0 1 0>,
1823 <DCC_READ 0x93e5804 1 0>,
1824 <DCC_READ 0x93e5b1c 1 0>,
1825 <DCC_READ 0x93e5b2c 1 0>,
1826 <DCC_READ 0x93e5b38 1 0>,
1827 <DCC_READ 0x93e9100 1 0>,
1828 <DCC_READ 0x93e9110 1 0>,
1829 <DCC_READ 0x93e9120 1 0>,
1830 <DCC_READ 0x96b0868 1 0>,
1831 <DCC_READ 0x96b0870 1 0>,
1832 <DCC_READ 0x96b1004 1 0>,
1833 <DCC_READ 0x96b100c 1 0>,
1834 <DCC_READ 0x96b1014 1 0>,
1835 <DCC_READ 0x96b1204 1 0>,
1836 <DCC_READ 0x96b120c 1 0>,
1837 <DCC_READ 0x96b1214 1 0>,
1838 <DCC_READ 0x96b1504 1 0>,
1839 <DCC_READ 0x96b150c 1 0>,
1840 <DCC_READ 0x96b1514 1 0>,
1841 <DCC_READ 0x96b1604 1 0>,
1842 <DCC_READ 0x96b8100 1 0>,
1843 <DCC_READ 0x96b813c 1 0>,
1844 <DCC_READ 0x96b8500 1 0>,
1845 <DCC_READ 0x96b853c 1 0>,
1846 <DCC_READ 0x96b8a04 1 0>,
1847 <DCC_READ 0x96b8a18 1 0>,
1848 <DCC_READ 0x96b8ea8 1 0>,
1849 <DCC_READ 0x96b9044 1 0>,
1850 <DCC_READ 0x96b904c 1 0>,
1851 <DCC_READ 0x96b9054 1 0>,
1852 <DCC_READ 0x96b905c 1 0>,
1853 <DCC_READ 0x96b910c 2 0>,
1854 <DCC_READ 0x96b9204 1 0>,
1855 <DCC_READ 0x96b920c 1 0>,
1856 <DCC_READ 0x96b9238 1 0>,
1857 <DCC_READ 0x96b9240 1 0>,
1858 <DCC_READ 0x96b926c 1 0>,
1859 <DCC_READ 0x96b9394 1 0>,
1860 <DCC_READ 0x96b939c 1 0>,
1861 <DCC_READ 0x96b9704 1 0>,
1862 <DCC_READ 0x96b970c 1 0>,
1863 <DCC_READ 0x96f0868 1 0>,
1864 <DCC_READ 0x96f0870 1 0>,
1865 <DCC_READ 0x96f1004 1 0>,
1866 <DCC_READ 0x96f100c 1 0>,
1867 <DCC_READ 0x96f1014 1 0>,
1868 <DCC_READ 0x96f1204 1 0>,
1869 <DCC_READ 0x96f120c 1 0>,
1870 <DCC_READ 0x96f1214 1 0>,
1871 <DCC_READ 0x96f1504 1 0>,
1872 <DCC_READ 0x96f150c 1 0>,
1873 <DCC_READ 0x96f1514 1 0>,
1874 <DCC_READ 0x96f1604 1 0>,
1875 <DCC_READ 0x96f8100 1 0>,
1876 <DCC_READ 0x96f813c 1 0>,
1877 <DCC_READ 0x96f8500 1 0>,
1878 <DCC_READ 0x96f853c 1 0>,
1879 <DCC_READ 0x96f8a04 1 0>,
1880 <DCC_READ 0x96f8a18 1 0>,
1881 <DCC_READ 0x96f8ea8 1 0>,
1882 <DCC_READ 0x96f9044 1 0>,
1883 <DCC_READ 0x96f904c 1 0>,
1884 <DCC_READ 0x96f9054 1 0>,
1885 <DCC_READ 0x96f905c 1 0>,
1886 <DCC_READ 0x96f910c 2 0>,
1887 <DCC_READ 0x96f9204 1 0>,
1888 <DCC_READ 0x96f920c 1 0>,
1889 <DCC_READ 0x96f9238 1 0>,
1890 <DCC_READ 0x96f9240 1 0>,
1891 <DCC_READ 0x96f926c 1 0>,
1892 <DCC_READ 0x96f9394 1 0>,
1893 <DCC_READ 0x96f939c 1 0>,
1894 <DCC_READ 0x96f9704 1 0>,
1895 <DCC_READ 0x96f970c 1 0>,
1896 <DCC_READ 0x9730868 1 0>,
1897 <DCC_READ 0x9730870 1 0>,
1898 <DCC_READ 0x9731004 1 0>,
1899 <DCC_READ 0x973100c 1 0>,
1900 <DCC_READ 0x9731014 1 0>,
1901 <DCC_READ 0x9731204 1 0>,
1902 <DCC_READ 0x973120c 1 0>,
1903 <DCC_READ 0x9731214 1 0>,
1904 <DCC_READ 0x9731504 1 0>,
1905 <DCC_READ 0x973150c 1 0>,
1906 <DCC_READ 0x9731514 1 0>,
1907 <DCC_READ 0x9731604 1 0>,
1908 <DCC_READ 0x9738100 1 0>,
1909 <DCC_READ 0x973813c 1 0>,
1910 <DCC_READ 0x9738500 1 0>,
1911 <DCC_READ 0x973853c 1 0>,
1912 <DCC_READ 0x9738a04 1 0>,
1913 <DCC_READ 0x9738a18 1 0>,
1914 <DCC_READ 0x9738ea8 1 0>,
1915 <DCC_READ 0x9739044 1 0>,
1916 <DCC_READ 0x973904c 1 0>,
1917 <DCC_READ 0x9739054 1 0>,
1918 <DCC_READ 0x973905c 1 0>,
1919 <DCC_READ 0x973910c 2 0>,
1920 <DCC_READ 0x9739204 1 0>,
1921 <DCC_READ 0x973920c 1 0>,
1922 <DCC_READ 0x9739238 1 0>,
1923 <DCC_READ 0x9739240 1 0>,
1924 <DCC_READ 0x973926c 1 0>,
1925 <DCC_READ 0x9739394 1 0>,
1926 <DCC_READ 0x973939c 1 0>,
1927 <DCC_READ 0x9739704 1 0>,
1928 <DCC_READ 0x973970c 1 0>,
1929 <DCC_READ 0x9770868 1 0>,
1930 <DCC_READ 0x9770870 1 0>,
1931 <DCC_READ 0x9771004 1 0>,
1932 <DCC_READ 0x977100c 1 0>,
1933 <DCC_READ 0x9771014 1 0>,
1934 <DCC_READ 0x9771204 1 0>,
1935 <DCC_READ 0x977120c 1 0>,
1936 <DCC_READ 0x9771214 1 0>,
1937 <DCC_READ 0x9771504 1 0>,
1938 <DCC_READ 0x977150c 1 0>,
1939 <DCC_READ 0x9771514 1 0>,
1940 <DCC_READ 0x9771604 1 0>,
1941 <DCC_READ 0x9778100 1 0>,
1942 <DCC_READ 0x977813c 1 0>,
1943 <DCC_READ 0x9778500 1 0>,
1944 <DCC_READ 0x977853c 1 0>,
1945 <DCC_READ 0x9778a04 1 0>,
1946 <DCC_READ 0x9778a18 1 0>,
1947 <DCC_READ 0x9778ea8 1 0>,
1948 <DCC_READ 0x9779044 1 0>,
1949 <DCC_READ 0x977904c 1 0>,
1950 <DCC_READ 0x9779054 1 0>,
1951 <DCC_READ 0x977905c 1 0>,
1952 <DCC_READ 0x977910c 2 0>,
1953 <DCC_READ 0x9779204 1 0>,
1954 <DCC_READ 0x977920c 1 0>,
1955 <DCC_READ 0x9779238 1 0>,
1956 <DCC_READ 0x9779240 1 0>,
1957 <DCC_READ 0x977926c 1 0>,
1958 <DCC_READ 0x9779394 1 0>,
1959 <DCC_READ 0x977939c 1 0>,
1960 <DCC_READ 0x9779704 1 0>,
1961 <DCC_READ 0x977970c 1 0>,
1962 <DCC_READ 0x910d100 3 0>,
1963 <DCC_READ 0x914d100 3 0>,
1964 <DCC_READ 0x918d100 4 0>,
1965 <DCC_READ 0x91a5100 1 0>,
1966 <DCC_READ 0x91ad100 1 0>;
1967 };
1968
1969 link_list3 {
1970 qcom,curr-link-list = <7>;
1971 qcom,data-sink = "sram";
1972 qcom,link-list = <DCC_READ 0x9050078 1 0>,
1973 <DCC_READ 0x9050110 8 0>,
1974 <DCC_READ 0x9080058 2 0>,
1975 <DCC_READ 0x90800c8 1 0>,
1976 <DCC_READ 0x90800d4 1 0>,
1977 <DCC_READ 0x90800e0 1 0>,
1978 <DCC_READ 0x90800ec 1 0>,
1979 <DCC_READ 0x90800f8 1 0>,
1980 <DCC_READ 0x908401c 1 0>,
1981 <DCC_READ 0x908403c 1 0>,
1982 <DCC_READ 0x908404c 2 0>,
1983 <DCC_READ 0x90840d4 1 0>,
1984 <DCC_READ 0x9084204 1 0>,
1985 <DCC_READ 0x908420c 1 0>,
1986 <DCC_READ 0x9084250 2 0>,
1987 <DCC_READ 0x9084260 3 0>,
1988 <DCC_READ 0x9084280 1 0>,
1989 <DCC_READ 0x90ba280 1 0>,
1990 <DCC_READ 0x90ba288 7 0>,
1991 <DCC_READ 0x9258610 4 0>,
1992 <DCC_READ 0x92d8610 4 0>,
1993 <DCC_READ 0x9358610 4 0>,
1994 <DCC_READ 0x93d8610 4 0>,
1995 <DCC_READ 0x9220344 8 0>,
1996 <DCC_READ 0x9220370 6 0>,
1997 <DCC_READ 0x9220480 1 0>,
1998 <DCC_READ 0x9222400 1 0>,
1999 <DCC_READ 0x922240c 1 0>,
2000 <DCC_READ 0x9223214 2 0>,
2001 <DCC_READ 0x9223220 3 0>,
2002 <DCC_READ 0x9223308 1 0>,
2003 <DCC_READ 0x9223318 1 0>,
2004 <DCC_READ 0x9232100 1 0>,
2005 <DCC_READ 0x9236040 6 0>,
2006 <DCC_READ 0x92360b0 1 0>,
2007 <DCC_READ 0x923e030 2 0>,
2008 <DCC_READ 0x9241000 1 0>,
2009 <DCC_READ 0x9242028 1 0>,
2010 <DCC_READ 0x9242044 3 0>,
2011 <DCC_READ 0x9242070 1 0>,
2012 <DCC_READ 0x9248030 1 0>,
2013 <DCC_READ 0x9248048 8 0>,
2014 <DCC_READ 0x92a0344 8 0>,
2015 <DCC_READ 0x92a0370 6 0>,
2016 <DCC_READ 0x92a0480 1 0>,
2017 <DCC_READ 0x92a2400 1 0>,
2018 <DCC_READ 0x92a240c 1 0>,
2019 <DCC_READ 0x92a3214 2 0>,
2020 <DCC_READ 0x92a3220 3 0>,
2021 <DCC_READ 0x92a3308 1 0>,
2022 <DCC_READ 0x92a3318 1 0>,
2023 <DCC_READ 0x92b2100 1 0>,
2024 <DCC_READ 0x92b6040 6 0>,
2025 <DCC_READ 0x92b60b0 1 0>,
2026 <DCC_READ 0x92be030 2 0>,
2027 <DCC_READ 0x92c1000 1 0>,
2028 <DCC_READ 0x92c2028 1 0>,
2029 <DCC_READ 0x92c2044 3 0>,
2030 <DCC_READ 0x92c2070 1 0>,
2031 <DCC_READ 0x92c8030 1 0>,
2032 <DCC_READ 0x92c8048 8 0>,
2033 <DCC_READ 0x9320344 8 0>,
2034 <DCC_READ 0x9320370 6 0>,
2035 <DCC_READ 0x9320480 1 0>,
2036 <DCC_READ 0x9322400 1 0>,
2037 <DCC_READ 0x932240c 1 0>,
2038 <DCC_READ 0x9323214 2 0>,
2039 <DCC_READ 0x9323220 3 0>,
2040 <DCC_READ 0x9323308 1 0>,
2041 <DCC_READ 0x9323318 1 0>,
2042 <DCC_READ 0x9332100 1 0>,
2043 <DCC_READ 0x9336040 6 0>,
2044 <DCC_READ 0x93360b0 1 0>,
2045 <DCC_READ 0x933e030 2 0>,
2046 <DCC_READ 0x9341000 1 0>,
2047 <DCC_READ 0x9342028 1 0>,
2048 <DCC_READ 0x9342044 3 0>,
2049 <DCC_READ 0x9342070 1 0>,
2050 <DCC_READ 0x9348030 1 0>,
2051 <DCC_READ 0x9348048 8 0>,
2052 <DCC_READ 0x93a0344 8 0>,
2053 <DCC_READ 0x93a0370 6 0>,
2054 <DCC_READ 0x93a0480 1 0>,
2055 <DCC_READ 0x93a2400 1 0>,
2056 <DCC_READ 0x93a240c 1 0>,
2057 <DCC_READ 0x93a3214 2 0>,
2058 <DCC_READ 0x93a3220 3 0>,
2059 <DCC_READ 0x93a3308 1 0>,
2060 <DCC_READ 0x93a3318 1 0>,
2061 <DCC_READ 0x93b2100 1 0>,
2062 <DCC_READ 0x93b6040 6 0>,
2063 <DCC_READ 0x93b60b0 1 0>,
2064 <DCC_READ 0x93be030 2 0>,
2065 <DCC_READ 0x93c1000 1 0>,
2066 <DCC_READ 0x93c2028 1 0>,
2067 <DCC_READ 0x93c2044 3 0>,
2068 <DCC_READ 0x93c2070 1 0>,
2069 <DCC_READ 0x93c8030 1 0>,
2070 <DCC_READ 0x93c8048 8 0>,
2071 <DCC_READ 0x9270080 1 0>,
2072 <DCC_READ 0x9270400 1 0>,
2073 <DCC_READ 0x9270410 6 0>,
2074 <DCC_READ 0x9270430 1 0>,
2075 <DCC_READ 0x9270440 1 0>,
2076 <DCC_READ 0x9270448 1 0>,
2077 <DCC_READ 0x92704a0 1 0>,
2078 <DCC_READ 0x92704b0 1 0>,
2079 <DCC_READ 0x92704b8 2 0>,
2080 <DCC_READ 0x92704d0 1 0>,
2081 <DCC_READ 0x9271400 1 0>,
2082 <DCC_READ 0x92753b0 1 0>,
2083 <DCC_READ 0x9275c1c 1 0>,
2084 <DCC_READ 0x9275c2c 1 0>,
2085 <DCC_READ 0x9275c38 1 0>,
2086 <DCC_READ 0x9276418 2 0>,
2087 <DCC_READ 0x92f0080 1 0>,
2088 <DCC_READ 0x92f0400 1 0>,
2089 <DCC_READ 0x92f0410 6 0>,
2090 <DCC_READ 0x92f0430 1 0>,
2091 <DCC_READ 0x92f0440 1 0>,
2092 <DCC_READ 0x92f0448 1 0>,
2093 <DCC_READ 0x92f04a0 1 0>,
2094 <DCC_READ 0x92f04b0 1 0>,
2095 <DCC_READ 0x92f04b8 2 0>,
2096 <DCC_READ 0x92f04d0 1 0>,
2097 <DCC_READ 0x92f1400 1 0>,
2098 <DCC_READ 0x92f53b0 1 0>,
2099 <DCC_READ 0x92f5c1c 1 0>,
2100 <DCC_READ 0x92f5c2c 1 0>,
2101 <DCC_READ 0x92f5c38 1 0>,
2102 <DCC_READ 0x92f6418 2 0>,
2103 <DCC_READ 0x9370080 1 0>,
2104 <DCC_READ 0x9370400 1 0>,
2105 <DCC_READ 0x9370410 6 0>,
2106 <DCC_READ 0x9370430 1 0>,
2107 <DCC_READ 0x9370440 1 0>,
2108 <DCC_READ 0x9370448 1 0>,
2109 <DCC_READ 0x93704a0 1 0>,
2110 <DCC_READ 0x93704b0 1 0>,
2111 <DCC_READ 0x93704b8 2 0>,
2112 <DCC_READ 0x93704d0 1 0>,
2113 <DCC_READ 0x9371400 1 0>,
2114 <DCC_READ 0x93753b0 1 0>,
2115 <DCC_READ 0x9375c1c 1 0>,
2116 <DCC_READ 0x9375c2c 1 0>,
2117 <DCC_READ 0x9375c38 1 0>,
2118 <DCC_READ 0x9376418 2 0>,
2119 <DCC_READ 0x93f0080 1 0>,
2120 <DCC_READ 0x93f0400 1 0>,
2121 <DCC_READ 0x93f0410 6 0>,
2122 <DCC_READ 0x93f0430 1 0>,
2123 <DCC_READ 0x93f0440 1 0>,
2124 <DCC_READ 0x93f0448 1 0>,
2125 <DCC_READ 0x93f04a0 1 0>,
2126 <DCC_READ 0x93f04b0 1 0>,
2127 <DCC_READ 0x93f04b8 2 0>,
2128 <DCC_READ 0x93f04d0 1 0>,
2129 <DCC_READ 0x93f1400 1 0>,
2130 <DCC_READ 0x93f53b0 1 0>,
2131 <DCC_READ 0x93f5c1c 1 0>,
2132 <DCC_READ 0x93f5c2c 1 0>,
2133 <DCC_READ 0x93f5c38 1 0>,
2134 <DCC_READ 0x93f6418 2 0>,
2135 <DCC_READ 0x9260080 1 0>,
2136 <DCC_READ 0x9260400 1 0>,
2137 <DCC_READ 0x9260410 3 0>,
2138 <DCC_READ 0x9260420 2 0>,
2139 <DCC_READ 0x9260430 1 0>,
2140 <DCC_READ 0x9260440 1 0>,
2141 <DCC_READ 0x9260448 1 0>,
2142 <DCC_READ 0x92604a0 1 0>,
2143 <DCC_READ 0x92604b0 1 0>,
2144 <DCC_READ 0x92604b8 2 0>,
2145 <DCC_READ 0x92604d0 2 0>,
2146 <DCC_READ 0x9261400 1 0>,
2147 <DCC_READ 0x9263410 1 0>,
2148 <DCC_READ 0x92653b0 1 0>,
2149 <DCC_READ 0x9265804 1 0>,
2150 <DCC_READ 0x9265b1c 1 0>,
2151 <DCC_READ 0x9265b2c 1 0>,
2152 <DCC_READ 0x9265b38 1 0>,
2153 <DCC_READ 0x9269100 1 0>,
2154 <DCC_READ 0x9269110 1 0>,
2155 <DCC_READ 0x9269120 1 0>,
2156 <DCC_READ 0x92e0080 1 0>,
2157 <DCC_READ 0x92e0400 1 0>,
2158 <DCC_READ 0x92e0410 3 0>,
2159 <DCC_READ 0x92e0420 2 0>,
2160 <DCC_READ 0x92e0430 1 0>,
2161 <DCC_READ 0x92e0440 1 0>,
2162 <DCC_READ 0x92e0448 1 0>,
2163 <DCC_READ 0x92e04a0 1 0>,
2164 <DCC_READ 0x92e04b0 1 0>,
2165 <DCC_READ 0x92e04b8 2 0>,
2166 <DCC_READ 0x92e04d0 2 0>,
2167 <DCC_READ 0x92e1400 1 0>,
2168 <DCC_READ 0x92e3410 1 0>,
2169 <DCC_READ 0x92e53b0 1 0>,
2170 <DCC_READ 0x92e5804 1 0>,
2171 <DCC_READ 0x92e5b1c 1 0>,
2172 <DCC_READ 0x92e5b2c 1 0>,
2173 <DCC_READ 0x92e5b38 1 0>,
2174 <DCC_READ 0x92e9100 1 0>,
2175 <DCC_READ 0x92e9110 1 0>,
2176 <DCC_READ 0x92e9120 1 0>,
2177 <DCC_READ 0x9360080 1 0>,
2178 <DCC_READ 0x9360400 1 0>,
2179 <DCC_READ 0x9360410 3 0>,
2180 <DCC_READ 0x9360420 2 0>,
2181 <DCC_READ 0x9360430 1 0>,
2182 <DCC_READ 0x9360440 1 0>,
2183 <DCC_READ 0x9360448 1 0>,
2184 <DCC_READ 0x93604a0 1 0>,
2185 <DCC_READ 0x93604b0 1 0>,
2186 <DCC_READ 0x93604b8 2 0>,
2187 <DCC_READ 0x93604d0 2 0>,
2188 <DCC_READ 0x9361400 1 0>,
2189 <DCC_READ 0x9363410 1 0>,
2190 <DCC_READ 0x93653b0 1 0>,
2191 <DCC_READ 0x9365804 1 0>,
2192 <DCC_READ 0x9365b1c 1 0>,
2193 <DCC_READ 0x9365b2c 1 0>,
2194 <DCC_READ 0x9365b38 1 0>,
2195 <DCC_READ 0x9369100 1 0>,
2196 <DCC_READ 0x9369110 1 0>,
2197 <DCC_READ 0x9369120 1 0>,
2198 <DCC_READ 0x93e0080 1 0>,
2199 <DCC_READ 0x93e0400 1 0>,
2200 <DCC_READ 0x93e0410 3 0>,
2201 <DCC_READ 0x93e0420 2 0>,
2202 <DCC_READ 0x93e0430 1 0>,
2203 <DCC_READ 0x93e0440 1 0>,
2204 <DCC_READ 0x93e0448 1 0>,
2205 <DCC_READ 0x93e04a0 1 0>,
2206 <DCC_READ 0x93e04b0 1 0>,
2207 <DCC_READ 0x93e04b8 2 0>,
2208 <DCC_READ 0x93e04d0 2 0>,
2209 <DCC_READ 0x93e1400 1 0>,
2210 <DCC_READ 0x93e3410 1 0>,
2211 <DCC_READ 0x93e53b0 1 0>,
2212 <DCC_READ 0x93e5804 1 0>,
2213 <DCC_READ 0x93e5b1c 1 0>,
2214 <DCC_READ 0x93e5b2c 1 0>,
2215 <DCC_READ 0x93e5b38 1 0>,
2216 <DCC_READ 0x93e9100 1 0>,
2217 <DCC_READ 0x93e9110 1 0>,
2218 <DCC_READ 0x93e9120 1 0>,
2219 <DCC_READ 0x96b0868 1 0>,
2220 <DCC_READ 0x96b0870 1 0>,
2221 <DCC_READ 0x96b1004 1 0>,
2222 <DCC_READ 0x96b100c 1 0>,
2223 <DCC_READ 0x96b1014 1 0>,
2224 <DCC_READ 0x96b1204 1 0>,
2225 <DCC_READ 0x96b120c 1 0>,
2226 <DCC_READ 0x96b1214 1 0>,
2227 <DCC_READ 0x96b1504 1 0>,
2228 <DCC_READ 0x96b150c 1 0>,
2229 <DCC_READ 0x96b1514 1 0>,
2230 <DCC_READ 0x96b1604 1 0>,
2231 <DCC_READ 0x96b8100 1 0>,
2232 <DCC_READ 0x96b813c 1 0>,
2233 <DCC_READ 0x96b8500 1 0>,
2234 <DCC_READ 0x96b853c 1 0>,
2235 <DCC_READ 0x96b8a04 1 0>,
2236 <DCC_READ 0x96b8a18 1 0>,
2237 <DCC_READ 0x96b8ea8 1 0>,
2238 <DCC_READ 0x96b9044 1 0>,
2239 <DCC_READ 0x96b904c 1 0>,
2240 <DCC_READ 0x96b9054 1 0>,
2241 <DCC_READ 0x96b905c 1 0>,
2242 <DCC_READ 0x96b910c 2 0>,
2243 <DCC_READ 0x96b9204 1 0>,
2244 <DCC_READ 0x96b920c 1 0>,
2245 <DCC_READ 0x96b9238 1 0>,
2246 <DCC_READ 0x96b9240 1 0>,
2247 <DCC_READ 0x96b926c 1 0>,
2248 <DCC_READ 0x96b9394 1 0>,
2249 <DCC_READ 0x96b939c 1 0>,
2250 <DCC_READ 0x96b9704 1 0>,
2251 <DCC_READ 0x96b970c 1 0>,
2252 <DCC_READ 0x96f0868 1 0>,
2253 <DCC_READ 0x96f0870 1 0>,
2254 <DCC_READ 0x96f1004 1 0>,
2255 <DCC_READ 0x96f100c 1 0>,
2256 <DCC_READ 0x96f1014 1 0>,
2257 <DCC_READ 0x96f1204 1 0>,
2258 <DCC_READ 0x96f120c 1 0>,
2259 <DCC_READ 0x96f1214 1 0>,
2260 <DCC_READ 0x96f1504 1 0>,
2261 <DCC_READ 0x96f150c 1 0>,
2262 <DCC_READ 0x96f1514 1 0>,
2263 <DCC_READ 0x96f1604 1 0>,
2264 <DCC_READ 0x96f8100 1 0>,
2265 <DCC_READ 0x96f813c 1 0>,
2266 <DCC_READ 0x96f8500 1 0>,
2267 <DCC_READ 0x96f853c 1 0>,
2268 <DCC_READ 0x96f8a04 1 0>,
2269 <DCC_READ 0x96f8a18 1 0>,
2270 <DCC_READ 0x96f8ea8 1 0>,
2271 <DCC_READ 0x96f9044 1 0>,
2272 <DCC_READ 0x96f904c 1 0>,
2273 <DCC_READ 0x96f9054 1 0>,
2274 <DCC_READ 0x96f905c 1 0>,
2275 <DCC_READ 0x96f910c 2 0>,
2276 <DCC_READ 0x96f9204 1 0>,
2277 <DCC_READ 0x96f920c 1 0>,
2278 <DCC_READ 0x96f9238 1 0>,
2279 <DCC_READ 0x96f9240 1 0>,
2280 <DCC_READ 0x96f926c 1 0>,
2281 <DCC_READ 0x96f9394 1 0>,
2282 <DCC_READ 0x96f939c 1 0>,
2283 <DCC_READ 0x96f9704 1 0>,
2284 <DCC_READ 0x96f970c 1 0>,
2285 <DCC_READ 0x9730868 1 0>,
2286 <DCC_READ 0x9730870 1 0>,
2287 <DCC_READ 0x9731004 1 0>,
2288 <DCC_READ 0x973100c 1 0>,
2289 <DCC_READ 0x9731014 1 0>,
2290 <DCC_READ 0x9731204 1 0>,
2291 <DCC_READ 0x973120c 1 0>,
2292 <DCC_READ 0x9731214 1 0>,
2293 <DCC_READ 0x9731504 1 0>,
2294 <DCC_READ 0x973150c 1 0>,
2295 <DCC_READ 0x9731514 1 0>,
2296 <DCC_READ 0x9731604 1 0>,
2297 <DCC_READ 0x9738100 1 0>,
2298 <DCC_READ 0x973813c 1 0>,
2299 <DCC_READ 0x9738500 1 0>,
2300 <DCC_READ 0x973853c 1 0>,
2301 <DCC_READ 0x9738a04 1 0>,
2302 <DCC_READ 0x9738a18 1 0>,
2303 <DCC_READ 0x9738ea8 1 0>,
2304 <DCC_READ 0x9739044 1 0>,
2305 <DCC_READ 0x973904c 1 0>,
2306 <DCC_READ 0x9739054 1 0>,
2307 <DCC_READ 0x973905c 1 0>,
2308 <DCC_READ 0x973910c 2 0>,
2309 <DCC_READ 0x9739204 1 0>,
2310 <DCC_READ 0x973920c 1 0>,
2311 <DCC_READ 0x9739238 1 0>,
2312 <DCC_READ 0x9739240 1 0>,
2313 <DCC_READ 0x973926c 1 0>,
2314 <DCC_READ 0x9739394 1 0>,
2315 <DCC_READ 0x973939c 1 0>,
2316 <DCC_READ 0x9739704 1 0>,
2317 <DCC_READ 0x973970c 1 0>,
2318 <DCC_READ 0x9770868 1 0>,
2319 <DCC_READ 0x9770870 1 0>,
2320 <DCC_READ 0x9771004 1 0>,
2321 <DCC_READ 0x977100c 1 0>,
2322 <DCC_READ 0x9771014 1 0>,
2323 <DCC_READ 0x9771204 1 0>,
2324 <DCC_READ 0x977120c 1 0>,
2325 <DCC_READ 0x9771214 1 0>,
2326 <DCC_READ 0x9771504 1 0>,
2327 <DCC_READ 0x977150c 1 0>,
2328 <DCC_READ 0x9771514 1 0>,
2329 <DCC_READ 0x9771604 1 0>,
2330 <DCC_READ 0x9778100 1 0>,
2331 <DCC_READ 0x977813c 1 0>,
2332 <DCC_READ 0x9778500 1 0>,
2333 <DCC_READ 0x977853c 1 0>,
2334 <DCC_READ 0x9778a04 1 0>,
2335 <DCC_READ 0x9778a18 1 0>,
2336 <DCC_READ 0x9778ea8 1 0>,
2337 <DCC_READ 0x9779044 1 0>,
2338 <DCC_READ 0x977904c 1 0>,
2339 <DCC_READ 0x9779054 1 0>,
2340 <DCC_READ 0x977905c 1 0>,
2341 <DCC_READ 0x977910c 2 0>,
2342 <DCC_READ 0x9779204 1 0>,
2343 <DCC_READ 0x977920c 1 0>,
2344 <DCC_READ 0x9779238 1 0>,
2345 <DCC_READ 0x9779240 1 0>,
2346 <DCC_READ 0x977926c 1 0>,
2347 <DCC_READ 0x9779394 1 0>,
2348 <DCC_READ 0x977939c 1 0>,
2349 <DCC_READ 0x9779704 1 0>,
2350 <DCC_READ 0x977970c 1 0>,
2351 <DCC_READ 0x910d100 3 0>,
2352 <DCC_READ 0x914d100 3 0>,
2353 <DCC_READ 0x918d100 4 0>,
2354 <DCC_READ 0x91a5100 1 0>,
2355 <DCC_READ 0x91ad100 1 0>;
2356 };
2357
2358 };
2359
2360 qcom_seecom: qseecom@82400000 {
2361 compatible = "qcom,qseecom";
2362 reg = <0x82400000 0x3A00000>;
2363 reg-names = "secapp-region";
2364 memory-region = <&qseecom_mem>;
2365 qcom,hlos-num-ce-hw-instances = <1>;
2366 qcom,hlos-ce-hw-instance = <0>;
2367 qcom,qsee-ce-hw-instance = <0>;
2368 qcom,disk-encrypt-pipe-pair = <2>;
2369 qcom,support-fde;
2370 qcom,no-clock-support;
2371 qcom,fde-key-size;
2372 qcom,appsbl-qseecom-support;
2373 qcom,commonlib64-loaded-by-uefi;
2374 qcom,qsee-reentrancy-support = <2>;
2375 };
2376
2377 qcom_rng: qrng@793000 {
2378 compatible = "qcom,msm-rng";
2379 reg = <0x793000 0x1000>;
2380 qcom,msm-rng-iface-clk;
2381 qcom,no-qrng-config;
2382 qcom,msm-bus,name = "msm-rng-noc";
2383 qcom,msm-bus,num-cases = <2>;
2384 qcom,msm-bus,num-paths = <1>;
2385 qcom,msm-bus,vectors-KBps =
2386 <1 618 0 0>, /* No vote */
2387 <1 618 0 300000>; /* 75 MHz */
2388 clocks = <&clock_gcc GCC_PRNG_AHB_CLK>;
2389 clock-names = "iface_clk";
2390 };
2391
2392 mdm0: qcom,mdm0 {
2393 compatible = "qcom,ext-sdx55m";
2394 cell-index = <0>;
2395 #address-cells = <0>;
2396 interrupt-parent = <&mdm0>;
2397 #interrupt-cells = <1>;
2398 interrupt-map-mask = <0xffffffff>;
2399 interrupt-names =
2400 "err_fatal_irq",
2401 "status_irq",
2402 "mdm2ap_vddmin_irq";
2403 /* modem attributes */
2404 qcom,ramdump-delay-ms = <3000>;
2405 qcom,ramdump-timeout-ms = <120000>;
2406 qcom,vddmin-modes = "normal";
2407 qcom,vddmin-drive-strength = <8>;
2408 qcom,sfr-query;
2409 qcom,sysmon-id = <20>;
2410 qcom,ssctl-instance-id = <0x10>;
2411 qcom,support-shutdown;
2412 qcom,pil-force-shutdown;
2413 qcom,esoc-skip-restart-for-mdm-crash;
2414 pinctrl-names = "mdm_active", "mdm_suspend";
2415 pinctrl-0 = <&ap2mdm_active &mdm2ap_active>;
2416 pinctrl-1 = <&ap2mdm_sleep &mdm2ap_sleep>;
2417 interrupt-map = <0 &tlmm 1 0x3
2418 1 &tlmm 3 0x3>;
2419 qcom,mdm2ap-errfatal-gpio = <&tlmm 1 0x00>;
2420 qcom,ap2mdm-errfatal-gpio = <&tlmm 57 0x00>;
2421 qcom,mdm2ap-status-gpio = <&tlmm 3 0x00>;
2422 qcom,ap2mdm-status-gpio = <&tlmm 56 0x00>;
2423 qcom,mdm-link-info = "0306_02.01.00";
2424 status = "ok";
2425 };
2426
2427 pdc: interrupt-controller@b220000 {
2428 compatible = "qcom,kona-pdc";
2429 reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
2430 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>;
2431 #interrupt-cells = <2>;
2432 interrupt-parent = <&intc>;
2433 interrupt-controller;
2434 };
2435
2436 clocks {
2437 xo_board: xo-board {
2438 compatible = "fixed-clock";
2439 #clock-cells = <0>;
2440 clock-frequency = <38400000>;
2441 clock-output-names = "xo_board";
2442 };
2443
2444 sleep_clk: sleep-clk {
2445 compatible = "fixed-clock";
2446 clock-frequency = <32000>;
2447 clock-output-names = "chip_sleep_clk";
2448 #clock-cells = <1>;
2449 };
2450 };
2451
2452 clock_aop: qcom,aopclk {
2453 compatible = "qcom,aop-qmp-clk";
2454 #clock-cells = <1>;
2455 mboxes = <&qmp_aop 0>;
2456 mbox-names = "qdss_clk";
2457 qcom,clk-stop-bimc-log;
2458 };
2459
2460 clock_gcc: qcom,gcc@100000 {
2461 compatible = "qcom,gcc-kona", "syscon";
2462 reg = <0x100000 0x1f0000>;
2463 reg-names = "cc_base";
2464 vdd_cx-supply = <&VDD_CX_LEVEL>;
2465 vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
2466 vdd_mm-supply = <&VDD_MMCX_LEVEL>;
2467 #clock-cells = <1>;
2468 #reset-cells = <1>;
2469 };
2470
2471 clock_npucc: qcom,npucc@9980000 {
2472 compatible = "qcom,npucc-kona", "syscon";
2473 reg = <0x9980000 0x10000>,
2474 <0x9800000 0x10000>,
2475 <0x9810000 0x10000>;
2476 reg-names = "cc", "qdsp6ss", "qdsp6ss_pll";
2477 vdd_cx-supply = <&VDD_CX_LEVEL>;
2478 #clock-cells = <1>;
2479 #reset-cells = <1>;
2480 };
2481
2482 clock_videocc: qcom,videocc@abf0000 {
2483 compatible = "qcom,videocc-kona", "syscon";
2484 reg = <0xabf0000 0x10000>;
2485 reg-names = "cc_base";
2486 vdd_mx-supply = <&VDD_MX_LEVEL>;
2487 vdd_mm-supply = <&VDD_MMCX_LEVEL>;
2488 clock-names = "cfg_ahb_clk";
2489 clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
2490 #clock-cells = <1>;
2491 #reset-cells = <1>;
2492 };
2493
2494 clock_camcc: qcom,camcc@ad00000 {
2495 compatible = "qcom,camcc-kona", "syscon";
2496 reg = <0xad00000 0x10000>;
2497 reg-names = "cc_base";
2498 vdd_mx-supply = <&VDD_MX_LEVEL>;
2499 vdd_mm-supply = <&VDD_MMCX_LEVEL>;
2500 clock-names = "cfg_ahb_clk";
2501 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
2502 #clock-cells = <1>;
2503 #reset-cells = <1>;
2504 };
2505
2506 clock_dispcc: qcom,dispcc@af00000 {
2507 compatible = "qcom,kona-dispcc", "syscon";
2508 reg = <0xaf00000 0x20000>;
2509 reg-names = "cc_base";
2510 vdd_mm-supply = <&VDD_MMCX_LEVEL>;
2511 clock-names = "cfg_ahb_clk";
2512 clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
2513 #clock-cells = <1>;
2514 #reset-cells = <1>;
2515 };
2516
2517 clock_gpucc: qcom,gpucc@3d90000 {
2518 compatible = "qcom,gpucc-kona", "syscon";
2519 reg = <0x3d90000 0x9000>;
2520 reg-names = "cc_base";
2521 vdd_cx-supply = <&VDD_CX_LEVEL>;
2522 vdd_mx-supply = <&VDD_MX_LEVEL>;
2523 #clock-cells = <1>;
2524 #reset-cells = <1>;
2525 };
2526
2527 clock_cpucc: qcom,cpucc {
2528 compatible = "qcom,dummycc";
2529 clock-output-names = "cpucc_clocks";
2530 #clock-cells = <1>;
2531 };
2532
2533 clock_apsscc: syscon@182a0000 {
2534 compatible = "syscon";
2535 reg = <0x182a0000 0x1c>;
2536 };
2537
2538 clock_mccc: syscon@90ba000 {
2539 compatible = "syscon";
2540 reg = <0x90ba000 0x54>;
2541 };
2542
2543 clock_debugcc: qcom,cc-debug {
2544 compatible = "qcom,kona-debugcc";
2545 qcom,gcc = <&clock_gcc>;
2546 qcom,videocc = <&clock_videocc>;
2547 qcom,dispcc = <&clock_dispcc>;
2548 qcom,camcc = <&clock_camcc>;
2549 qcom,gpucc = <&clock_gpucc>;
2550 qcom,npucc = <&clock_npucc>;
2551 qcom,apsscc = <&clock_apsscc>;
2552 qcom,mccc = <&clock_mccc>;
2553 clock-names = "xo_clk_src";
2554 clocks = <&clock_rpmh RPMH_CXO_CLK>;
2555 #clock-cells = <1>;
2556 };
2557
2558 /* GCC GDSCs */
2559 pcie_0_gdsc: qcom,gdsc@16b004 {
2560 compatible = "qcom,gdsc";
2561 reg = <0x16b004 0x4>;
2562 regulator-name = "pcie_0_gdsc";
2563 qcom,retain-regs;
2564 };
2565
2566 pcie_1_gdsc: qcom,gdsc@18d004 {
2567 compatible = "qcom,gdsc";
2568 reg = <0x18d004 0x4>;
2569 regulator-name = "pcie_1_gdsc";
2570 qcom,retain-regs;
2571 };
2572
2573 pcie_2_gdsc: qcom,gdsc@106004 {
2574 compatible = "qcom,gdsc";
2575 reg = <0x106004 0x4>;
2576 regulator-name = "pcie_2_gdsc";
2577 qcom,retain-regs;
2578 };
2579
2580 ufs_phy_gdsc: qcom,gdsc@177004 {
2581 compatible = "qcom,gdsc";
2582 reg = <0x177004 0x4>;
2583 regulator-name = "ufs_phy_gdsc";
2584 qcom,retain-regs;
2585 };
2586
2587 usb30_prim_gdsc: qcom,gdsc@10f004 {
2588 compatible = "qcom,gdsc";
2589 reg = <0x10f004 0x4>;
2590 regulator-name = "usb30_prim_gdsc";
2591 qcom,retain-regs;
2592 };
2593
2594 usb30_sec_gdsc: qcom,gdsc@110004 {
2595 compatible = "qcom,gdsc";
2596 reg = <0x110004 0x4>;
2597 regulator-name = "usb30_sec_gdsc";
2598 qcom,retain-regs;
2599 };
2600
2601 hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
2602 compatible = "qcom,gdsc";
2603 reg = <0x17d050 0x4>;
2604 regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
2605 qcom,no-status-check-on-disable;
2606 qcom,gds-timeout = <500>;
2607 };
2608
2609 hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
2610 compatible = "qcom,gdsc";
2611 reg = <0x17d058 0x4>;
2612 regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
2613 qcom,no-status-check-on-disable;
2614 qcom,gds-timeout = <500>;
2615 };
2616
2617 hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
2618 compatible = "qcom,gdsc";
2619 reg = <0x17d054 0x4>;
2620 regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
2621 qcom,no-status-check-on-disable;
2622 qcom,gds-timeout = <500>;
2623 };
2624
2625 hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c {
2626 compatible = "qcom,gdsc";
2627 reg = <0x17d06c 0x4>;
2628 regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc";
2629 qcom,no-status-check-on-disable;
2630 qcom,gds-timeout = <500>;
2631 };
2632
2633 /* CAM_CC GDSCs */
2634 bps_gdsc: qcom,gdsc@ad07004 {
2635 compatible = "qcom,gdsc";
2636 reg = <0xad07004 0x4>;
2637 regulator-name = "bps_gdsc";
2638 clock-names = "ahb_clk";
2639 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
2640 parent-supply = <&VDD_MMCX_LEVEL>;
2641 vdd_parent-supply = <&VDD_MMCX_LEVEL>;
2642 qcom,msm-bus,name = "bps_gdsc_ahb";
2643 qcom,msm-bus,num-cases = <2>;
2644 qcom,msm-bus,num-paths = <1>;
2645 qcom,msm-bus,vectors-KBps =
2646 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
2647 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 1>;
2648 qcom,support-hw-trigger;
2649 qcom,retain-regs;
2650 };
2651
2652 ife_0_gdsc: qcom,gdsc@ad0a004 {
2653 compatible = "qcom,gdsc";
2654 reg = <0xad0a004 0x4>;
2655 regulator-name = "ife_0_gdsc";
2656 clock-names = "ahb_clk";
2657 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
2658 parent-supply = <&VDD_MMCX_LEVEL>;
2659 vdd_parent-supply = <&VDD_MMCX_LEVEL>;
2660 qcom,msm-bus,name = "ife_0_gdsc_ahb";
2661 qcom,msm-bus,num-cases = <2>;
2662 qcom,msm-bus,num-paths = <1>;
2663 qcom,msm-bus,vectors-KBps =
2664 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
2665 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 1>;
2666 qcom,retain-regs;
2667 };
2668
2669 ife_1_gdsc: qcom,gdsc@ad0b004 {
2670 compatible = "qcom,gdsc";
2671 reg = <0xad0b004 0x4>;
2672 regulator-name = "ife_1_gdsc";
2673 clock-names = "ahb_clk";
2674 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
2675 parent-supply = <&VDD_MMCX_LEVEL>;
2676 vdd_parent-supply = <&VDD_MMCX_LEVEL>;
2677 qcom,msm-bus,name = "ife_1_gdsc_ahb";
2678 qcom,msm-bus,num-cases = <2>;
2679 qcom,msm-bus,num-paths = <1>;
2680 qcom,msm-bus,vectors-KBps =
2681 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
2682 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 1>;
2683 qcom,retain-regs;
2684 };
2685
2686 ipe_0_gdsc: qcom,gdsc@ad08004 {
2687 compatible = "qcom,gdsc";
2688 reg = <0xad08004 0x4>;
2689 regulator-name = "ipe_0_gdsc";
2690 clock-names = "ahb_clk";
2691 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
2692 parent-supply = <&VDD_MMCX_LEVEL>;
2693 vdd_parent-supply = <&VDD_MMCX_LEVEL>;
2694 qcom,msm-bus,name = "ipe_0_gdsc_ahb";
2695 qcom,msm-bus,num-cases = <2>;
2696 qcom,msm-bus,num-paths = <1>;
2697 qcom,msm-bus,vectors-KBps =
2698 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
2699 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 1>;
2700 qcom,support-hw-trigger;
2701 qcom,retain-regs;
2702 };
2703
2704 sbi_gdsc: qcom,gdsc@ad09004 {
2705 compatible = "qcom,gdsc";
2706 reg = <0xad09004 0x4>;
2707 regulator-name = "sbi_gdsc";
2708 clock-names = "ahb_clk";
2709 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
2710 parent-supply = <&VDD_MMCX_LEVEL>;
2711 vdd_parent-supply = <&VDD_MMCX_LEVEL>;
2712 qcom,msm-bus,name = "sbi_gdsc_ahb";
2713 qcom,msm-bus,num-cases = <2>;
2714 qcom,msm-bus,num-paths = <1>;
2715 qcom,msm-bus,vectors-KBps =
2716 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
2717 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 1>;
2718 qcom,retain-regs;
2719 };
2720
2721 titan_top_gdsc: qcom,gdsc@ad0c144 {
2722 compatible = "qcom,gdsc";
2723 reg = <0xad0c144 0x4>;
2724 regulator-name = "titan_top_gdsc";
2725 clock-names = "ahb_clk";
2726 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
2727 parent-supply = <&VDD_MMCX_LEVEL>;
2728 vdd_parent-supply = <&VDD_MMCX_LEVEL>;
2729 qcom,msm-bus,name = "titan_top_gdsc_ahb";
2730 qcom,msm-bus,num-cases = <2>;
2731 qcom,msm-bus,num-paths = <1>;
2732 qcom,msm-bus,vectors-KBps =
2733 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
2734 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 1>;
2735 qcom,retain-regs;
2736 qcom,gds-timeout = <500>;
2737 };
2738
2739 /* DISP_CC GDSC */
2740 mdss_core_gdsc: qcom,gdsc@af03000 {
2741 compatible = "qcom,gdsc";
2742 reg = <0xaf03000 0x4>;
2743 regulator-name = "mdss_core_gdsc";
2744 clock-names = "ahb_clk";
2745 clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
2746 parent-supply = <&VDD_MMCX_LEVEL>;
2747 vdd_parent-supply = <&VDD_MMCX_LEVEL>;
2748 qcom,msm-bus,name = "mdss_core_gdsc_ahb";
2749 qcom,msm-bus,num-cases = <2>;
2750 qcom,msm-bus,num-paths = <1>;
2751 qcom,msm-bus,vectors-KBps =
2752 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_DISPLAY_CFG 0 0>,
2753 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_DISPLAY_CFG 0 1>;
2754 qcom,support-hw-trigger;
2755 qcom,retain-regs;
2756 proxy-supply = <&mdss_core_gdsc>;
2757 qcom,proxy-consumer-enable;
2758 };
2759
2760 /* GPU_CC GDSCs */
2761 gpu_cx_hw_ctrl: syscon@3d91540 {
2762 compatible = "syscon";
2763 reg = <0x3d91540 0x4>;
2764 };
2765
2766 gpu_cx_gdsc: qcom,gdsc@3d9106c {
2767 compatible = "qcom,gdsc";
2768 reg = <0x3d9106c 0x4>;
2769 regulator-name = "gpu_cx_gdsc";
2770 hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
2771 parent-supply = <&VDD_CX_LEVEL>;
2772 vdd_parent-supply = <&VDD_CX_LEVEL>;
2773 qcom,no-status-check-on-disable;
2774 qcom,clk-dis-wait-val = <8>;
2775 qcom,gds-timeout = <500>;
2776 qcom,retain-regs;
2777 };
2778
2779 gpu_gx_domain_addr: syscon@3d91508 {
2780 compatible = "syscon";
2781 reg = <0x3d91508 0x4>;
2782 };
2783
2784 gpu_gx_sw_reset: syscon@3d91008 {
2785 compatible = "syscon";
2786 reg = <0x3d91008 0x4>;
2787 };
2788
2789 gpu_gx_gdsc: qcom,gdsc@3d9100c {
2790 compatible = "qcom,gdsc";
2791 reg = <0x3d9100c 0x4>;
2792 regulator-name = "gpu_gx_gdsc";
2793 domain-addr = <&gpu_gx_domain_addr>;
2794 sw-reset = <&gpu_gx_sw_reset>;
2795 parent-supply = <&VDD_GFX_LEVEL>;
2796 vdd_parent-supply = <&VDD_GFX_LEVEL>;
2797 qcom,skip-disable-before-sw-enable;
2798 qcom,reset-aon-logic;
2799 qcom,retain-regs;
2800 };
2801
2802 /* NPU GDSC */
2803 npu_core_gdsc: qcom,gdsc@9981004 {
2804 compatible = "qcom,gdsc";
2805 reg = <0x9981004 0x4>;
2806 regulator-name = "npu_core_gdsc";
2807 clock-names = "ahb_clk";
2808 clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>;
2809 qcom,retain-regs;
2810 };
2811
2812 qcom,sps {
2813 compatible = "qcom,msm-sps-4k";
2814 qcom,pipe-attr-ee;
2815 };
2816
2817 /* VIDEO_CC GDSCs */
2818 mvs0_gdsc: qcom,gdsc@abf0d18 {
2819 compatible = "qcom,gdsc";
2820 reg = <0xabf0d18 0x4>;
2821 regulator-name = "mvs0_gdsc";
2822 clock-names = "ahb_clk";
2823 clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
2824 parent-supply = <&VDD_MMCX_LEVEL>;
2825 vdd_parent-supply = <&VDD_MMCX_LEVEL>;
2826 qcom,msm-bus,name = "mvs0_gdsc_ahb";
2827 qcom,msm-bus,num-cases = <2>;
2828 qcom,msm-bus,num-paths = <1>;
2829 qcom,msm-bus,vectors-KBps =
2830 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 0>,
2831 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 1>;
2832 qcom,support-hw-trigger;
2833 qcom,retain-regs;
2834 };
2835
2836 mvs0c_gdsc: qcom,gdsc@abf0bf8 {
2837 compatible = "qcom,gdsc";
2838 reg = <0xabf0bf8 0x4>;
2839 regulator-name = "mvs0c_gdsc";
2840 clock-names = "ahb_clk";
2841 clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
2842 parent-supply = <&VDD_MMCX_LEVEL>;
2843 vdd_parent-supply = <&VDD_MMCX_LEVEL>;
2844 qcom,msm-bus,name = "mvs0c_gdsc_ahb";
2845 qcom,msm-bus,num-cases = <2>;
2846 qcom,msm-bus,num-paths = <1>;
2847 qcom,msm-bus,vectors-KBps =
2848 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 0>,
2849 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 1>;
2850 qcom,retain-regs;
2851 };
2852
2853 mvs1_gdsc: qcom,gdsc@abf0d98 {
2854 compatible = "qcom,gdsc";
2855 reg = <0xabf0d98 0x4>;
2856 regulator-name = "mvs1_gdsc";
2857 clock-names = "ahb_clk";
2858 clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
2859 parent-supply = <&VDD_MMCX_LEVEL>;
2860 vdd_parent-supply = <&VDD_MMCX_LEVEL>;
2861 qcom,msm-bus,name = "mvs1_gdsc_ahb";
2862 qcom,msm-bus,num-cases = <2>;
2863 qcom,msm-bus,num-paths = <1>;
2864 qcom,msm-bus,vectors-KBps =
2865 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 0>,
2866 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 1>;
2867 qcom,support-hw-trigger;
2868 qcom,retain-regs;
2869 };
2870
2871 mvs1c_gdsc: qcom,gdsc@abf0c98 {
2872 compatible = "qcom,gdsc";
2873 reg = <0xabf0c98 0x4>;
2874 regulator-name = "mvs1c_gdsc";
2875 clock-names = "ahb_clk";
2876 clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
2877 parent-supply = <&VDD_MMCX_LEVEL>;
2878 vdd_parent-supply = <&VDD_MMCX_LEVEL>;
2879 qcom,msm-bus,name = "mvs1c_gdsc_ahb";
2880 qcom,msm-bus,num-cases = <2>;
2881 qcom,msm-bus,num-paths = <1>;
2882 qcom,msm-bus,vectors-KBps =
2883 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 0>,
2884 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 1>;
2885 qcom,retain-regs;
2886 };
2887
2888 spmi_bus: qcom,spmi@c440000 {
2889 compatible = "qcom,spmi-pmic-arb";
2890 reg = <0xc440000 0x1100>,
2891 <0xc600000 0x2000000>,
2892 <0xe600000 0x100000>,
2893 <0xe700000 0xa0000>,
2894 <0xc40a000 0x26000>;
2895 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2896 interrupt-names = "periph_irq";
2897 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
2898 qcom,ee = <0>;
2899 qcom,channel = <0>;
2900 #address-cells = <2>;
2901 #size-cells = <0>;
2902 interrupt-controller;
2903 #interrupt-cells = <4>;
2904 cell-index = <0>;
2905 };
2906
2907 spmi_debug_bus: qcom,spmi-debug@6b0f000 {
2908 compatible = "qcom,spmi-pmic-arb-debug";
2909 reg = <0x6b0f000 0x60>, <0x7820a8 0x4>;
2910 reg-names = "core", "fuse";
2911 clocks = <&clock_aop QDSS_CLK>;
2912 clock-names = "core_clk";
2913 qcom,fuse-disable-bit = <24>;
2914 #address-cells = <2>;
2915 #size-cells = <0>;
2916 status = "disabled";
2917
2918 qcom,pm8150-debug@0 {
2919 compatible = "qcom,spmi-pmic";
2920 reg = <0x0 SPMI_USID>;
2921 #address-cells = <2>;
2922 #size-cells = <0>;
2923 qcom,can-sleep;
2924 };
2925
2926 qcom,pm8150-debug@1 {
2927 compatible = "qcom,spmi-pmic";
2928 reg = <0x1 SPMI_USID>;
2929 #address-cells = <2>;
2930 #size-cells = <0>;
2931 qcom,can-sleep;
2932 };
2933
2934 qcom,pm8150b-debug@2 {
2935 compatible = "qcom,spmi-pmic";
2936 reg = <0x2 SPMI_USID>;
2937 #address-cells = <2>;
2938 #size-cells = <0>;
2939 qcom,can-sleep;
2940 };
2941
2942 qcom,pm8150b-debug@3 {
2943 compatible = "qcom,spmi-pmic";
2944 reg = <0x3 SPMI_USID>;
2945 #address-cells = <2>;
2946 #size-cells = <0>;
2947 qcom,can-sleep;
2948 };
2949
2950 qcom,pm8150l-debug@4 {
2951 compatible = "qcom,spmi-pmic";
2952 reg = <0x4 SPMI_USID>;
2953 #address-cells = <2>;
2954 #size-cells = <0>;
2955 qcom,can-sleep;
2956 };
2957
2958 qcom,pm8150l-debug@5 {
2959 compatible = "qcom,spmi-pmic";
2960 reg = <0x5 SPMI_USID>;
2961 #address-cells = <2>;
2962 #size-cells = <0>;
2963 qcom,can-sleep;
2964 };
2965
2966 qcom,pmk8002-debug@6 {
2967 compatible = "qcom,spmi-pmic";
2968 reg = <0x6 SPMI_USID>;
2969 #address-cells = <2>;
2970 #size-cells = <0>;
2971 qcom,can-sleep;
2972 };
2973
2974 qcom,pmk8002-debug@7 {
2975 compatible = "qcom,spmi-pmic";
2976 reg = <0x7 SPMI_USID>;
2977 #address-cells = <2>;
2978 #size-cells = <0>;
2979 qcom,can-sleep;
2980 };
2981
2982 qcom,pmxprairie-debug@8 {
2983 compatible = "qcom,spmi-pmic";
2984 reg = <0x8 SPMI_USID>;
2985 #address-cells = <2>;
2986 #size-cells = <0>;
2987 qcom,can-sleep;
2988 };
2989
2990 qcom,pmxprairie-debug@9 {
2991 compatible ="qcom,spmi-pmic";
2992 reg = <0x9 SPMI_USID>;
2993 #address-cells = <2>;
2994 #size-cells = <0>;
2995 qcom,can-sleep;
2996 };
2997
2998 qcom,pm8009-debug@a {
2999 compatible = "qcom,spmi-pmic";
3000 reg = <0xa SPMI_USID>;
3001 #address-cells = <2>;
3002 #size-cells = <0>;
3003 qcom,can-sleep;
3004 };
3005
3006 qcom,pm8009-debug@b {
3007 compatible = "qcom,spmi-pmic";
3008 reg = <0xb SPMI_USID>;
3009 #address-cells = <2>;
3010 #size-cells = <0>;
3011 qcom,can-sleep;
3012 };
3013 };
3014
3015 ufsphy_mem: ufsphy_mem@1d87000 {
3016 reg = <0x1d87000 0xe00>, <0x1d90000 0x8000>; /* PHY regs */
3017 reg-names = "phy_mem", "ufs_ice";
3018 #phy-cells = <0>;
3019
3020 lanes-per-direction = <2>;
3021
3022 clock-names = "ref_clk_src",
3023 "ref_aux_clk";
3024 clocks = <&clock_rpmh RPMH_CXO_CLK>,
3025 <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;
3026
3027 status = "disabled";
3028 };
3029
3030 ufshc_mem: ufshc@1d84000 {
3031 compatible = "qcom,ufshc";
3032 reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;
3033 reg-names = "ufs_mem", "ufs_ice";
3034 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
3035 phys = <&ufsphy_mem>;
3036 phy-names = "ufsphy";
3037
3038 lanes-per-direction = <2>;
3039 dev-ref-clk-freq = <0>; /* 19.2 MHz */
3040
3041 clock-names =
3042 "core_clk",
3043 "bus_aggr_clk",
3044 "iface_clk",
3045 "core_clk_unipro",
3046 "core_clk_ice",
3047 "ref_clk",
3048 "tx_lane0_sync_clk",
3049 "rx_lane0_sync_clk",
3050 "rx_lane1_sync_clk";
3051 clocks =
3052 <&clock_gcc GCC_UFS_PHY_AXI_CLK>,
3053 <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
3054 <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
3055 <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
3056 <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,
3057 <&clock_rpmh RPMH_CXO_CLK>,
3058 <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
3059 <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
3060 <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
3061 freq-table-hz =
3062 <37500000 300000000>,
3063 <0 0>,
3064 <0 0>,
3065 <37500000 300000000>,
3066 <37500000 300000000>,
3067 <0 0>,
3068 <0 0>,
3069 <0 0>,
3070 <0 0>;
3071
3072 qcom,msm-bus,name = "ufshc_mem";
3073 qcom,msm-bus,num-cases = <26>;
3074 qcom,msm-bus,num-paths = <2>;
3075 qcom,msm-bus,vectors-KBps =
3076 /*
3077 * During HS G3 UFS runs at nominal voltage corner, vote
3078 * higher bandwidth to push other buses in the data path
3079 * to run at nominal to achieve max throughput.
3080 * 4GBps pushes BIMC to run at nominal.
3081 * 200MBps pushes CNOC to run at nominal.
3082 * Vote for half of this bandwidth for HS G3 1-lane.
3083 * For max bandwidth, vote high enough to push the buses
3084 * to run in turbo voltage corner.
3085 */
3086 <123 512 0 0>, <1 757 0 0>, /* No vote */
3087 <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
3088 <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
3089 <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
3090 <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
3091 <123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */
3092 <123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */
3093 <123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */
3094 <123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */
3095 <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
3096 <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
3097 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
3098 <123 512 4194304 0>, <1 757 204800 0>, /* HS G4 RA */
3099 <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */
3100 <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */
3101 <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */
3102 <123 512 8388608 0>, <1 757 409600 0>, /* HS G4 RA L2 */
3103 <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
3104 <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
3105 <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
3106 <123 512 4194304 0>, <1 757 204800 0>, /* HS G4 RB */
3107 <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */
3108 <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */
3109 /* As UFS working in HS G3 RB L2 mode, aggregated
3110 * bandwidth (AB) should take care of providing
3111 * optimum throughput requested. However, as tested,
3112 * in order to scale up CNOC clock, instantaneous
3113 * bindwidth (IB) needs to be given a proper value too.
3114 */
3115 <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */
3116 <123 512 8388608 0>, <1 757 409600 409600>, /* HS G4 RB L2 */
3117 <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
3118
3119 qcom,bus-vector-names = "MIN",
3120 "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
3121 "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
3122 "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
3123 "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
3124 "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
3125 "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
3126
3127 "MAX";
3128
3129 /* PM QoS */
3130 qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
3131 qcom,pm-qos-cpu-group-latency-us = <44 44>;
3132 qcom,pm-qos-default-cpu = <0>;
3133
3134 pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
3135 pinctrl-0 = <&ufs_dev_reset_assert>;
3136 pinctrl-1 = <&ufs_dev_reset_deassert>;
3137
3138 resets = <&clock_gcc GCC_UFS_PHY_BCR>;
3139 reset-names = "core_reset";
3140
3141 status = "disabled";
3142 };
3143
3144 sdhc_2: sdhci@8804000 {
3145 compatible = "qcom,sdhci-msm-v5";
3146 reg = <0x8804000 0x1000>;
3147 reg-names = "hc_mem";
3148
3149 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
3150 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
3151 interrupt-names = "hc_irq", "pwr_irq";
3152
3153 qcom,bus-width = <4>;
3154 qcom,large-address-bus;
3155
3156 qcom,msm-bus,name = "sdhc2";
3157 qcom,msm-bus,num-cases = <8>;
3158 qcom,msm-bus,num-paths = <2>;
3159 qcom,msm-bus,vectors-KBps =
3160 /* No vote */
3161 <81 512 0 0>, <1 608 0 0>,
3162 /* 400 KB/s*/
3163 <81 512 1046 1600>,
3164 <1 608 1600 1600>,
3165 /* 20 MB/s */
3166 <81 512 52286 80000>,
3167 <1 608 80000 80000>,
3168 /* 25 MB/s */
3169 <81 512 65360 100000>,
3170 <1 608 100000 100000>,
3171 /* 50 MB/s */
3172 <81 512 130718 200000>,
3173 <1 608 133320 133320>,
3174 /* 100 MB/s */
3175 <81 512 261438 200000>,
3176 <1 608 150000 150000>,
3177 /* 200 MB/s */
3178 <81 512 261438 400000>,
3179 <1 608 300000 300000>,
3180 /* Max. bandwidth */
3181 <81 512 1338562 4096000>,
3182 <1 608 1338562 4096000>;
3183 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
3184 100750000 200000000 4294967295>;
3185
3186 qcom,restore-after-cx-collapse;
3187
3188 qcom,clk-rates = <400000 20000000 25000000
3189 50000000 100000000 201500000>;
3190 qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
3191 "SDR104";
3192
3193 qcom,devfreq,freq-table = <50000000 201500000>;
3194 clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
3195 <&clock_gcc GCC_SDCC2_APPS_CLK>;
3196 clock-names = "iface_clk", "core_clk";
3197
3198 /* PM QoS */
3199 qcom,pm-qos-irq-type = "affine_irq";
3200 qcom,pm-qos-irq-latency = <44 44>;
3201 qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
3202 qcom,pm-qos-legacy-latency-us = <44 44>, <44 44>;
3203
3204 /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
3205 qcom,dll-hsr-list = <0x0007642C 0xA800 0x10
3206 0x2C010800 0x80040868>;
3207
3208 status = "disabled";
3209 };
3210
3211 ipcc_mproc: qcom,ipcc@408000 {
3212 compatible = "qcom,ipcc";
3213 reg = <0x408000 0x1000>;
3214 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
3215 interrupt-controller;
3216 #interrupt-cells = <3>;
3217 #mbox-cells = <2>;
3218 };
3219
3220 apps_rsc: rsc@18200000 {
3221 label = "apps_rsc";
3222 compatible = "qcom,rpmh-rsc";
3223 reg = <0x18200000 0x10000>,
3224 <0x18210000 0x10000>,
3225 <0x18220000 0x10000>;
3226 reg-names = "drv-0", "drv-1", "drv-2";
3227 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3228 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3229 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3230 qcom,tcs-offset = <0xd00>;
3231 qcom,drv-id = <2>;
3232 qcom,tcs-config = <ACTIVE_TCS 2>,
3233 <SLEEP_TCS 3>,
3234 <WAKE_TCS 3>,
3235 <CONTROL_TCS 1>;
3236
3237 msm_bus_apps_rsc {
3238 compatible = "qcom,msm-bus-rsc";
3239 qcom,msm-bus-id = <MSM_BUS_RSC_APPS>;
3240 };
3241
3242 system_pm {
3243 compatible = "qcom,system-pm";
3244 };
3245
3246 clock_rpmh: qcom,rpmhclk {
3247 compatible = "qcom,kona-rpmh-clk";
3248 #clock-cells = <1>;
3249 };
3250 };
3251
3252 disp_rsc: rsc@af20000 {
3253 label = "disp_rsc";
3254 compatible = "qcom,rpmh-rsc";
3255 reg = <0xaf20000 0x10000>;
3256 reg-names = "drv-0";
3257 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
3258 qcom,tcs-offset = <0x1c00>;
3259 qcom,drv-id = <0>;
3260 qcom,tcs-config = <ACTIVE_TCS 0>,
3261 <SLEEP_TCS 1>,
3262 <WAKE_TCS 1>,
3263 <CONTROL_TCS 0>;
3264
3265 msm_bus_disp_rsc {
3266 compatible = "qcom,msm-bus-rsc";
3267 qcom,msm-bus-id = <MSM_BUS_RSC_DISP>;
3268 };
3269
3270 sde_rsc_rpmh {
3271 compatible = "qcom,sde-rsc-rpmh";
3272 cell-index = <0>;
3273 };
3274 };
3275
3276 tcsr_mutex_block: syscon@1f40000 {
3277 compatible = "syscon";
3278 reg = <0x1f40000 0x20000>;
3279 };
3280
3281 tcsr_mutex: hwlock {
3282 compatible = "qcom,tcsr-mutex";
3283 syscon = <&tcsr_mutex_block 0 0x1000>;
3284 #hwlock-cells = <1>;
3285 };
3286
3287 smem: qcom,smem {
3288 compatible = "qcom,smem";
3289 memory-region = <&smem_mem>;
3290 hwlocks = <&tcsr_mutex 3>;
3291 };
3292
3293 kryo-erp {
3294 compatible = "arm,arm64-kryo-cpu-erp";
3295 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
3296 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
3297 interrupt-names = "l1-l2-faultirq",
3298 "l3-scu-faultirq";
3299 };
3300
3301 sp_scsr: mailbox@188501c {
3302 compatible = "qcom,kona-spcs-global";
3303 reg = <0x188501c 0x4>;
3304
3305 #mbox-cells = <1>;
3306 };
3307
3308 sp_scsr_block: syscon@1880000 {
3309 compatible = "syscon";
3310 reg = <0x1880000 0x10000>;
3311 };
3312
3313 intsp: qcom,qsee_irq {
3314 compatible = "qcom,kona-qsee-irq";
3315
3316 syscon = <&sp_scsr_block>;
3317 interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>,
3318 <0 349 IRQ_TYPE_LEVEL_HIGH>;
3319
3320 interrupt-names = "sp_ipc0",
3321 "sp_ipc1";
3322
3323 interrupt-controller;
3324 #interrupt-cells = <3>;
3325 };
3326
3327 qcom,qsee_irq_bridge {
3328 compatible = "qcom,qsee-ipc-irq-bridge";
3329
3330 qcom,qsee-ipc-irq-spss {
3331 qcom,dev-name = "qsee_ipc_irq_spss";
3332 label = "spss";
3333 interrupt-parent = <&intsp>;
3334 interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>;
3335 };
3336 };
3337
3338 spss_utils: qcom,spss_utils {
3339 compatible = "qcom,spss-utils";
3340 /* spss fuses physical address */
3341 qcom,spss-fuse1-addr = <0x00780234>;
3342 qcom,spss-fuse1-bit = <27>;
3343 qcom,spss-fuse2-addr = <0x00780234>;
3344 qcom,spss-fuse2-bit = <26>;
3345 qcom,spss-fuse3-addr = <0x007801E8>; // IAR_FEATURE_ENABLED fuse
3346 qcom,spss-fuse3-bit = <10>;
3347 qcom,spss-fuse4-addr = <0x00780218>; // IAR_STATE fuse
3348 qcom,spss-fuse4-bit = <1>; // 0x00780214 bits 33-35
3349 qcom,spss-dev-firmware-name = "spss1d"; /* 8 chars max */
3350 qcom,spss-test-firmware-name = "spss1t"; /* 8 chars max */
3351 qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */
3352 qcom,spss-debug-reg-addr = <0x01886020>;
3353 qcom,spss-emul-type-reg-addr = <0x01fc8004>;
3354 pil-mem = <&pil_spss_mem>;
3355 qcom,pil-addr = <0x8BE00000>; // backward compatible
3356 qcom,pil-size = <0x0F0000>; // padding to 960 KB
3357 status = "ok";
3358 };
3359
3360 qcom,spcom {
3361 compatible = "qcom,spcom";
3362
3363 /* predefined channels, remote side is server */
3364 qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
3365 /* rmb_err shared register physical address */
3366 qcom,spcom-rmb-err-reg-addr = <0x188103c>;
3367 /* sp2soc rmb shared register physical address and bmsk */
3368 qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
3369 qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
3370 qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;
3371 /* soc2sp rmb shared register physical address */
3372 qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
3373 qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
3374 status = "ok";
3375 };
3376
3377 qcom,msm_gsi {
3378 compatible = "qcom,msm_gsi";
3379 };
3380
3381 qcom,rmnet-ipa {
3382 compatible = "qcom,rmnet-ipa3";
3383 qcom,rmnet-ipa-ssr;
3384 qcom,ipa-advertise-sg-support;
3385 qcom,ipa-napi-enable;
3386 };
3387
3388 qcom,ipa_fws {
3389 compatible = "qcom,pil-tz-generic";
3390 qcom,pas-id = <0xf>;
3391 qcom,firmware-name = "ipa_fws";
3392 qcom,pil-force-shutdown;
3393 memory-region = <&pil_ipa_gsi_mem>;
3394 };
3395
3396 qcom,ipa_uc {
3397 compatible = "qcom,pil-tz-generic";
3398 qcom,pas-id = <0x1B>;
3399 qcom,firmware-name = "ipa_uc";
3400 qcom,pil-force-shutdown;
3401 memory-region = <&pil_ipa_fw_mem>;
3402 };
3403
3404 qcom,ipa-mpm {
3405 compatible = "qcom,ipa-mpm";
3406 qcom,mhi-chdb-base = <0x64300300>;
3407 qcom,mhi-erdb-base = <0x64300700>;
3408 qcom,iova-mapping = <0x10000000 0x0FFFFFFF>;
3409 };
3410
3411 ipa_hw: qcom,ipa@1e00000 {
3412 compatible = "qcom,ipa";
3413 mboxes = <&qmp_aop 0>;
3414 reg =
3415 <0x1e00000 0x84000>,
3416 <0x1e04000 0x23000>;
3417 reg-names = "ipa-base", "gsi-base";
3418 interrupts =
3419 <0 311 IRQ_TYPE_LEVEL_HIGH>,
3420 <0 432 IRQ_TYPE_LEVEL_HIGH>;
3421 interrupt-names = "ipa-irq", "gsi-irq";
3422 qcom,ipa-hw-ver = <17>; /* IPA core version = IPAv4.5 */
3423 qcom,ipa-hw-mode = <0>;
3424 qcom,platform-type = <2>; /* APQ platform */
3425 qcom,ee = <0>;
3426 qcom,use-ipa-tethering-bridge;
3427 qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */
3428 qcom,modem-cfg-emb-pipe-flt;
3429 qcom,ipa-wdi3-over-gsi;
3430 qcom,arm-smmu;
3431 qcom,smmu-fast-map;
3432 qcom,bandwidth-vote-for-ipa;
3433 qcom,use-64-bit-dma-mask;
3434 qcom,ipa-endp-delay-wa;
3435 qcom,msm-bus,name = "ipa";
3436 qcom,msm-bus,num-cases = <5>;
3437 qcom,msm-bus,num-paths = <5>;
3438 qcom,msm-bus,vectors-KBps =
3439 /* No vote */
3440 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 0 0>,
3441 <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 0 0>,
3442 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,
3443 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,
3444 <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 0>,
3445
3446 /* SVS2 */
3447 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 150000 600000>,
3448 <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 150000 1804000>,
3449 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 75000 300000>,
3450 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 76800>,
3451 <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 150>,
3452
3453 /* SVS */
3454 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 625000 1200000>,
3455 <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 625000 3072000>,
3456 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 312500 700000>,
3457 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 150000>,
3458 <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 240>,
3459
3460 /* NOMINAL */
3461 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 1250000 2400000>,
3462 <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 1250000 6220800>,
3463 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 625000 1500000>,
3464 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 400000>,
3465 <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 466>,
3466
3467 /* TURBO */
3468 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 2000000 3500000>,
3469 <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 2000000 7219200>,
3470 <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 1000000 1920000>,
3471 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 400000>,
3472 <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 533>;
3473
3474 qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
3475 "TURBO";
3476 qcom,throughput-threshold = <600 2500 5000>;
3477 qcom,scaling-exceptions = "wdi", "0", "600", "1200",
3478 "USB DPL", "0", "2500", "5000", "ODL", "0",
3479 "2500", "5000";
3480
3481 qcom,entire-ipa-block-size = <0x100000>;
3482 qcom,register-collection-on-crash;
3483 qcom,testbus-collection-on-crash;
3484 qcom,non-tn-collection-on-crash;
3485 qcom,ram-collection-on-crash;
3486 qcom,secure-debug-check-action = <0>;
3487
3488 ipa_smmu_ap: ipa_smmu_ap {
3489 compatible = "qcom,ipa-smmu-ap-cb";
3490 iommus = <&apps_smmu 0x5C0 0x0>;
3491 qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
3492 qcom,additional-mapping =
3493 /* modem tables in IMEM */
3494 <0x146BD000 0x146BD000 0x2000>;
3495 dma-coherent;
3496 qcom,iommu-dma = "fastmap";
3497 };
3498
3499 ipa_smmu_wlan: ipa_smmu_wlan {
3500 compatible = "qcom,ipa-smmu-wlan-cb";
3501 iommus = <&apps_smmu 0x5C1 0x0>;
3502 qcom,iommu-dma = "fastmap";
3503 dma-coherent;
3504 };
3505
3506 ipa_smmu_uc: ipa_smmu_uc {
3507 compatible = "qcom,ipa-smmu-uc-cb";
3508 iommus = <&apps_smmu 0x5C2 0x0>;
3509 qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
3510 qcom,iommu-dma = "fastmap";
3511 };
3512
3513 ipa_smmu_11ad: ipa_smmu_11ad {
3514 compatible = "qcom,ipa-smmu-11ad-cb";
3515 iommus = <&apps_smmu 0x5C3 0x0>;
3516 dma-coherent;
3517 qcom,shared-cb;
3518 qcom,iommu-group = <&wil6210_pci_iommu_group>;
3519 };
3520 };
3521
3522 qcom,glink {
3523 compatible = "qcom,glink";
3524 #address-cells = <1>;
3525 #size-cells = <1>;
3526 ranges;
3527
3528 glink_npu: npu {
3529 qcom,remote-pid = <10>;
3530 transport = "smem";
3531 mboxes = <&msm_npu IPCC_CLIENT_NPU
3532 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3533 mbox-names = "npu_smem";
3534 interrupt-parent = <&ipcc_mproc>;
3535 interrupts = <IPCC_CLIENT_NPU
3536 IPCC_MPROC_SIGNAL_GLINK_QMP
3537 IRQ_TYPE_EDGE_RISING>;
3538
3539 label = "npu";
3540 qcom,glink-label = "npu";
3541
3542 qcom,npu_qrtr {
3543 qcom,net-id = <1>;
3544 qcom,glink-channels = "IPCRTR";
3545 qcom,intents = <0x800 5
3546 0x2000 3
3547 0x4400 2>;
3548 };
3549
3550 qcom,npu_glink_ssr {
3551 qcom,glink-channels = "glink_ssr";
3552 qcom,notify-edges = <&glink_cdsp>;
3553 };
3554 };
3555
3556 glink_adsp: adsp {
3557 qcom,remote-pid = <2>;
3558 transport = "smem";
3559 mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
3560 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3561 mbox-names = "adsp_smem";
3562 interrupt-parent = <&ipcc_mproc>;
3563 interrupts = <IPCC_CLIENT_LPASS
3564 IPCC_MPROC_SIGNAL_GLINK_QMP
3565 IRQ_TYPE_EDGE_RISING>;
3566
3567 label = "adsp";
3568 qcom,glink-label = "lpass";
3569
3570 qcom,adsp_qrtr {
3571 qcom,net-id = <2>;
3572 qcom,glink-channels = "IPCRTR";
3573 qcom,intents = <0x800 5
3574 0x2000 3
3575 0x4400 2>;
3576 };
3577
3578 qcom,apr_tal_rpmsg {
3579 qcom,glink-channels = "apr_audio_svc";
3580 qcom,intents = <0x200 20>;
3581 };
3582
3583 qcom,msm_fastrpc_rpmsg {
3584 compatible = "qcom,msm-fastrpc-rpmsg";
3585 qcom,glink-channels = "fastrpcglink-apps-dsp";
3586 qcom,intents = <0x64 64>;
3587 };
3588
3589 qcom,adsp_glink_ssr {
3590 qcom,glink-channels = "glink_ssr";
3591 qcom,notify-edges = <&glink_slpi>,
3592 <&glink_cdsp>;
3593 };
3594 };
3595
3596 glink_slpi: dsps {
3597 qcom,remote-pid = <3>;
3598 transport = "smem";
3599 mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI
3600 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3601 mbox-names = "dsps_smem";
3602 interrupt-parent = <&ipcc_mproc>;
3603 interrupts = <IPCC_CLIENT_SLPI
3604 IPCC_MPROC_SIGNAL_GLINK_QMP
3605 IRQ_TYPE_EDGE_RISING>;
3606
3607 label = "slpi";
3608 qcom,glink-label = "dsps";
3609
3610 qcom,slpi_qrtr {
3611 qcom,net-id = <2>;
3612 qcom,glink-channels = "IPCRTR";
3613 qcom,low-latency;
3614 qcom,intents = <0x800 5
3615 0x2000 3
3616 0x4400 2>;
3617 };
3618
3619 qcom,msm_fastrpc_rpmsg {
3620 compatible = "qcom,msm-fastrpc-rpmsg";
3621 qcom,glink-channels = "fastrpcglink-apps-dsp";
3622 qcom,intents = <0x64 64>;
3623 };
3624
3625 qcom,slpi_glink_ssr {
3626 qcom,glink-channels = "glink_ssr";
3627 qcom,notify-edges = <&glink_adsp>,
3628 <&glink_cdsp>;
3629 };
3630 };
3631
3632 glink_cdsp: cdsp {
3633 qcom,remote-pid = <5>;
3634 transport = "smem";
3635 mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
3636 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3637 mbox-names = "dsps_smem";
3638 interrupt-parent = <&ipcc_mproc>;
3639 interrupts = <IPCC_CLIENT_CDSP
3640 IPCC_MPROC_SIGNAL_GLINK_QMP
3641 IRQ_TYPE_EDGE_RISING>;
3642
3643 label = "cdsp";
3644 qcom,glink-label = "cdsp";
3645
3646 qcom,cdsp_qrtr {
3647 qcom,net-id = <1>;
3648 qcom,glink-channels = "IPCRTR";
3649 qcom,intents = <0x800 5
3650 0x2000 3
3651 0x4400 2>;
3652 };
3653
3654 qcom,msm_fastrpc_rpmsg {
3655 compatible = "qcom,msm-fastrpc-rpmsg";
3656 qcom,glink-channels = "fastrpcglink-apps-dsp";
3657 qcom,intents = <0x64 64>;
3658 };
3659
3660 qcom,msm_cdsprm_rpmsg {
3661 compatible = "qcom,msm-cdsprm-rpmsg";
3662 qcom,glink-channels = "cdsprmglink-apps-dsp";
3663 qcom,intents = <0x20 12>;
3664
3665 qcom,cdsp-cdsp-l3-gov {
3666 compatible = "qcom,cdsp-l3";
3667 qcom,target-dev = <&cdsp_l3>;
3668 };
3669
3670 msm_cdsp_rm: qcom,msm_cdsp_rm {
3671 compatible = "qcom,msm-cdsp-rm";
3672 qcom,qos-latency-us = <44>;
3673 qcom,qos-maxhold-ms = <20>;
3674 qcom,compute-cx-limit-en;
3675 qcom,compute-priority-mode = <2>;
3676 #cooling-cells = <2>;
3677 };
3678
3679 msm_hvx_rm: qcom,msm_hvx_rm {
3680 compatible = "qcom,msm-hvx-rm";
3681 #cooling-cells = <2>;
3682 };
3683 };
3684
3685 qcom,cdsp_glink_ssr {
3686 qcom,glink-channels = "glink_ssr";
3687 qcom,notify-edges = <&glink_adsp>,
3688 <&glink_slpi>,
3689 <&glink_npu>;
3690 };
3691 };
3692
3693 glink_spss: spss {
3694 qcom,remote-pid = <8>;
3695 transport = "spss";
3696 mboxes = <&sp_scsr 0>;
3697 mbox-names = "spss_spss";
3698 interrupt-parent = <&intsp>;
3699 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
3700
3701 reg = <0x1885008 0x8>,
3702 <0x1885010 0x4>;
3703 reg-names = "qcom,spss-addr",
3704 "qcom,spss-size";
3705
3706 label = "spss";
3707 qcom,glink-label = "spss";
3708 };
3709 };
3710
3711 qmp_aop: qcom,qmp-aop@c300000 {
3712 compatible = "qcom,qmp-mbox";
3713 mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
3714 IPCC_MPROC_SIGNAL_GLINK_QMP>;
3715 mbox-names = "aop_qmp";
3716 interrupt-parent = <&ipcc_mproc>;
3717 interrupts = <IPCC_CLIENT_AOP
3718 IPCC_MPROC_SIGNAL_GLINK_QMP
3719 IRQ_TYPE_EDGE_RISING>;
3720 reg = <0xc300000 0x1000>;
3721 reg-names = "msgram";
3722
3723 label = "aop";
3724 qcom,early-boot;
3725 priority = <0>;
3726 mbox-desc-offset = <0x0>;
3727 #mbox-cells = <1>;
3728 };
3729
3730 aop-msg-client {
3731 compatible = "qcom,debugfs-qmp-client";
3732 mboxes = <&qmp_aop 0>;
3733 mbox-names = "aop";
3734 };
3735
3736 eud: qcom,msm-eud@ff0000 {
3737 compatible = "qcom,msm-eud";
3738 interrupt-names = "eud_irq";
3739 interrupt-parent = <&pdc>;
3740 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
3741 reg = <0x088E0000 0x2000>,
3742 <0x088E2000 0x1000>;
3743 reg-names = "eud_base", "eud_mode_mgr2";
3744 qcom,secure-eud-en;
3745 qcom,eud-clock-vote-req;
3746 clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_BCR>;
3747 clock-names = "eud_ahb2phy_clk";
3748 status = "ok";
3749 };
3750
3751 qcom,lpass@17300000 {
3752 compatible = "qcom,pil-tz-generic";
3753 reg = <0x17300000 0x00100>;
3754
3755 vdd_cx-supply = <&L11A_LEVEL>;
3756 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
3757 vdd_mx-supply = <&L4A_LEVEL>;
3758 qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
3759 qcom,proxy-reg-names = "vdd_cx","vdd_mx";
3760
3761 clocks = <&clock_rpmh RPMH_CXO_CLK>;
3762 clock-names = "xo";
3763 qcom,proxy-clock-names = "xo";
3764
3765 qcom,pas-id = <1>;
3766 qcom,proxy-timeout-ms = <10000>;
3767 qcom,smem-id = <423>;
3768 qcom,sysmon-id = <1>;
3769 qcom,ssctl-instance-id = <0x14>;
3770 qcom,firmware-name = "adsp";
3771 memory-region = <&pil_adsp_mem>;
3772 qcom,signal-aop;
3773 qcom,complete-ramdump;
3774
3775 /* Inputs from lpass */
3776 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
3777 <&adsp_smp2p_in 0 0>,
3778 <&adsp_smp2p_in 2 0>,
3779 <&adsp_smp2p_in 1 0>,
3780 <&adsp_smp2p_in 3 0>;
3781
3782 interrupt-names = "qcom,wdog",
3783 "qcom,err-fatal",
3784 "qcom,proxy-unvote",
3785 "qcom,err-ready",
3786 "qcom,stop-ack";
3787
3788 /* Outputs to lpass */
3789 qcom,smem-states = <&adsp_smp2p_out 0>;
3790 qcom,smem-state-names = "qcom,force-stop";
3791
3792 mboxes = <&qmp_aop 0>;
3793 mbox-names = "adsp-pil";
3794 };
3795
3796 qcom,turing@8300000 {
3797 compatible = "qcom,pil-tz-generic";
3798 reg = <0x8300000 0x100000>;
3799
3800 vdd_cx-supply = <&VDD_CX_LEVEL>;
3801 qcom,proxy-reg-names = "vdd_cx";
3802 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
3803
3804 clocks = <&clock_rpmh RPMH_CXO_CLK>;
3805 clock-names = "xo";
3806 qcom,proxy-clock-names = "xo";
3807
3808 qcom,pas-id = <18>;
3809 qcom,proxy-timeout-ms = <10000>;
3810 qcom,smem-id = <601>;
3811 qcom,sysmon-id = <7>;
3812 qcom,ssctl-instance-id = <0x17>;
3813 qcom,firmware-name = "cdsp";
3814 memory-region = <&pil_cdsp_mem>;
3815 qcom,signal-aop;
3816 qcom,complete-ramdump;
3817
3818 qcom,msm-bus,name = "pil-cdsp";
3819 qcom,msm-bus,num-cases = <2>;
3820 qcom,msm-bus,num-paths = <1>;
3821 qcom,msm-bus,vectors-KBps =
3822 <154 10070 0 0>,
3823 <154 10070 0 1>;
3824
3825 /* Inputs from turing */
3826 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
3827 <&cdsp_smp2p_in 0 0>,
3828 <&cdsp_smp2p_in 2 0>,
3829 <&cdsp_smp2p_in 1 0>,
3830 <&cdsp_smp2p_in 3 0>;
3831
3832 interrupt-names = "qcom,wdog",
3833 "qcom,err-fatal",
3834 "qcom,proxy-unvote",
3835 "qcom,err-ready",
3836 "qcom,stop-ack";
3837
3838 /* Outputs to turing */
3839 qcom,smem-states = <&cdsp_smp2p_out 0>;
3840 qcom,smem-state-names = "qcom,force-stop";
3841
3842 mboxes = <&qmp_aop 0>;
3843 mbox-names = "cdsp-pil";
3844 };
3845
3846 qcom,venus@aab0000 {
3847 compatible = "qcom,pil-tz-generic";
3848 reg = <0xaab0000 0x2000>;
3849
3850 vdd-supply = <&mvs0c_gdsc>;
3851 qcom,proxy-reg-names = "vdd";
3852 qcom,complete-ramdump;
3853
3854 clocks = <&clock_videocc VIDEO_CC_XO_CLK>,
3855 <&clock_videocc VIDEO_CC_MVS0C_CLK>,
3856 <&clock_videocc VIDEO_CC_AHB_CLK>;
3857 clock-names = "xo", "core", "ahb";
3858 qcom,proxy-clock-names = "xo", "core", "ahb";
3859
3860 qcom,core-freq = <200000000>;
3861 qcom,ahb-freq = <200000000>;
3862
3863 qcom,pas-id = <9>;
3864 qcom,msm-bus,name = "pil-venus";
3865 qcom,msm-bus,num-cases = <2>;
3866 qcom,msm-bus,num-paths = <1>;
3867 qcom,msm-bus,vectors-KBps =
3868 <63 512 0 0>,
3869 <63 512 0 304000>;
3870 qcom,proxy-timeout-ms = <100>;
3871 qcom,firmware-name = "venus";
3872 memory-region = <&pil_video_mem>;
3873 };
3874
3875 /* PIL spss node - for loading Secure Processor */
3876 qcom,spss@1880000 {
3877 compatible = "qcom,pil-tz-generic";
3878 reg = <0x188101c 0x4>,
3879 <0x1881024 0x4>,
3880 <0x1881028 0x4>,
3881 <0x188103c 0x4>,
3882 <0x1882014 0x4>;
3883 reg-names = "sp2soc_irq_status", "sp2soc_irq_clr",
3884 "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2";
3885 interrupts = <0 352 1>;
3886
3887 vdd_cx-supply = <&VDD_CX_LEVEL>;
3888 qcom,proxy-reg-names = "vdd_cx";
3889 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
3890 vdd_mx-supply = <&VDD_MX_LEVEL>;
3891 vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
3892
3893 clocks = <&clock_rpmh RPMH_CXO_CLK>;
3894 clock-names = "xo";
3895 qcom,proxy-clock-names = "xo";
3896 qcom,pil-generic-irq-handler;
3897 status = "ok";
3898
3899 qcom,signal-aop;
3900 qcom,complete-ramdump;
3901
3902 qcom,pas-id = <14>;
3903 qcom,proxy-timeout-ms = <10000>;
3904 qcom,firmware-name = "spss";
3905 memory-region = <&pil_spss_mem>;
3906 qcom,spss-scsr-bits = <24 25>;
3907 /* use extra size for IAR memory */
3908 qcom,extra-size = <4096>;
3909
3910 mboxes = <&qmp_aop 0>;
3911 mbox-names = "spss-pil";
3912 };
3913
3914 qcom,cvpss@abb0000 {
3915 compatible = "qcom,pil-tz-generic";
3916 reg = <0xabb0000 0x2000>;
3917 status = "ok";
3918 qcom,pas-id = <26>;
3919 qcom,firmware-name = "cvpss";
3920
3921 memory-region = <&pil_cvp_mem>;
3922 };
3923
3924 qcom,npu@9800000 {
3925 compatible = "qcom,pil-tz-generic";
3926 reg = <0x9800000 0x800000>;
3927
3928 status = "ok";
3929 qcom,pas-id = <23>;
3930 qcom,firmware-name = "npu";
3931 memory-region = <&pil_npu_mem>;
3932
3933 /* Outputs to npu */
3934 qcom,smem-states = <&npu_smp2p_out 0>;
3935 qcom,smem-state-names = "qcom,force-stop";
3936 };
3937
3938 qcom,smp2p_sleepstate {
3939 compatible = "qcom,smp2p-sleepstate";
3940 qcom,smem-states = <&sleepstate_smp2p_out 0>;
3941 interrupt-parent = <&sleepstate_smp2p_in>;
3942 interrupts = <0 0>;
3943 interrupt-names = "smp2p-sleepstate-in";
3944 };
3945
3946 qcom,msm-cdsp-loader {
3947 compatible = "qcom,cdsp-loader";
3948 qcom,proc-img-to-load = "cdsp";
3949 };
3950
3951 qcom,msm-adsprpc-mem {
3952 compatible = "qcom,msm-adsprpc-mem-region";
3953 memory-region = <&adsp_mem>;
3954 restrict-access;
3955 };
3956
3957 msm_fastrpc: qcom,msm_fastrpc {
3958 compatible = "qcom,msm-fastrpc-compute";
3959 qcom,adsp-remoteheap-vmid = <22 37>;
3960 qcom,fastrpc-adsp-audio-pdr;
3961 qcom,fastrpc-adsp-sensors-pdr;
3962 qcom,rpc-latency-us = <235>;
3963 qcom,qos-cores = <0 1 2 3>;
3964
3965 qcom,msm_fastrpc_compute_cb1 {
3966 compatible = "qcom,msm-fastrpc-compute-cb";
3967 label = "cdsprpc-smd";
3968 iommus = <&apps_smmu 0x1001 0x0460>;
3969 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
3970 qcom,iommu-faults = "stall-disable", "HUPCF";
3971 dma-coherent;
3972 };
3973
3974 qcom,msm_fastrpc_compute_cb2 {
3975 compatible = "qcom,msm-fastrpc-compute-cb";
3976 label = "cdsprpc-smd";
3977 iommus = <&apps_smmu 0x1002 0x0460>;
3978 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
3979 qcom,iommu-faults = "stall-disable", "HUPCF";
3980 dma-coherent;
3981 };
3982
3983 qcom,msm_fastrpc_compute_cb3 {
3984 compatible = "qcom,msm-fastrpc-compute-cb";
3985 label = "cdsprpc-smd";
3986 iommus = <&apps_smmu 0x1003 0x0460>;
3987 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
3988 qcom,iommu-faults = "stall-disable", "HUPCF";
3989 dma-coherent;
3990 };
3991
3992 qcom,msm_fastrpc_compute_cb4 {
3993 compatible = "qcom,msm-fastrpc-compute-cb";
3994 label = "cdsprpc-smd";
3995 iommus = <&apps_smmu 0x1004 0x0460>;
3996 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
3997 qcom,iommu-faults = "stall-disable", "HUPCF";
3998 dma-coherent;
3999 };
4000
4001 qcom,msm_fastrpc_compute_cb5 {
4002 compatible = "qcom,msm-fastrpc-compute-cb";
4003 label = "cdsprpc-smd";
4004 iommus = <&apps_smmu 0x1005 0x0460>;
4005 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
4006 qcom,iommu-faults = "stall-disable", "HUPCF";
4007 dma-coherent;
4008 };
4009
4010 qcom,msm_fastrpc_compute_cb6 {
4011 compatible = "qcom,msm-fastrpc-compute-cb";
4012 label = "cdsprpc-smd";
4013 iommus = <&apps_smmu 0x1006 0x0460>;
4014 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
4015 qcom,iommu-faults = "stall-disable", "HUPCF";
4016 dma-coherent;
4017 };
4018
4019 qcom,msm_fastrpc_compute_cb7 {
4020 compatible = "qcom,msm-fastrpc-compute-cb";
4021 label = "cdsprpc-smd";
4022 iommus = <&apps_smmu 0x1007 0x0460>;
4023 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
4024 qcom,iommu-faults = "stall-disable", "HUPCF";
4025 dma-coherent;
4026 };
4027
4028 qcom,msm_fastrpc_compute_cb8 {
4029 compatible = "qcom,msm-fastrpc-compute-cb";
4030 label = "cdsprpc-smd";
4031 iommus = <&apps_smmu 0x1008 0x0460>;
4032 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
4033 qcom,iommu-faults = "stall-disable", "HUPCF";
4034 dma-coherent;
4035 };
4036
4037 qcom,msm_fastrpc_compute_cb9 {
4038 compatible = "qcom,msm-fastrpc-compute-cb";
4039 label = "cdsprpc-smd";
4040 qcom,secure-context-bank;
4041 iommus = <&apps_smmu 0x1009 0x0460>;
4042 qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
4043 qcom,iommu-faults = "stall-disable", "HUPCF";
4044 qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
4045 dma-coherent;
4046 };
4047
4048 qcom,msm_fastrpc_compute_cb10 {
4049 compatible = "qcom,msm-fastrpc-compute-cb";
4050 label = "adsprpc-smd";
4051 iommus = <&apps_smmu 0x1803 0x0>;
4052 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
4053 qcom,iommu-faults = "stall-disable", "HUPCF";
4054 dma-coherent;
4055 };
4056
4057 qcom,msm_fastrpc_compute_cb11 {
4058 compatible = "qcom,msm-fastrpc-compute-cb";
4059 label = "adsprpc-smd";
4060 iommus = <&apps_smmu 0x1804 0x0>;
4061 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
4062 qcom,iommu-faults = "stall-disable", "HUPCF";
4063 dma-coherent;
4064 };
4065
4066 qcom,msm_fastrpc_compute_cb12 {
4067 compatible = "qcom,msm-fastrpc-compute-cb";
4068 label = "adsprpc-smd";
4069 iommus = <&apps_smmu 0x1805 0x0>;
4070 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
4071 qcom,iommu-faults = "stall-disable", "HUPCF";
4072 dma-coherent;
4073 };
4074
4075 qcom,msm_fastrpc_compute_cb13 {
4076 compatible = "qcom,msm-fastrpc-compute-cb";
4077 label = "sdsprpc-smd";
4078 iommus = <&apps_smmu 0x0541 0x0>;
4079 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
4080 qcom,iommu-faults = "stall-disable", "HUPCF";
4081 dma-coherent;
4082 };
4083
4084 qcom,msm_fastrpc_compute_cb14 {
4085 compatible = "qcom,msm-fastrpc-compute-cb";
4086 label = "sdsprpc-smd";
4087 iommus = <&apps_smmu 0x0542 0x0>;
4088 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
4089 qcom,iommu-faults = "stall-disable", "HUPCF";
4090 dma-coherent;
4091 };
4092
4093 qcom,msm_fastrpc_compute_cb15 {
4094 compatible = "qcom,msm-fastrpc-compute-cb";
4095 label = "sdsprpc-smd";
4096 iommus = <&apps_smmu 0x0543 0x0>;
4097 qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
4098 qcom,iommu-faults = "stall-disable", "HUPCF";
4099 shared-cb = <4>;
4100 dma-coherent;
4101 };
4102 };
4103
4104 qcom_cedev: qcedev@1de0000 {
4105 compatible = "qcom,qcedev";
4106 reg = <0x1de0000 0x20000>,
4107 <0x1dc4000 0x24000>;
4108 reg-names = "crypto-base","crypto-bam-base";
4109 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4110 qcom,bam-pipe-pair = <3>;
4111 qcom,ce-hw-instance = <0>;
4112 qcom,ce-device = <0>;
4113 qcom,ce-hw-shared;
4114 qcom,bam-ee = <0>;
4115 qcom,msm-bus,name = "qcedev-noc";
4116 qcom,msm-bus,num-cases = <2>;
4117 qcom,msm-bus,num-paths = <1>;
4118 qcom,msm-bus,vectors-KBps =
4119 <125 512 0 0>,
4120 <125 512 393600 393600>;
4121 qcom,smmu-s1-enable;
4122 qcom,no-clock-support;
4123 iommus = <&apps_smmu 0x0586 0x0011>,
4124 <&apps_smmu 0x0596 0x0011>;
4125 qcom,iommu-dma = "atomic";
4126
4127 qcom_cedev_ns_cb {
4128 compatible = "qcom,qcedev,context-bank";
4129 label = "ns_context";
4130 iommus = <&apps_smmu 0x592 0>,
4131 <&apps_smmu 0x598 0>,
4132 <&apps_smmu 0x599 0>,
4133 <&apps_smmu 0x59F 0>;
4134 };
4135
4136 qcom_cedev_s_cb {
4137 compatible = "qcom,qcedev,context-bank";
4138 label = "secure_context";
4139 iommus = <&apps_smmu 0x593 0>,
4140 <&apps_smmu 0x59C 0>,
4141 <&apps_smmu 0x59D 0>,
4142 <&apps_smmu 0x59E 0>;
4143 qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
4144 qcom,secure-context-bank;
4145 };
4146 };
4147
4148 qcom_crypto: qcrypto@1de0000 {
4149 compatible = "qcom,qcrypto";
4150 reg = <0x1de0000 0x20000>,
4151 <0x1dc4000 0x24000>;
4152 reg-names = "crypto-base","crypto-bam-base";
4153 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
4154 qcom,bam-pipe-pair = <2>;
4155 qcom,ce-hw-instance = <0>;
4156 qcom,ce-device = <0>;
4157 qcom,bam-ee = <0>;
4158 qcom,ce-hw-shared;
4159 qcom,clk-mgmt-sus-res;
4160 qcom,msm-bus,name = "qcrypto-noc";
4161 qcom,msm-bus,num-cases = <2>;
4162 qcom,msm-bus,num-paths = <1>;
4163 qcom,msm-bus,vectors-KBps =
4164 <125 512 0 0>,
4165 <125 512 393600 393600>;
4166 qcom,use-sw-aes-cbc-ecb-ctr-algo;
4167 qcom,use-sw-aes-xts-algo;
4168 qcom,use-sw-aes-ccm-algo;
4169 qcom,use-sw-ahash-algo;
4170 qcom,use-sw-aead-algo;
4171 qcom,use-sw-hmac-algo;
4172 qcom,smmu-s1-enable;
4173 qcom,no-clock-support;
4174 iommus = <&apps_smmu 0x0584 0x0011>,
4175 <&apps_smmu 0x0594 0x0011>;
4176 qcom,iommu-dma = "atomic";
4177 };
4178
4179 qcom_msmhdcp: qcom,msm_hdcp {
4180 compatible = "qcom,msm-hdcp";
4181 };
4182
4183 mem_dump {
4184 compatible = "qcom,mem-dump";
4185 memory-region = <&dump_mem>;
4186
4187 c0_context {
4188 qcom,dump-size = <0x800>;
4189 qcom,dump-id = <0x0>;
4190 };
4191
4192 c100_context {
4193 qcom,dump-size = <0x800>;
4194 qcom,dump-id = <0x1>;
4195 };
4196
4197 c200_context {
4198 qcom,dump-size = <0x800>;
4199 qcom,dump-id = <0x2>;
4200 };
4201
4202 c300_context {
4203 qcom,dump-size = <0x800>;
4204 qcom,dump-id = <0x3>;
4205 };
4206
4207 c400_context {
4208 qcom,dump-size = <0x800>;
4209 qcom,dump-id = <0x4>;
4210 };
4211
4212 c500_context {
4213 qcom,dump-size = <0x800>;
4214 qcom,dump-id = <0x5>;
4215 };
4216
4217 c600_context {
4218 qcom,dump-size = <0x800>;
4219 qcom,dump-id = <0x6>;
4220 };
4221
4222 c700_context {
4223 qcom,dump-size = <0x800>;
4224 qcom,dump-id = <0x7>;
4225 };
4226
4227 c0_scandump {
4228 qcom,dump-size = <0x10100>;
4229 qcom,dump-id = <0x130>;
4230 };
4231
4232 c100_scandump {
4233 qcom,dump-size = <0x10100>;
4234 qcom,dump-id = <0x131>;
4235 };
4236
4237 c200_scandump {
4238 qcom,dump-size = <0x10100>;
4239 qcom,dump-id = <0x132>;
4240 };
4241
4242 c300_scandump {
4243 qcom,dump-size = <0x10100>;
4244 qcom,dump-id = <0x133>;
4245 };
4246
4247 c400_scandump {
4248 qcom,dump-size = <0x1a4c0>;
4249 qcom,dump-id = <0x134>;
4250 };
4251
4252 c500_scandump {
4253 qcom,dump-size = <0x1a4c0>;
4254 qcom,dump-id = <0x135>;
4255 };
4256
4257 c600_scandump {
4258 qcom,dump-size = <0x1a4c0>;
4259 qcom,dump-id = <0x136>;
4260 };
4261
4262 c700_scandump {
4263 qcom,dump-size = <0x1a4c0>;
4264 qcom,dump-id = <0x137>;
4265 };
4266
4267 cpuss_reg {
4268 qcom,dump-size = <0x30000>;
4269 qcom,dump-id = <0xef>;
4270 };
4271
4272 l1_icache0 {
4273 qcom,dump-size = <0x10800>;
4274 qcom,dump-id = <0x60>;
4275 };
4276
4277 l1_icache100 {
4278 qcom,dump-size = <0x10800>;
4279 qcom,dump-id = <0x61>;
4280 };
4281
4282 l1_icache200 {
4283 qcom,dump-size = <0x10800>;
4284 qcom,dump-id = <0x62>;
4285 };
4286
4287 l1_icache300 {
4288 qcom,dump-size = <0x10800>;
4289 qcom,dump-id = <0x63>;
4290 };
4291
4292 l1_icache400 {
4293 qcom,dump-size = <0x26000>;
4294 qcom,dump-id = <0x64>;
4295 };
4296
4297 l1_icache500 {
4298 qcom,dump-size = <0x26000>;
4299 qcom,dump-id = <0x65>;
4300 };
4301
4302 l1_icache600 {
4303 qcom,dump-size = <0x26000>;
4304 qcom,dump-id = <0x66>;
4305 };
4306
4307 l1_icache700 {
4308 qcom,dump-size = <0x26000>;
4309 qcom,dump-id = <0x67>;
4310 };
4311
4312 l1_dcache0 {
4313 qcom,dump-size = <0x9000>;
4314 qcom,dump-id = <0x80>;
4315 };
4316
4317 l1_dcache100 {
4318 qcom,dump-size = <0x9000>;
4319 qcom,dump-id = <0x81>;
4320 };
4321
4322 l1_dcache200 {
4323 qcom,dump-size = <0x9000>;
4324 qcom,dump-id = <0x82>;
4325 };
4326
4327 l1_dcache300 {
4328 qcom,dump-size = <0x9000>;
4329 qcom,dump-id = <0x83>;
4330 };
4331
4332 l1_dcache400 {
4333 qcom,dump-size = <0x1A000>;
4334 qcom,dump-id = <0x84>;
4335 };
4336
4337 l1_dcache500 {
4338 qcom,dump-size = <0x1A000>;
4339 qcom,dump-id = <0x85>;
4340 };
4341
4342 l1_dcache600 {
4343 qcom,dump-size = <0x1A000>;
4344 qcom,dump-id = <0x86>;
4345 };
4346
4347 l1_dcache700 {
4348 qcom,dump-size = <0x1A000>;
4349 qcom,dump-id = <0x87>;
4350 };
4351
4352 l1_itlb400 {
4353 qcom,dump-size = <0x300>;
4354 qcom,dump-id = <0x24>;
4355 };
4356
4357 l1_itlb500 {
4358 qcom,dump-size = <0x300>;
4359 qcom,dump-id = <0x25>;
4360 };
4361
4362 l1_itlb600 {
4363 qcom,dump-size = <0x300>;
4364 qcom,dump-id = <0x26>;
4365 };
4366
4367 l1_itlb700 {
4368 qcom,dump-size = <0x300>;
4369 qcom,dump-id = <0x27>;
4370 };
4371
4372 l1_dtlb400 {
4373 qcom,dump-size = <0x480>;
4374 qcom,dump-id = <0x44>;
4375 };
4376
4377 l1_dtlb500 {
4378 qcom,dump-size = <0x480>;
4379 qcom,dump-id = <0x45>;
4380 };
4381
4382 l1_dtlb600 {
4383 qcom,dump-size = <0x480>;
4384 qcom,dump-id = <0x46>;
4385 };
4386
4387 l1_dtlb700 {
4388 qcom,dump-size = <0x480>;
4389 qcom,dump-id = <0x47>;
4390 };
4391
4392 l2_cache400 {
4393 qcom,dump-size = <0x68000>;
4394 qcom,dump-id = <0xc4>;
4395 };
4396
4397 l2_cache500 {
4398 qcom,dump-size = <0x68000>;
4399 qcom,dump-id = <0xc5>;
4400 };
4401
4402 l2_cache600 {
4403 qcom,dump-size = <0x68000>;
4404 qcom,dump-id = <0xc6>;
4405 };
4406
4407 l2_cache700 {
4408 qcom,dump-size = <0xD0000>;
4409 qcom,dump-id = <0xc7>;
4410 };
4411
4412 l2_tlb0 {
4413 qcom,dump-size = <0x6000>;
4414 qcom,dump-id = <0x120>;
4415 };
4416
4417 l2_tlb100 {
4418 qcom,dump-size = <0x6000>;
4419 qcom,dump-id = <0x121>;
4420 };
4421
4422 l2_tlb200 {
4423 qcom,dump-size = <0x6000>;
4424 qcom,dump-id = <0x122>;
4425 };
4426
4427 l2_tlb300 {
4428 qcom,dump-size = <0x6000>;
4429 qcom,dump-id = <0x123>;
4430 };
4431
4432 l2_tlb400 {
4433 qcom,dump-size = <0x7800>;
4434 qcom,dump-id = <0x124>;
4435 };
4436
4437 l2_tlb500 {
4438 qcom,dump-size = <0x7800>;
4439 qcom,dump-id = <0x125>;
4440 };
4441
4442 l2_tlb600 {
4443 qcom,dump-size = <0x7800>;
4444 qcom,dump-id = <0x126>;
4445 };
4446
4447 l2_tlb700 {
4448 qcom,dump-size = <0x7800>;
4449 qcom,dump-id = <0x127>;
4450 };
4451
4452 gemnoc {
4453 qcom,dump-size = <0x100000>;
4454 qcom,dump-id = <0x162>;
4455 };
4456
4457 mhm_scan {
4458 qcom,dump-size = <0x20000>;
4459 qcom,dump-id = <0x161>;
4460 };
4461
4462 rpmh {
4463 qcom,dump-size = <0x2000000>;
4464 qcom,dump-id = <0xec>;
4465 };
4466
4467 rpm_sw {
4468 qcom,dump-size = <0x28000>;
4469 qcom,dump-id = <0xea>;
4470 };
4471
4472 pmic {
4473 qcom,dump-size = <0x80000>;
4474 qcom,dump-id = <0xe4>;
4475 };
4476
4477 fcm {
4478 qcom,dump-size = <0x8400>;
4479 qcom,dump-id = <0xee>;
4480 };
4481
4482 etf_swao {
4483 qcom,dump-size = <0x10000>;
4484 qcom,dump-id = <0xf1>;
4485 };
4486
4487 etr_reg {
4488 qcom,dump-size = <0x1000>;
4489 qcom,dump-id = <0x100>;
4490 };
4491
4492 etfswao_reg {
4493 qcom,dump-size = <0x1000>;
4494 qcom,dump-id = <0x102>;
4495 };
4496
4497 misc_data {
4498 qcom,dump-size = <0x1000>;
4499 qcom,dump-id = <0xe8>;
4500 };
4501
4502 etf_slpi {
4503 qcom,dump-size = <0x4000>;
4504 qcom,dump-id = <0xf3>;
4505 };
4506
4507 etfslpi_reg {
4508 qcom,dump-size = <0x1000>;
4509 qcom,dump-id = <0x103>;
4510 };
4511
4512 etf_lpass {
4513 qcom,dump-size = <0x4000>;
4514 qcom,dump-id = <0xf4>;
4515 };
4516
4517 etflpass_reg {
4518 qcom,dump-size = <0x1000>;
4519 qcom,dump-id = <0x104>;
4520 };
4521
4522 osm_reg {
4523 qcom,dump-size = <0x400>;
4524 qcom,dump-id = <0x163>;
4525 };
4526
4527 pcu_reg {
4528 qcom,dump-size = <0x400>;
4529 qcom,dump-id = <0x164>;
4530 };
4531
4532 fsm_data {
4533 qcom,dump-size = <0x400>;
4534 qcom,dump-id = <0x165>;
4535 };
4536 };
4537
4538 qcom_tzlog: tz-log@146bf720 {
4539 compatible = "qcom,tz-log";
4540 reg = <0x146bf720 0x3000>;
4541 qcom,hyplog-enabled;
4542 hyplog-address-offset = <0x410>;
4543 hyplog-size-offset = <0x414>;
4544 };
4545
4546 qcom,ssc@5c00000 {
4547 compatible = "qcom,pil-tz-generic";
4548 reg = <0x5c00000 0x4000>;
4549
4550 vdd_cx-supply = <&L11A_LEVEL>;
4551 qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
4552 vdd_mx-supply = <&L4A_LEVEL>;
4553 qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
4554 qcom,proxy-reg-names = "vdd_cx", "vdd_mx";
4555
4556 clocks = <&clock_rpmh RPMH_CXO_CLK>;
4557 clock-names = "xo";
4558 qcom,proxy-clock-names = "xo";
4559
4560 qcom,pas-id = <12>;
4561 qcom,proxy-timeout-ms = <10000>;
4562 qcom,smem-id = <424>;
4563 qcom,sysmon-id = <3>;
4564 qcom,ssctl-instance-id = <0x16>;
4565 qcom,firmware-name = "slpi";
4566 status = "ok";
4567 memory-region = <&pil_slpi_mem>;
4568 qcom,complete-ramdump;
4569 qcom,signal-aop;
4570
4571 /* Inputs from ssc */
4572 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
4573 <&dsps_smp2p_in 0 0>,
4574 <&dsps_smp2p_in 2 0>,
4575 <&dsps_smp2p_in 1 0>,
4576 <&dsps_smp2p_in 3 0>;
4577
4578 interrupt-names = "qcom,wdog",
4579 "qcom,err-fatal",
4580 "qcom,proxy-unvote",
4581 "qcom,err-ready",
4582 "qcom,stop-ack";
4583
4584 /* Outputs to ssc */
4585 qcom,smem-states = <&dsps_smp2p_out 0>;
4586 qcom,smem-state-names = "qcom,force-stop";
4587
4588 mboxes = <&qmp_aop 0>;
4589 mbox-names = "slpi-pil";
4590 };
4591
4592 ssc_sensors: qcom,msm-ssc-sensors {
4593 compatible = "qcom,msm-ssc-sensors";
4594 status = "ok";
4595 qcom,firmware-name = "slpi";
4596 };
4597
4598 qcom_smcinvoke: smcinvoke@87900000 {
4599 compatible = "qcom,smcinvoke";
4600 reg = <0x87900000 0x2200000>;
4601 reg-names = "secapp-region";
4602 };
4603
4604 tsens0: tsens@c222000 {
4605 compatible = "qcom,tsens24xx";
4606 reg = <0xc222000 0x4>,
4607 <0xc263000 0x1ff>;
4608 reg-names = "tsens_srot_physical",
4609 "tsens_tm_physical";
4610 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
4611 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
4612 interrupt-names = "tsens-upper-lower", "tsens-critical";
4613 tsens-reinit-wa;
4614 #thermal-sensor-cells = <1>;
4615 };
4616
4617 tsens1: tsens@c223000 {
4618 compatible = "qcom,tsens24xx";
4619 reg = <0xc223000 0x4>,
4620 <0xc265000 0x1ff>;
4621 reg-names = "tsens_srot_physical",
4622 "tsens_tm_physical";
4623 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
4624 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
4625 interrupt-names = "tsens-upper-lower", "tsens-critical";
4626 tsens-reinit-wa;
4627 #thermal-sensor-cells = <1>;
4628 };
4629
4630 qcom,msm-rtb {
4631 compatible = "qcom,msm-rtb";
4632 qcom,rtb-size = <0x100000>;
4633 };
4634
4635 qcom,mpm2-sleep-counter@c221000 {
4636 compatible = "qcom,mpm2-sleep-counter";
4637 reg = <0xc221000 0x1000>;
4638 clock-frequency = <32768>;
4639 };
4640
4641 gpi_dma0: qcom,gpi-dma@900000 {
4642 #dma-cells = <5>;
4643 compatible = "qcom,gpi-dma";
4644 reg = <0x900000 0x70000>;
4645 reg-names = "gpi-top";
4646 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
4647 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
4648 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
4649 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
4650 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
4651 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
4652 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
4653 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
4654 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
4655 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
4656 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
4657 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
4658 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
4659 qcom,max-num-gpii = <15>;
4660 qcom,gpii-mask = <0x7ff>;
4661 qcom,ev-factor = <2>;
4662 qcom,gpi-ee-offset = <0x1000>;
4663 iommus = <&apps_smmu 0x5b6 0x0>;
4664 qcom,smmu-cfg = <0x1>;
4665 qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
4666 status = "ok";
4667 };
4668
4669 gpi_dma1: qcom,gpi-dma@a00000 {
4670 #dma-cells = <5>;
4671 compatible = "qcom,gpi-dma";
4672 reg = <0xa00000 0x70000>;
4673 reg-names = "gpi-top";
4674 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
4675 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
4676 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
4677 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
4678 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
4679 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
4680 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
4681 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
4682 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
4683 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
4684 qcom,max-num-gpii = <10>;
4685 qcom,gpii-mask = <0x3f>;
4686 qcom,ev-factor = <2>;
4687 qcom,gpi-ee-offset = <0x6000>;
4688 iommus = <&apps_smmu 0x56 0x0>;
4689 qcom,smmu-cfg = <0x1>;
4690 qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
4691 status = "ok";
4692 };
4693
4694 gpi_dma2: qcom,gpi-dma@800000 {
4695 #dma-cells = <5>;
4696 compatible = "qcom,gpi-dma";
4697 reg = <0x800000 0x70000>;
4698 reg-names = "gpi-top";
4699 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
4700 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
4701 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
4702 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
4703 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
4704 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
4705 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
4706 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
4707 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
4708 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
4709 qcom,max-num-gpii = <10>;
4710 qcom,gpii-mask = <0x3f>;
4711 qcom,ev-factor = <2>;
4712 qcom,gpi-ee-offset = <0x6000>;
4713 iommus = <&apps_smmu 0x76 0x0>;
4714 qcom,smmu-cfg = <0x1>;
4715 qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
4716 status = "ok";
4717 };
4718
4719 wlan: qcom,cnss-qca6390@b0000000 {
4720 compatible = "qcom,cnss-qca6390";
4721 reg = <0xb0000000 0x10000>,
4722 <0xb2e5510 0x5c0>;
4723 reg-names = "smmu_iova_ipa", "tcs_cmd";
4724 wlan-en-gpio = <&tlmm 20 0>;
4725 qcom,bt-en-gpio = <&tlmm 21 0>;
4726 qcom,sw-ctrl-gpio = <&tlmm 124 0>;
4727 pinctrl-names = "wlan_en_active", "wlan_en_sleep";
4728 pinctrl-0 = <&cnss_wlan_en_active>;
4729 pinctrl-1 = <&cnss_wlan_en_sleep>;
4730 qcom,wlan-rc-num = <0>;
4731 qcom,wlan-ramdump-dynamic = <0x420000>;
4732 qcom,smmu-s1-enable;
4733 qcom,converged-dt;
4734 cnss-daemon-support;
4735 qcom,cmd_db_name = "smpf2";
4736 qcom,set-wlaon-pwr-ctrl;
4737 cnss-enable-self-recovery;
4738
4739 qcom,msm-bus,name = "msm-cnss";
4740 qcom,msm-bus,num-cases = <7>;
4741 qcom,msm-bus,num-paths = <1>;
4742 qcom,msm-bus,vectors-KBps =
4743 /* no vote */
4744 <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 0 0>,
4745 /* idle: 0-18 Mbps, ddr freq: 451.2 MHz */
4746 <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 2250 1600000>,
4747 /* low: 18-60 Mbps, ddr freq: 451.2 MHz*/
4748 <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 7500 1600000>,
4749 /* medium: 60-240 Mbps, ddr freq: 451.2 MHz */
4750 <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 30000 1804800>,
4751 /* high: 240 - 800 Mbps, ddr freq: 451.2 MHz */
4752 <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 100000 1804800>,
4753 /* very high: 800 - 1400 Mbps, ddr freq: 1555.2 MHz */
4754 <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 175000 6220800>,
4755 /* low (latency critical): 18 - 60 Mbps, ddr freq: 547.2 MHz */
4756 <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 7500 2188800>;
4757
4758 vdd-wlan-aon-supply = <&pm8150_s6>;
4759 qcom,vdd-wlan-aon-config = <950000 950000 0 0 1>;
4760 vdd-wlan-dig-supply = <&pm8009_s2>;
4761 qcom,vdd-wlan-dig-config = <950000 952000 0 0 1>;
4762 vdd-wlan-io-supply = <&pm8150_s4>;
4763 qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
4764 vdd-wlan-rfa1-supply = <&pm8150_s5>;
4765 qcom,vdd-wlan-rfa1-config = <1900000 1900000 0 0 1>;
4766 vdd-wlan-rfa2-supply = <&pm8150a_s8>;
4767 qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>;
4768 wlan-ant-switch-supply = <&pm8150a_l5>;
4769 qcom,wlan-ant-switch-config = <1800000 1800000 0 0 0>;
4770
4771 mhi,max-channels = <30>;
4772 mhi,timeout = <10000>;
4773 mhi,buffer-len = <0x8000>;
4774 mhi,m2-no-db-access;
4775
4776 mhi_channels {
4777 #address-cells = <1>;
4778 #size-cells = <0>;
4779
4780 mhi_chan@0 {
4781 reg = <0>;
4782 label = "LOOPBACK";
4783 mhi,num-elements = <32>;
4784 mhi,event-ring = <1>;
4785 mhi,chan-dir = <1>;
4786 mhi,data-type = <0>;
4787 mhi,doorbell-mode = <2>;
4788 mhi,ee = <0x14>;
4789 };
4790
4791 mhi_chan@1 {
4792 reg = <1>;
4793 label = "LOOPBACK";
4794 mhi,num-elements = <32>;
4795 mhi,event-ring = <1>;
4796 mhi,chan-dir = <2>;
4797 mhi,data-type = <0>;
4798 mhi,doorbell-mode = <2>;
4799 mhi,ee = <0x14>;
4800 };
4801
4802 mhi_chan@4 {
4803 reg = <4>;
4804 label = "DIAG";
4805 mhi,num-elements = <32>;
4806 mhi,event-ring = <1>;
4807 mhi,chan-dir = <1>;
4808 mhi,data-type = <0>;
4809 mhi,doorbell-mode = <2>;
4810 mhi,ee = <0x14>;
4811 };
4812
4813 mhi_chan@5 {
4814 reg = <5>;
4815 label = "DIAG";
4816 mhi,num-elements = <32>;
4817 mhi,event-ring = <1>;
4818 mhi,chan-dir = <2>;
4819 mhi,data-type = <0>;
4820 mhi,doorbell-mode = <2>;
4821 mhi,ee = <0x14>;
4822 };
4823
4824 mhi_chan@20 {
4825 reg = <20>;
4826 label = "IPCR";
4827 mhi,num-elements = <32>;
4828 mhi,event-ring = <1>;
4829 mhi,chan-dir = <1>;
4830 mhi,data-type = <1>;
4831 mhi,doorbell-mode = <2>;
4832 mhi,ee = <0x14>;
4833 mhi,auto-start;
4834 };
4835
4836 mhi_chan@21 {
4837 reg = <21>;
4838 label = "IPCR";
4839 mhi,num-elements = <32>;
4840 mhi,event-ring = <1>;
4841 mhi,chan-dir = <2>;
4842 mhi,data-type = <0>;
4843 mhi,doorbell-mode = <2>;
4844 mhi,ee = <0x14>;
4845 mhi,auto-queue;
4846 mhi,auto-start;
4847 };
4848 };
4849
4850 mhi_events {
4851 mhi_event@0 {
4852 mhi,num-elements = <32>;
4853 mhi,intmod = <0>;
4854 mhi,msi = <1>;
4855 mhi,priority = <1>;
4856 mhi,brstmode = <2>;
4857 mhi,data-type = <1>;
4858 };
4859
4860 mhi_event@1 {
4861 mhi,num-elements = <256>;
4862 mhi,intmod = <0>;
4863 mhi,msi = <2>;
4864 mhi,priority = <1>;
4865 mhi,brstmode = <2>;
4866 };
4867
4868 mhi_event@2 {
4869 mhi,num-elements = <32>;
4870 mhi,intmod = <1>;
4871 mhi,msi = <0>;
4872 mhi,priority = <2>;
4873 mhi,brstmode = <2>;
4874 mhi,data-type = <3>;
4875 };
4876 };
4877
4878 mhi_devices {
4879 mhi_qrtr {
4880 mhi,chan = "IPCR";
4881 qcom,net-id = <0>;
4882 qcom,low-latency;
4883 mhi,early-notify;
4884 };
4885 };
4886 };
4887
4888 wil6210: qcom,wil6210 {
4889 compatible = "qcom,wil6210";
4890 qcom,pcie-parent = <&pcie1>;
4891 pinctrl-names = "default";
4892 pinctrl-0 = <&wil6210_refclk_en_pin>;
4893 qcom,msm-bus,name = "wil6210";
4894 qcom,msm-bus,num-cases = <3>;
4895 qcom,msm-bus,num-paths = <1>;
4896 qcom,msm-bus,vectors-KBps =
4897 <100 512 0 0>,
4898 <100 512 600000 800000>, /* ~4.6Gbps (MCS12) */
4899 <100 512 1300000 1300000>; /* ~10.1Gbps */
4900 qcom,use-ext-supply;
4901 vdd-ldo-supply = <&pm8150_l15>;
4902 vddio-supply = <&pm8150_s5>;
4903 qcom,use-ext-clocks;
4904 clocks = <&clock_rpmh RPMH_RF_CLK1>;
4905 clock-names = "rf_clk";
4906 qcom,keep-radio-on-during-sleep;
4907 qcom,use-ap-power-save;
4908 status = "disabled";
4909 };
4910
4911 tspp: msm_tspp@8880000 {
4912 compatible = "qcom,msm_tspp";
4913 reg = <0x088a7000 0x200>, /* MSM_TSIF0_PHYS */
4914 <0x088a8000 0x200>, /* MSM_TSIF1_PHYS */
4915 <0x088a9000 0x1000>, /* MSM_TSPP_PHYS */
4916 <0x08884000 0x23000>; /* MSM_TSPP_BAM_PHYS */
4917 reg-names = "MSM_TSIF0_PHYS",
4918 "MSM_TSIF1_PHYS",
4919 "MSM_TSPP_PHYS",
4920 "MSM_TSPP_BAM_PHYS";
4921 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,/*TSIF_TSPP_IRQ*/
4922 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, /* TSIF0_IRQ */
4923 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, /* TSIF1_IRQ */
4924 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; /* TSIF_BAM_IRQ */
4925 interrupt-names = "TSIF_TSPP_IRQ",
4926 "TSIF0_IRQ",
4927 "TSIF1_IRQ",
4928 "TSIF_BAM_IRQ";
4929
4930 clock-names = "iface_clk", "ref_clk";
4931 clocks = <&clock_gcc GCC_TSIF_AHB_CLK>,
4932 <&clock_gcc GCC_TSIF_REF_CLK>;
4933
4934 qcom,msm-bus,name = "tsif";
4935 qcom,msm-bus,num-cases = <2>;
4936 qcom,msm-bus,num-paths = <1>;
4937 qcom,msm-bus,vectors-KBps =
4938 <82 512 0 0>, /* No vote */
4939 <82 512 12288 24576>;
4940 /* Max. bandwidth, 2xTSIF, each max of 96Mbps */
4941
4942 pinctrl-names = "disabled",
4943 "tsif0-mode1", "tsif0-mode2",
4944 "tsif1-mode1", "tsif1-mode2",
4945 "dual-tsif-mode1", "dual-tsif-mode2";
4946
4947 pinctrl-0 = <>; /* disabled */
4948 pinctrl-1 = <&tsif0_signals_active>; /* tsif0-mode1 */
4949 pinctrl-2 = <&tsif0_signals_active
4950 &tsif0_sync_active>; /* tsif0-mode2 */
4951 pinctrl-3 = <&tsif1_signals_active>; /* tsif1-mode1 */
4952 pinctrl-4 = <&tsif1_signals_active
4953 &tsif1_sync_active>; /* tsif1-mode2 */
4954 pinctrl-5 = <&tsif0_signals_active
4955 &tsif1_signals_active>; /* dual-tsif-mode1 */
4956 pinctrl-6 = <&tsif0_signals_active
4957 &tsif0_sync_active
4958 &tsif1_signals_active
4959 &tsif1_sync_active>; /* dual-tsif-mode2 */
4960
4961 memory-region = <&qseecom_mem>;
4962 iommus = <&apps_smmu 0xA0 0x00>;
4963 qcom,iommu-dma-addr-pool = <0x10000000 0x40000000>;
4964 qcom,smmu-s1-enable;
4965 };
4966
4967 demux {
4968 compatible = "qcom,demux";
4969 };
4970
4971 qfprom: qfprom@780000 {
4972 compatible = "qcom,qfprom";
4973 reg = <0x00780000 0x5000>;
4974 #address-cells = <1>;
4975 #size-cells = <1>;
4976 read-only;
4977 ranges;
4978
4979 gpu_lm_efuse: gpu_lm_efuse@45c8 {
4980 reg = <0x45c8 0x4>;
4981 };
4982
4983 gpu_speed_bin: gpu_speed_bin@419b {
4984 reg = <0x419b 0x1>;
4985 bits = <5 3>;
4986 };
4987
4988 thermal_speed_bin: thermal-speed-bin@1a2 {
4989 reg = <0x1a2 0x1>;
4990 bits = <7 1>;
4991 };
4992 };
4993};
4994
4995#include "kona-regulators.dtsi"
4996#include "kona-bus.dtsi"
4997#include "kona-ion.dtsi"
4998#include "kona-pcie.dtsi"
4999#include "kona-mhi.dtsi"
5000
5001&pcie0_rp {
5002 #address-cells = <5>;
5003 #size-cells = <0>;
5004
5005 cnss_pci: cnss_pci {
5006 reg = <0 0 0 0 0>;
5007 qcom,iommu-group = <&cnss_pci_iommu_group>;
5008 memory-region = <&cnss_wlan_mem>;
5009
5010 #address-cells = <1>;
5011 #size-cells = <1>;
5012
5013 cnss_pci_iommu_group: cnss_pci_iommu_group {
5014 qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
5015 qcom,iommu-dma = "fastmap";
5016 qcom,iommu-pagetable = "coherent";
5017 qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
5018 "non-fatal";
5019 };
5020 };
5021};
5022
5023&pcie1_rp {
5024 #address-cells = <5>;
5025 #size-cells = <0>;
5026
5027 wil6210_pci: wil6210_pci {
5028 reg = <0 0 0 0 0>;
5029 qcom,iommu-group = <&wil6210_pci_iommu_group>;
5030
5031 #address-cells = <1>;
5032 #size-cells = <1>;
5033
5034 wil6210_pci_iommu_group: wil6210_pci_iommu_group {
5035 reg = <0 0>;
5036 qcom,iommu-dma-addr-pool = <0x60000000 0xa0000000>;
5037 qcom,iommu-dma = "fastmap";
5038 qcom,iommu-pagetable = "coherent";
5039 };
5040 };
5041};
5042
5043#include "msm-arm-smmu-kona.dtsi"
5044#include "kona-pinctrl.dtsi"
5045#include "kona-smp2p.dtsi"
5046#include "kona-usb.dtsi"
5047#include "kona-coresight.dtsi"
5048#include "kona-sde.dtsi"
5049#include "kona-sde-pll.dtsi"
5050#include "msm-rdbg.dtsi"
5051
5052#include "kona-pm.dtsi"
5053#include "camera/kona-camera.dtsi"
5054#include "kona-qupv3.dtsi"
5055#include "kona-audio.dtsi"
5056#include "kona-audio-ar.dtsi"
5057#include "kona-thermal.dtsi"
5058#include "kona-vidc.dtsi"
5059#include "kona-cvp.dtsi"
5060#include "kona-npu.dtsi"
5061#include "kona-gpu.dtsi"
5062#include "msm-qvr-external.dtsi"
5063#include "ipcc-test.dtsi"
5064
5065&qupv3_se15_i2c {
5066 status = "ok";
5067 nq@64 {
5068 compatible = "rtc6226";
5069 reg = <0x64>;
5070 fmint-gpio = <&tlmm 51 0>;
5071 vdd-supply = <&pm8150a_bob>;
5072 rtc6226,vdd-supply-voltage = <3296000 3296000>;
5073 vio-supply = <&pm8150_s4>;
5074 rtc6226,vio-supply-voltage = <1800000 1800000 >;
5075 };
5076};