Luca Weiss | 9b02244 | 2023-04-14 14:47:36 +0200 | [diff] [blame^] | 1 | &soc { |
| 2 | mdss_dsi0_pll: qcom,mdss_dsi0_pll { |
| 3 | compatible = "qcom,mdss_dsi_pll_10nm"; |
| 4 | label = "MDSS DSI 0 PLL"; |
| 5 | cell-index = <0>; |
| 6 | #clock-cells = <1>; |
| 7 | reg = <0xae94a00 0x1e0>, |
| 8 | <0xae94400 0x800>, |
| 9 | <0xaf03000 0x8>, |
| 10 | <0xae94200 0x100>; |
| 11 | reg-names = "pll_base", "phy_base", "gdsc_base", |
| 12 | "dynamic_pll_base"; |
| 13 | clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; |
| 14 | clock-names = "iface_clk"; |
| 15 | clock-rate = <0>; |
| 16 | memory-region = <&dfps_data_memory>; |
| 17 | qcom,dsi-pll-ssc-en; |
| 18 | qcom,dsi-pll-ssc-mode = "down-spread"; |
| 19 | }; |
| 20 | |
| 21 | mdss_dp_pll: qcom,mdss_dp_pll@ae90000 { |
| 22 | compatible = "qcom,mdss_dp_pll_10nm"; |
| 23 | label = "MDSS DP PLL"; |
| 24 | cell-index = <0>; |
| 25 | #clock-cells = <1>; |
| 26 | |
| 27 | reg = <0x088ea000 0x200>, |
| 28 | <0x088eaa00 0x200>, |
| 29 | <0x088ea200 0x200>, |
| 30 | <0x088ea600 0x200>, |
| 31 | <0xaf03000 0x8>; |
| 32 | reg-names = "pll_base", "phy_base", "ln_tx0_base", |
| 33 | "ln_tx1_base", "gdsc_base"; |
| 34 | |
| 35 | clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| 36 | <&rpmhcc RPMH_QLINK_CLK>, |
| 37 | <&gcc GCC_USB3_PRIM_CLKREF_CLK>, |
| 38 | <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; |
| 39 | clock-names = "iface_clk", "ref_clk_src", "ref_clk", |
| 40 | "pipe_clk"; |
| 41 | clock-rate = <0>; |
| 42 | }; |
| 43 | |
| 44 | }; |