Luca Weiss | 9b02244 | 2023-04-14 14:47:36 +0200 | [diff] [blame^] | 1 | &soc { |
| 2 | pil_gpu: qcom,kgsl-hyp { |
| 3 | compatible = "qcom,pil-tz-generic"; |
| 4 | qcom,pas-id = <13>; |
| 5 | qcom,firmware-name = "a620_zap"; |
| 6 | }; |
| 7 | |
| 8 | msm_bus: qcom,kgsl-busmon { |
| 9 | label = "kgsl-busmon"; |
| 10 | compatible = "qcom,kgsl-busmon"; |
| 11 | operating-points-v2 = <&gpu_opp_table>; |
| 12 | }; |
| 13 | |
| 14 | gpubw: qcom,gpubw { |
| 15 | compatible = "qcom,devbw"; |
| 16 | governor = "bw_vbif"; |
| 17 | qcom,src-dst-ports = <26 512>; |
| 18 | operating-points-v2 = <&suspendable_ddr_bw_opp_table>; |
| 19 | }; |
| 20 | |
| 21 | gpu_opp_table: gpu-opp-table { |
| 22 | compatible = "operating-points-v2"; |
| 23 | |
| 24 | opp-750000000 { |
| 25 | opp-hz = /bits/ 64 <750000000>; |
| 26 | opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>; |
| 27 | }; |
| 28 | |
| 29 | opp-700000000 { |
| 30 | opp-hz = /bits/ 64 <700000000>; |
| 31 | opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| 32 | }; |
| 33 | |
| 34 | opp-670000000 { |
| 35 | opp-hz = /bits/ 64 <670000000>; |
| 36 | opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| 37 | }; |
| 38 | |
| 39 | opp-625000000 { |
| 40 | opp-hz = /bits/ 64 <625000000>; |
| 41 | opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>; |
| 42 | }; |
| 43 | |
| 44 | opp-540000000 { |
| 45 | opp-hz = /bits/ 64 <540000000>; |
| 46 | opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>; |
| 47 | }; |
| 48 | |
| 49 | opp-500000000 { |
| 50 | opp-hz = /bits/ 64 <500000000>; |
| 51 | opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| 52 | }; |
| 53 | |
| 54 | opp-400000000 { |
| 55 | opp-hz = /bits/ 64 <400000000>; |
| 56 | opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>; |
| 57 | }; |
| 58 | |
| 59 | opp-275000000 { |
| 60 | opp-hz = /bits/ 64 <275000000>; |
| 61 | opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
| 62 | }; |
| 63 | }; |
| 64 | |
| 65 | msm_gpu: qcom,kgsl-3d0@3d00000 { |
| 66 | label = "kgsl-3d0"; |
| 67 | compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d"; |
| 68 | status = "ok"; |
| 69 | reg = <0x3d00000 0x40000>, <0x3d61000 0x800>, |
| 70 | <0x3de0000 0x1000>, <0x3d8b000 0x2000>; |
| 71 | reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc", |
| 72 | "isense_cntl"; |
| 73 | interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; |
| 74 | interrupt-names = "kgsl_3d0_irq"; |
| 75 | qcom,id = <0>; |
| 76 | |
| 77 | qcom,chipid = <0x06020000>; |
| 78 | |
| 79 | qcom,initial-pwrlevel = <3>; |
| 80 | |
| 81 | qcom,idle-timeout = <80>; /* msecs */ |
| 82 | |
| 83 | qcom,highest-bank-bit = <14>; |
| 84 | |
| 85 | qcom,min-access-length = <32>; |
| 86 | |
| 87 | qcom,ubwc-mode = <3>; |
| 88 | qcom,no-nap; |
| 89 | qcom,snapshot-size = <2048576>; /* bytes */ |
| 90 | qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ |
| 91 | |
| 92 | #cooling-cells = <2>; |
| 93 | qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; |
| 94 | |
| 95 | /* CPU latency parameter */ |
| 96 | qcom,pm-qos-active-latency = <67>; |
| 97 | qcom,pm-qos-wakeup-latency = <67>; |
| 98 | |
| 99 | /* Enable context aware freq. scaling */ |
| 100 | qcom,enable-ca-jump; |
| 101 | /* Context aware jump busy penalty in us */ |
| 102 | qcom,ca-busy-penalty = <12000>; |
| 103 | |
| 104 | clocks = <&gpucc GPU_CC_CXO_CLK>, |
| 105 | <&gcc GCC_DDRSS_GPU_AXI_CLK>, |
| 106 | <&gcc GCC_GPU_MEMNOC_GFX_CLK>, |
| 107 | <&gpucc GPU_CC_CX_GMU_CLK>, |
| 108 | <&gpucc GPU_CC_AHB_CLK>, |
| 109 | <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; |
| 110 | |
| 111 | clock-names = "rbbmtimer_clk", "mem_clk", |
| 112 | "mem_iface_clk", "gmu_clk", |
| 113 | "gpu_cc_ahb", "smmu_vote"; |
| 114 | |
| 115 | qcom,gpubw-dev = <&gpubw>; |
| 116 | qcom,bus-control; |
| 117 | qcom,msm-bus,name = "grp3d"; |
| 118 | qcom,msm-bus,num-cases = <13>; |
| 119 | qcom,msm-bus,num-paths = <1>; |
| 120 | qcom,msm-bus,vectors-KBps = |
| 121 | <26 512 0 0>, |
| 122 | <26 512 0 400000>, /* 1 bus=100 */ |
| 123 | <26 512 0 800000>, /* 2 bus=200 */ |
| 124 | <26 512 0 1200000>, /* 3 bus=300 */ |
| 125 | <26 512 0 1804800>, /* 4 bus=451 */ |
| 126 | <26 512 0 2188000>, /* 5 bus=547 */ |
| 127 | <26 512 0 2724000>, /* 6 bus=681 */ |
| 128 | <26 512 0 3072000>, /* 7 bus=768 */ |
| 129 | <26 512 0 4068000>, /* 8 bus=1017 */ |
| 130 | <26 512 0 5412000>, /* 9 bus=1353 */ |
| 131 | <26 512 0 6220000>, /* 10 bus=1555 */ |
| 132 | <26 512 0 7216000>, /* 11 bus=1804 */ |
| 133 | <26 512 0 8371200>; /* 12 bus=2092 */ |
| 134 | |
| 135 | /* GDSC regulator names */ |
| 136 | regulator-names = "vddcx", "vdd"; |
| 137 | /* GDSC oxili regulators */ |
| 138 | vddcx-supply = <&gpu_cx_gdsc>; |
| 139 | vdd-supply = <&gpu_gx_gdsc>; |
| 140 | |
| 141 | nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>, <&gpu_lm_efuse>; |
| 142 | nvmem-cell-names = "speed_bin", "gaming_bin", "isense_slope"; |
| 143 | |
| 144 | /* GPU OPP data */ |
| 145 | operating-points-v2 = <&gpu_opp_table>; |
| 146 | |
| 147 | /* GPU Mempools */ |
| 148 | qcom,gpu-mempools { |
| 149 | #address-cells = <1>; |
| 150 | #size-cells = <0>; |
| 151 | compatible = "qcom,gpu-mempools"; |
| 152 | |
| 153 | /* 4K Page Pool configuration */ |
| 154 | qcom,gpu-mempool@0 { |
| 155 | reg = <0>; |
| 156 | qcom,mempool-page-size = <4096>; |
| 157 | qcom,mempool-reserved = <2048>; |
| 158 | qcom,mempool-allocate; |
| 159 | }; |
| 160 | /* 8K Page Pool configuration */ |
| 161 | qcom,gpu-mempool@1 { |
| 162 | reg = <1>; |
| 163 | qcom,mempool-page-size = <8192>; |
| 164 | qcom,mempool-reserved = <1024>; |
| 165 | qcom,mempool-allocate; |
| 166 | }; |
| 167 | /* 64K Page Pool configuration */ |
| 168 | qcom,gpu-mempool@2 { |
| 169 | reg = <2>; |
| 170 | qcom,mempool-page-size = <65536>; |
| 171 | qcom,mempool-reserved = <256>; |
| 172 | }; |
| 173 | /* 1M Page Pool configuration */ |
| 174 | qcom,gpu-mempool@3 { |
| 175 | reg = <3>; |
| 176 | qcom,mempool-page-size = <1048576>; |
| 177 | qcom,mempool-reserved = <32>; |
| 178 | }; |
| 179 | }; |
| 180 | |
| 181 | /* |
| 182 | * Speed-bin zero is default speed bin. |
| 183 | * For rest of the speed bins, speed-bin value |
| 184 | * is calulated as FMAX/4.8 MHz round up to zero |
| 185 | * decimal places. |
| 186 | */ |
| 187 | qcom,gpu-pwrlevel-bins { |
| 188 | #address-cells = <1>; |
| 189 | #size-cells = <0>; |
| 190 | |
| 191 | compatible="qcom,gpu-pwrlevel-bins"; |
| 192 | |
| 193 | qcom,gpu-pwrlevels-0 { |
| 194 | #address-cells = <1>; |
| 195 | #size-cells = <0>; |
| 196 | |
| 197 | qcom,speed-bin = <0>; |
| 198 | qcom,ca-target-pwrlevel = <2>; |
| 199 | qcom,initial-pwrlevel = <3>; |
| 200 | |
| 201 | /* NOM */ |
| 202 | qcom,gpu-pwrlevel@0 { |
| 203 | reg = <0>; |
| 204 | qcom,gpu-freq = <625000000>; |
| 205 | qcom,bus-freq = <10>; |
| 206 | qcom,bus-min = <9>; |
| 207 | qcom,bus-max = <12>; |
| 208 | qcom,acd-level = <0x802C5FFD>; |
| 209 | }; |
| 210 | |
| 211 | /* SVS L1 */ |
| 212 | qcom,gpu-pwrlevel@1 { |
| 213 | reg = <1>; |
| 214 | qcom,gpu-freq = <500000000>; |
| 215 | qcom,bus-freq = <8>; |
| 216 | qcom,bus-min = <7>; |
| 217 | qcom,bus-max = <10>; |
| 218 | qcom,acd-level = <0xA02C5FFD>; |
| 219 | }; |
| 220 | |
| 221 | /* SVS */ |
| 222 | qcom,gpu-pwrlevel@2 { |
| 223 | reg = <2>; |
| 224 | qcom,gpu-freq = <400000000>; |
| 225 | qcom,bus-freq = <7>; |
| 226 | qcom,bus-min = <5>; |
| 227 | qcom,bus-max = <8>; |
| 228 | qcom,acd-level = <0xA02C5FFD>; |
| 229 | }; |
| 230 | |
| 231 | /* Low SVS */ |
| 232 | qcom,gpu-pwrlevel@3 { |
| 233 | reg = <3>; |
| 234 | qcom,gpu-freq = <275000000>; |
| 235 | qcom,bus-freq = <5>; |
| 236 | qcom,bus-min = <5>; |
| 237 | qcom,bus-max = <7>; |
| 238 | qcom,acd-level = <0x802F5FFD>; |
| 239 | }; |
| 240 | |
| 241 | qcom,gpu-pwrlevel@4 { |
| 242 | reg = <4>; |
| 243 | qcom,gpu-freq = <0>; |
| 244 | qcom,bus-freq = <0>; |
| 245 | qcom,bus-min = <0>; |
| 246 | qcom,bus-max = <0>; |
| 247 | }; |
| 248 | }; |
| 249 | |
| 250 | qcom,gpu-pwrlevels-1 { |
| 251 | #address-cells = <1>; |
| 252 | #size-cells = <0>; |
| 253 | |
| 254 | qcom,speed-bin = <132>; |
| 255 | |
| 256 | qcom,initial-pwrlevel = <3>; |
| 257 | qcom,ca-target-pwrlevel = <2>; |
| 258 | |
| 259 | /* NOM */ |
| 260 | qcom,gpu-pwrlevel@0 { |
| 261 | reg = <0>; |
| 262 | qcom,gpu-freq = <625000000>; |
| 263 | qcom,bus-freq = <10>; |
| 264 | qcom,bus-min = <9>; |
| 265 | qcom,bus-max = <12>; |
| 266 | qcom,acd-level = <0x802C5FFD>; |
| 267 | }; |
| 268 | |
| 269 | /* SVS L1 */ |
| 270 | qcom,gpu-pwrlevel@1 { |
| 271 | reg = <1>; |
| 272 | qcom,gpu-freq = <500000000>; |
| 273 | qcom,bus-freq = <8>; |
| 274 | qcom,bus-min = <7>; |
| 275 | qcom,bus-max = <10>; |
| 276 | qcom,acd-level = <0xA02C5FFD>; |
| 277 | }; |
| 278 | |
| 279 | /* SVS */ |
| 280 | qcom,gpu-pwrlevel@2 { |
| 281 | reg = <2>; |
| 282 | qcom,gpu-freq = <400000000>; |
| 283 | qcom,bus-freq = <7>; |
| 284 | qcom,bus-min = <5>; |
| 285 | qcom,bus-max = <8>; |
| 286 | qcom,acd-level = <0xA02C5FFD>; |
| 287 | }; |
| 288 | |
| 289 | /* Low SVS */ |
| 290 | qcom,gpu-pwrlevel@3 { |
| 291 | reg = <3>; |
| 292 | qcom,gpu-freq = <275000000>; |
| 293 | qcom,bus-freq = <5>; |
| 294 | qcom,bus-min = <5>; |
| 295 | qcom,bus-max = <7>; |
| 296 | qcom,acd-level = <0x802F5FFD>; |
| 297 | }; |
| 298 | |
| 299 | qcom,gpu-pwrlevel@4 { |
| 300 | reg = <4>; |
| 301 | qcom,gpu-freq = <0>; |
| 302 | qcom,bus-freq = <0>; |
| 303 | qcom,bus-min = <0>; |
| 304 | qcom,bus-max = <0>; |
| 305 | }; |
| 306 | }; |
| 307 | |
| 308 | qcom,gpu-pwrlevels-3 { |
| 309 | #address-cells = <1>; |
| 310 | #size-cells = <0>; |
| 311 | |
| 312 | qcom,speed-bin = <115>; |
| 313 | qcom,initial-pwrlevel = <2>; |
| 314 | qcom,ca-target-pwrlevel = <1>; |
| 315 | |
| 316 | /* SVS L1 */ |
| 317 | qcom,gpu-pwrlevel@0 { |
| 318 | reg = <0>; |
| 319 | qcom,gpu-freq = <540000000>; |
| 320 | qcom,bus-freq = <8>; |
| 321 | qcom,bus-min = <7>; |
| 322 | qcom,bus-max = <12>; |
| 323 | qcom,acd-level = <0x802C5FFD>; |
| 324 | }; |
| 325 | |
| 326 | /* SVS */ |
| 327 | qcom,gpu-pwrlevel@1 { |
| 328 | reg = <1>; |
| 329 | qcom,gpu-freq = <400000000>; |
| 330 | qcom,bus-freq = <7>; |
| 331 | qcom,bus-min = <5>; |
| 332 | qcom,bus-max = <8>; |
| 333 | qcom,acd-level = <0xA02C5FFD>; |
| 334 | }; |
| 335 | |
| 336 | /* Low SVS */ |
| 337 | qcom,gpu-pwrlevel@2 { |
| 338 | reg = <2>; |
| 339 | qcom,gpu-freq = <275000000>; |
| 340 | qcom,bus-freq = <5>; |
| 341 | qcom,bus-min = <5>; |
| 342 | qcom,bus-max = <7>; |
| 343 | qcom,acd-level = <0x802F5FFD>; |
| 344 | }; |
| 345 | |
| 346 | qcom,gpu-pwrlevel@3 { |
| 347 | reg = <3>; |
| 348 | qcom,gpu-freq = <0>; |
| 349 | qcom,bus-freq = <0>; |
| 350 | qcom,bus-min = <0>; |
| 351 | qcom,bus-max = <0>; |
| 352 | }; |
| 353 | }; |
| 354 | }; |
| 355 | |
| 356 | qcom,cpu-to-gpu-cfg-path { |
| 357 | qcom,msm-bus,name = "gpu_cfg"; |
| 358 | qcom,msm-bus,num-cases = <3>; |
| 359 | qcom,msm-bus,num-paths = <1>; |
| 360 | qcom,msm-bus,vectors-KBps = |
| 361 | <1 598 0 0>, // off |
| 362 | <1 598 0 100>, // min freq |
| 363 | <1 598 0 9999999>; // max freq |
| 364 | }; |
| 365 | }; |
| 366 | |
| 367 | kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 { |
| 368 | compatible = "qcom,kgsl-smmu-v2"; |
| 369 | |
| 370 | reg = <0x03da0000 0x10000>; |
| 371 | /* CB5(ATOS) & CB5/6/7 are protected by HYP */ |
| 372 | qcom,protect = <0xa0000 0xc000>; |
| 373 | |
| 374 | clocks =<&gcc GCC_GPU_MEMNOC_GFX_CLK>, |
| 375 | <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, |
| 376 | <&gpucc GPU_CC_AHB_CLK>, |
| 377 | <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; |
| 378 | |
| 379 | clock-names = "gcc_gpu_memnoc_gfx", |
| 380 | "gcc_gpu_snoc_dvm_gfx", |
| 381 | "gpu_cc_ahb", "smmu_vote"; |
| 382 | |
| 383 | qcom,secure_align_mask = <0xfff>; |
| 384 | qcom,retention; |
| 385 | qcom,hyp_secure_alloc; |
| 386 | |
| 387 | gfx3d_user: gfx3d_user { |
| 388 | compatible = "qcom,smmu-kgsl-cb"; |
| 389 | label = "gfx3d_user"; |
| 390 | iommus = <&kgsl_smmu 0x0 0x401>; |
| 391 | qcom,iommu-dma = "disabled"; |
| 392 | qcom,gpu-offset = <0xa8000>; |
| 393 | }; |
| 394 | |
| 395 | gfx3d_secure: gfx3d_secure { |
| 396 | compatible = "qcom,smmu-kgsl-cb"; |
| 397 | label = "gfx3d_secure"; |
| 398 | iommus = <&kgsl_smmu 0x2 0x400>; |
| 399 | qcom,iommu-dma = "disabled"; |
| 400 | }; |
| 401 | }; |
| 402 | |
| 403 | gmu: qcom,gmu@3d6a000 { |
| 404 | label = "kgsl-gmu"; |
| 405 | compatible = "qcom,gpu-gmu"; |
| 406 | |
| 407 | reg = <0x3d6a000 0x30000>, |
| 408 | <0xb290000 0x10000>, |
| 409 | <0xb490000 0x10000>; |
| 410 | reg-names = "kgsl_gmu_reg", |
| 411 | "kgsl_gmu_pdc_cfg", |
| 412 | "kgsl_gmu_pdc_seq"; |
| 413 | |
| 414 | interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>, |
| 415 | <0 305 IRQ_TYPE_LEVEL_HIGH>; |
| 416 | interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq"; |
| 417 | |
| 418 | qcom,msm-bus,name = "cnoc"; |
| 419 | qcom,msm-bus,num-cases = <2>; |
| 420 | qcom,msm-bus,num-paths = <1>; |
| 421 | qcom,msm-bus,vectors-KBps = |
| 422 | <26 10036 0 0>, /* CNOC off */ |
| 423 | <26 10036 0 100>; /* CNOC on */ |
| 424 | |
| 425 | regulator-names = "vddcx", "vdd"; |
| 426 | vddcx-supply = <&gpu_cx_gdsc>; |
| 427 | vdd-supply = <&gpu_gx_gdsc>; |
| 428 | |
| 429 | clocks = <&gpucc GPU_CC_CX_GMU_CLK>, |
| 430 | <&gpucc GPU_CC_CXO_CLK>, |
| 431 | <&gcc GCC_DDRSS_GPU_AXI_CLK>, |
| 432 | <&gcc GCC_GPU_MEMNOC_GFX_CLK>, |
| 433 | <&gpucc GPU_CC_AHB_CLK>, |
| 434 | <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, |
| 435 | <&aopcc QDSS_CLK>; |
| 436 | |
| 437 | clock-names = "gmu_clk", "cxo_clk", "axi_clk", |
| 438 | "memnoc_clk", "gpu_cc_ahb", "smmu_vote", |
| 439 | "apb_pclk"; |
| 440 | |
| 441 | /* AOP mailbox for sending ACD enable and disable messages */ |
| 442 | mboxes = <&qmp_aop 0>; |
| 443 | mbox-names = "aop"; |
| 444 | |
| 445 | gmu_user: gmu_user { |
| 446 | compatible = "qcom,smmu-gmu-user-cb"; |
| 447 | iommus = <&kgsl_smmu 0x4 0x400>; |
| 448 | qcom,iommu-dma = "disabled"; |
| 449 | }; |
| 450 | |
| 451 | gmu_kernel: gmu_kernel { |
| 452 | compatible = "qcom,smmu-gmu-kernel-cb"; |
| 453 | iommus = <&kgsl_smmu 0x5 0x400>; |
| 454 | qcom,iommu-dma = "disabled"; |
| 455 | }; |
| 456 | }; |
| 457 | }; |