blob: 3e85d3e85a52fa44d9a93ea66847d323a681608f [file] [log] [blame]
Luca Weiss9b022442023-04-14 14:47:36 +02001#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"
2#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi"
3#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi"
4#include "dsi-panel-sharp-dualdsi-wqhd-video.dtsi"
5#include "dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi"
6#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
7#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
8#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi"
9#include "dsi-panel-sharp-qsync-wqhd-video.dtsi"
10#include "dsi-panel-sharp-qsync-fhd-cmd.dtsi"
11#include "dsi-panel-sharp-qsync-fhd-video.dtsi"
12#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
13#include "dsi-panel-sharp-dsc-4k-video.dtsi"
14#include "dsi-panel-sim-cmd.dtsi"
15#include "dsi-panel-sim-video.dtsi"
16#include "dsi-panel-sim-dsc375-cmd.dtsi"
17#include "dsi-panel-sim-dualmipi-cmd.dtsi"
18#include "dsi-panel-sim-dualmipi-video.dtsi"
19#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
20#include "dsi-panel-sim-sec-hd-cmd.dtsi"
21#include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi"
22#include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi"
23#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
24
25&pm8150l_gpios {
26 disp_pins {
27 disp_pins_default: disp_pins_default {
28 pins = "gpio3";
29 function = "func1";
30 qcom,drive-strength = <2>;
31 power-source = <0>;
32 bias-disable;
33 output-low;
34 };
35 };
36};
37
38&soc {
39 ext_disp: qcom,msm-ext-disp {
40 compatible = "qcom,msm-ext-disp";
41
42 ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
43 compatible = "qcom,msm-ext-disp-audio-codec-rx";
44 };
45 };
46
47 dsi_panel_pwr_supply: dsi_panel_pwr_supply {
48 #address-cells = <1>;
49 #size-cells = <0>;
50
51 qcom,panel-supply-entry@0 {
52 reg = <0>;
53 qcom,supply-name = "vddio";
54 qcom,supply-min-voltage = <1800000>;
55 qcom,supply-max-voltage = <1800000>;
56 qcom,supply-enable-load = <62000>;
57 qcom,supply-disable-load = <80>;
58 qcom,supply-post-on-sleep = <20>;
59 };
60
61 qcom,panel-supply-entry@1 {
62 reg = <1>;
63 qcom,supply-name = "vdd";
64 qcom,supply-min-voltage = <3000000>;
65 qcom,supply-max-voltage = <3000000>;
66 qcom,supply-enable-load = <857000>;
67 qcom,supply-disable-load = <0>;
68 qcom,supply-post-on-sleep = <0>;
69 };
70
71 qcom,panel-supply-entry@2 {
72 reg = <2>;
73 qcom,supply-name = "lab";
74 qcom,supply-min-voltage = <4600000>;
75 qcom,supply-max-voltage = <6000000>;
76 qcom,supply-enable-load = <100000>;
77 qcom,supply-disable-load = <100>;
78 };
79
80 qcom,panel-supply-entry@3 {
81 reg = <3>;
82 qcom,supply-name = "ibb";
83 qcom,supply-min-voltage = <4600000>;
84 qcom,supply-max-voltage = <6000000>;
85 qcom,supply-enable-load = <100000>;
86 qcom,supply-disable-load = <100>;
87 qcom,supply-post-on-sleep = <20>;
88 };
89 };
90
91 dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd {
92 #address-cells = <1>;
93 #size-cells = <0>;
94
95 qcom,panel-supply-entry@0 {
96 reg = <0>;
97 qcom,supply-name = "vddio";
98 qcom,supply-min-voltage = <1800000>;
99 qcom,supply-max-voltage = <1800000>;
100 qcom,supply-enable-load = <62000>;
101 qcom,supply-disable-load = <80>;
102 qcom,supply-post-on-sleep = <20>;
103 };
104
105 qcom,panel-supply-entry@1 {
106 reg = <1>;
107 qcom,supply-name = "avdd";
108 qcom,supply-min-voltage = <4600000>;
109 qcom,supply-max-voltage = <6000000>;
110 qcom,supply-enable-load = <100000>;
111 qcom,supply-disable-load = <100>;
112 };
113 };
114
115 dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
116 #address-cells = <1>;
117 #size-cells = <0>;
118
119 qcom,panel-supply-entry@0 {
120 reg = <0>;
121 qcom,supply-name = "vddio";
122 qcom,supply-min-voltage = <1800000>;
123 qcom,supply-max-voltage = <1800000>;
124 qcom,supply-enable-load = <62000>;
125 qcom,supply-disable-load = <80>;
126 qcom,supply-post-on-sleep = <20>;
127 };
128 };
129
130 sde_dsi: qcom,dsi-display-primary {
131 compatible = "qcom,dsi-display";
132 label = "primary";
133
134 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
135 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
136
137 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
138 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
139 <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
140 <&mdss_dsi0_pll PCLK_SRC_0_CLK>,
141 <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,
142 <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>,
143 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
144 <&mdss_dsi1_pll PCLK_MUX_1_CLK>,
145 <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>,
146 <&mdss_dsi1_pll PCLK_SRC_1_CLK>,
147 <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>,
148 <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>;
149 clock-names = "mux_byte_clk0", "mux_pixel_clk0",
150 "src_byte_clk0", "src_pixel_clk0",
151 "shadow_byte_clk0", "shadow_pixel_clk0",
152 "mux_byte_clk1", "mux_pixel_clk1",
153 "src_byte_clk1", "src_pixel_clk1",
154 "shadow_byte_clk1", "shadow_pixel_clk1";
155
156 pinctrl-names = "panel_active", "panel_suspend";
157 pinctrl-0 = <&sde_te_active &disp_pins_default>;
158 pinctrl-1 = <&sde_te_suspend>;
159
160 qcom,platform-te-gpio = <&tlmm 10 0>;
161 qcom,panel-te-source = <0>;
162
163 vddio-supply = <&L1C>;
164 vdd-supply = <&L16A>;
165 lab-supply = <&ab_vreg>;
166 ibb-supply = <&ibb_vreg>;
167
168 qcom,mdp = <&mdss_mdp>;
169 qcom,dsi-default-panel = <&dsi_sw43404_amoled_video>;
170 };
171
172 sde_dsi1: qcom,dsi-display-secondary {
173 compatible = "qcom,dsi-display";
174 label = "secondary";
175
176 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
177 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
178
179 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
180 <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
181 <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
182 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
183 clock-names = "mux_byte_clk0", "mux_pixel_clk0",
184 "mux_byte_clk1", "mux_pixel_clk1";
185
186 pinctrl-names = "panel_active", "panel_suspend";
187 pinctrl-0 = <&sde_te1_active>;
188 pinctrl-1 = <&sde_te1_suspend>;
189
190 qcom,platform-te-gpio = <&tlmm 11 0>;
191 qcom,panel-te-source = <1>;
192
193 vddio-supply = <&L1C>;
194 vdd-supply = <&L16A>;
195
196 qcom,mdp = <&mdss_mdp>;
197 };
198
199 sde_wb: qcom,wb-display@0 {
200 compatible = "qcom,wb-display";
201 cell-index = <0>;
202 label = "wb_display";
203 };
204
205 msm_notifier: qcom,msm_notifier@0 {
206 compatible = "qcom,msm-notifier";
207 panel = <&dsi_sw43404_amoled_cmd &dsi_sharp_qsync_wqhd_cmd
208 &dsi_dual_sim_dsc_375_cmd &dsi_sw43404_amoled_video
209 &dsi_sharp_qsync_wqhd_video &dsi_sharp_qsync_fhd_cmd
210 &dsi_sharp_qsync_fhd_video>;
211 };
212};
213
214&sde_dp {
215 qcom,dp-usbpd-detection = <&pm7250b_pdphy>;
216 qcom,ext-disp = <&ext_disp>;
217 qcom,dp-aux-switch = <&fsa4480>;
218 extcon = <&pm7250b_pdphy>;
219
220 qcom,usbplug-cc-gpio = <&tlmm 114 0>;
221
222 pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
223 pinctrl-0 = <&sde_dp_usbplug_cc_active>;
224 pinctrl-1 = <&sde_dp_usbplug_cc_suspend>;
225};
226
227&mdss_mdp {
228 connectors = <&sde_wb &sde_dsi &sde_dsi1 &sde_dp &sde_rscc>;
229};
230
231&dsi_rm69299_visionox_amoled_video {
232 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
233 qcom,mdss-dsi-display-timings {
234 timing@0 {
235 qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08
236 08 05 02 04 00 1a 18];
237 qcom,display-topology = <1 0 1>;
238 qcom,default-topology-index = <0>;
239 };
240 };
241};
242
243/* PHY TIMINGS REVISION W */
244&dsi_sw43404_amoled_cmd {
245 qcom,ulps-enabled;
246 qcom,esd-check-enabled;
247 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
248 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
249 qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
250 qcom,mdss-dsi-panel-status-value = <0x9c>;
251 qcom,mdss-dsi-panel-status-read-length = <1>;
252
253 qcom,dsi-dyn-clk-enable;
254 qcom,dsi-dyn-clk-list = <552424501 549895420 547366339>;
255
256 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
257 "src_byte_clk0", "src_pixel_clk0",
258 "shadow_byte_clk0", "shadow_pixel_clk0";
259 qcom,mdss-dsi-display-timings {
260 timing@0 {
261 qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
262 05 03 02 04 00 12 15];
263 qcom,display-topology = <2 2 1>;
264 qcom,default-topology-index = <0>;
265 qcom,partial-update-enabled = "single_roi";
266 qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
267 };
268
269 timing@1 {
270 qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 1f 1e 05
271 05 03 02 04 00 12 14];
272 qcom,display-topology = <2 2 1>;
273 qcom,default-topology-index = <0>;
274 qcom,partial-update-enabled = "single_roi";
275 qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
276 };
277
278 timing@2 {
279 qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 1e 1e 04
280 04 02 02 04 00 10 14];
281 qcom,display-topology = <2 2 1>;
282 qcom,default-topology-index = <0>;
283 qcom,partial-update-enabled = "single_roi";
284 qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
285 };
286 };
287};
288
289&dsi_sw43404_amoled_video {
290 qcom,dsi-supported-dfps-list = <60 57 55>;
291 qcom,mdss-dsi-pan-enable-dynamic-fps;
292 qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";
293 qcom,mdss-dsi-min-refresh-rate = <55>;
294 qcom,mdss-dsi-max-refresh-rate = <60>;
295 qcom,mdss-dsi-qsync-min-refresh-rate = <55>;
296 qcom,esd-check-enabled;
297 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
298 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
299 qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
300 qcom,mdss-dsi-panel-status-value = <0x9c>;
301 qcom,mdss-dsi-panel-status-read-length = <1>;
302
303 qcom,dsi-dyn-clk-enable;
304 qcom,dsi-dyn-clk-list =
305 <534712320 536940288 539168256>;
306 qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp";
307
308 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
309 "src_byte_clk0", "src_pixel_clk0",
310 "shadow_byte_clk0", "shadow_pixel_clk0";
311 qcom,mdss-dsi-display-timings {
312 timing@0 {
313 qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
314 05 03 02 04 00 12 15];
315 qcom,display-topology = <2 2 1>;
316 qcom,default-topology-index = <0>;
317 };
318 };
319};
320
321&dsi_sw43404_amoled_fhd_plus_cmd {
322 qcom,ulps-enabled;
323 qcom,esd-check-enabled;
324 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
325 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
326 qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
327 qcom,mdss-dsi-panel-status-value = <0x9c>;
328 qcom,mdss-dsi-panel-status-read-length = <1>;
329 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
330 qcom,mdss-dsi-display-timings {
331 timing@0 {
332 qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04
333 05 02 03 04 00 11 14];
334 qcom,display-topology = <1 1 1>;
335 qcom,default-topology-index = <0>;
336 qcom,partial-update-enabled = "single_roi";
337 qcom,panel-roi-alignment = <540 270 270 270 1080 270>;
338 qcom,mdss-dsi-panel-clockrate = <380000000>;
339 };
340 };
341};
342
343&dsi_sim_cmd {
344 qcom,ulps-enabled;
345 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
346 qcom,mdss-dsi-display-timings {
347 timing@0 {
348 qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
349 07 05 02 04 00 18 17];
350 qcom,display-topology = <1 1 1>,
351 <2 2 1>;
352 qcom,default-topology-index = <1>;
353 };
354
355 timing@1 {
356 qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
357 07 05 02 04 00 18 17];
358 qcom,display-topology = <1 1 1>,
359 <2 2 1>;
360 qcom,default-topology-index = <1>;
361 };
362
363 timing@2 {
364 qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
365 07 05 02 04 00 18 17];
366 qcom,display-topology = <1 1 1>,
367 <2 2 1>;
368 qcom,default-topology-index = <1>;
369 qcom,panel-roi-alignment = <720 40 720 40 720 40>;
370 qcom,partial-update-enabled = "single_roi";
371 };
372
373 timing@3 {
374 qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
375 07 05 02 04 00 18 17];
376 qcom,display-topology = <1 1 1>,
377 <2 2 1>;
378 qcom,default-topology-index = <1>;
379 qcom,panel-roi-alignment = <540 40 540 40 540 40>;
380 qcom,partial-update-enabled = "single_roi";
381 };
382
383 timing@4 {
384 qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
385 07 05 02 04 00 18 17];
386 qcom,display-topology = <1 1 1>,
387 <2 2 1>;
388 qcom,default-topology-index = <1>;
389 qcom,panel-roi-alignment = <360 40 360 40 360 40>;
390 qcom,partial-update-enabled = "single_roi";
391 };
392 };
393};
394
395&dsi_sim_vid {
396 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
397 qcom,mdss-dsi-display-timings {
398 timing@0 {
399 qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
400 07 05 02 04 00 18 17];
401 qcom,display-topology = <1 0 1>,
402 <2 0 1>;
403 qcom,default-topology-index = <0>;
404 };
405 };
406};
407
408&dsi_sim_dsc_375_cmd {
409 qcom,ulps-enabled;
410 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
411 qcom,mdss-dsi-display-timings {
412 timing@0 { /* 1080p */
413 qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
414 07 05 02 04 00 18 17];
415 qcom,display-topology = <1 1 1>;
416 qcom,default-topology-index = <0>;
417 };
418
419 timing@1 { /* qhd */
420 qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
421 08 05 02 04 00 19 18];
422 qcom,display-topology = <1 1 1>,
423 <2 2 1>, /* dsc merge */
424 <2 1 1>; /* 3d mux */
425 qcom,default-topology-index = <0>;
426 };
427 };
428};
429
430&dsi_dual_sim_cmd {
431 qcom,ulps-enabled;
432 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
433 qcom,mdss-dsi-display-timings {
434 timing@0 {
435 qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
436 09 06 02 04 00 18 17];
437 qcom,display-topology = <2 0 2>;
438 qcom,default-topology-index = <0>;
439 };
440
441 timing@1 {
442 qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
443 07 05 02 04 00 18 17];
444 qcom,display-topology = <2 0 2>,
445 <1 0 2>;
446 qcom,default-topology-index = <0>;
447 };
448
449 timing@2 {
450 qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
451 08 05 02 04 00 19 18];
452 qcom,display-topology = <2 0 2>;
453 qcom,default-topology-index = <0>;
454 };
455 };
456};
457
458&dsi_dual_sim_vid {
459 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
460 qcom,mdss-dsi-display-timings {
461 timing@0 {
462 qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
463 07 05 02 04 00 18 17];
464 qcom,display-topology = <2 0 2>,
465 <1 0 2>;
466 qcom,default-topology-index = <0>;
467 };
468 };
469};
470
471&dsi_dual_sim_dsc_375_cmd {
472 qcom,ulps-enabled;
473 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
474 qcom,mdss-dsi-display-timings {
475 timing@0 { /* qhd */
476 qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
477 07 05 02 04 00 18 17];
478 qcom,display-topology = <2 2 2>;
479 qcom,default-topology-index = <0>;
480 };
481
482 timing@1 { /* 4k */
483 qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
484 08 05 02 04 00 19 18];
485 qcom,display-topology = <2 2 2>;
486 qcom,default-topology-index = <0>;
487 };
488
489 timing@2 { /* 5k */
490 qcom,mdss-dsi-panel-phy-timings = [00 46 13 14 33 30 12
491 14 0e 02 04 00 37 22];
492 qcom,display-topology = <2 2 2>;
493 qcom,default-topology-index = <0>;
494 };
495 };
496};
497
498&dsi_sim_sec_hd_cmd {
499 qcom,ulps-enabled;
500 qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
501 qcom,mdss-dsi-display-timings {
502 timing@0 {
503 qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
504 08 08 05 02 04 00 19 17];
505 qcom,display-topology = <1 0 1>;
506 qcom,default-topology-index = <0>;
507 qcom,panel-roi-alignment = <720 40 720 40 720 40>;
508 qcom,partial-update-enabled = "single_roi";
509 };
510 };
511};
512
513&dsi_dual_sharp_wqhd_video {
514 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
515 qcom,mdss-dsi-display-timings {
516 timing@0 {
517 qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21
518 07 07 04 02 04 00 17 16];
519 qcom,display-topology = <2 0 2>;
520 qcom,default-topology-index = <0>;
521 };
522 };
523};
524
525&dsi_dual_sharp_wqhd_cmd {
526 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
527 qcom,mdss-dsi-display-timings {
528 timing@0 {
529 qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21
530 07 07 04 02 04 00 17 16];
531 qcom,display-topology = <2 0 2>;
532 qcom,default-topology-index = <0>;
533 };
534 };
535};
536
537&dsi_sharp_4k_dsc_cmd {
538 qcom,ulps-enabled;
539 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
540 qcom,mdss-dsi-display-timings {
541 timing@0 {
542 qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
543 08 05 02 04 00 19 18];
544 qcom,display-topology = <2 2 2>;
545 qcom,default-topology-index = <0>;
546 };
547 };
548};
549
550&dsi_sharp_4k_dsc_video {
551 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
552 qcom,mdss-dsi-display-timings {
553 timing@0 {
554 qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
555 08 05 02 04 00 19 18];
556 qcom,display-topology = <2 2 2>;
557 qcom,default-topology-index = <0>;
558 };
559 };
560};
561
562&dsi_nt35695b_truly_fhd_cmd {
563 qcom,ulps-enabled;
564 qcom,esd-check-enabled;
565 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
566 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
567 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
568 qcom,mdss-dsi-panel-status-value = <0x9c>;
569 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
570 qcom,mdss-dsi-panel-status-read-length = <1>;
571 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
572 qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
573 qcom,mdss-dsi-display-timings {
574 timing@0 {
575 qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
576 08 08 05 02 04 00 19 17];
577 qcom,display-topology = <1 0 1>;
578 qcom,default-topology-index = <0>;
579 };
580 };
581};
582
583&dsi_nt35695b_truly_fhd_video {
584 qcom,esd-check-enabled;
585 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
586 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
587 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
588 qcom,mdss-dsi-panel-status-value = <0x9c>;
589 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
590 qcom,mdss-dsi-panel-status-read-length = <1>;
591 qcom,dsi-supported-dfps-list = <60 55 48>;
592 qcom,mdss-dsi-pan-enable-dynamic-fps;
593 qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
594 qcom,mdss-dsi-min-refresh-rate = <48>;
595 qcom,mdss-dsi-max-refresh-rate = <60>;
596 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
597 qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
598 qcom,mdss-dsi-display-timings {
599 timing@0 {
600 qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
601 08 08 05 02 04 00 19 17];
602 qcom,display-topology = <1 0 1>;
603 qcom,default-topology-index = <0>;
604 };
605 };
606};
607
608&dsi_sharp_qsync_wqhd_cmd {
609 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
610 qcom,mdss-dsi-display-timings {
611 timing@0 { /* WQHD 60FPS CMD */
612 qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 1d 1c 03
613 03 01 02 04 00 0c 12];
614 qcom,display-topology = <2 2 2>;
615 qcom,default-topology-index = <0>;
616 qcom,partial-update-enabled = "single_roi";
617 qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
618 };
619
620 timing@1 { /* WQHD 60FPS VID */
621 qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06
622 06 03 02 04 00 13 15];
623 qcom,display-topology = <2 2 2>;
624 qcom,default-topology-index = <0>;
625 };
626
627 timing@2 { /* FHD 60FPS CMD */
628 qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02
629 02 00 02 04 00 0a 12];
630 qcom,display-topology = <2 2 2>;
631 qcom,default-topology-index = <0>;
632 qcom,partial-update-enabled = "single_roi";
633 qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
634 };
635
636 timing@3 { /* WQHD 90FPS CMD */
637 qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 1e 1e 04
638 04 02 02 04 00 0f 13];
639 qcom,display-topology = <2 2 2>;
640 qcom,default-topology-index = <0>;
641 qcom,partial-update-enabled = "single_roi";
642 qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
643 };
644
645 timing@4 { /* WQHD 120FPS CMD */
646 qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1f 1e 05
647 05 03 02 04 00 12 14];
648 qcom,display-topology = <2 2 2>;
649 qcom,default-topology-index = <0>;
650 qcom,partial-update-enabled = "single_roi";
651 qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
652 };
653
654 timing@5 { /* WQHD 120FPS VID */
655 qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06
656 06 03 02 04 00 13 15];
657 qcom,display-topology = <2 2 2>;
658 qcom,default-topology-index = <0>;
659 };
660
661 timing@6 { /* FHD 120FPS CMD */
662 qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04
663 04 02 02 04 00 0e 13];
664 qcom,display-topology = <2 2 2>;
665 qcom,default-topology-index = <0>;
666 qcom,partial-update-enabled = "single_roi";
667 qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
668 };
669
670 timing@7 { /* FHD 90FPS CMD */
671 qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03
672 02 01 02 04 00 0c 12];
673 qcom,display-topology = <2 2 2>;
674 qcom,default-topology-index = <0>;
675 qcom,partial-update-enabled = "single_roi";
676 qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
677 };
678 };
679};
680
681
682&dsi_sharp_qsync_wqhd_video {
683 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
684 qcom,dsi-supported-dfps-list = <120 90 60>;
685 qcom,mdss-dsi-pan-enable-dynamic-fps;
686 qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
687 qcom,mdss-dsi-min-refresh-rate = <60>;
688 qcom,mdss-dsi-max-refresh-rate = <120>;
689 qcom,mdss-dsi-display-timings {
690 timing@0 {
691 qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06
692 06 03 02 04 00 13 15];
693 qcom,display-topology = <2 2 2>;
694 qcom,default-topology-index = <0>;
695 };
696 };
697};
698
699&dsi_sharp_qsync_fhd_video {
700 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
701 qcom,dsi-supported-dfps-list = <120 90 60>;
702 qcom,mdss-dsi-pan-enable-dynamic-fps;
703 qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
704 qcom,mdss-dsi-min-refresh-rate = <60>;
705 qcom,mdss-dsi-max-refresh-rate = <120>;
706 qcom,mdss-dsi-display-timings {
707 timing@0 {
708 qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 1f 1f 04
709 05 03 02 04 00 12 14];
710 qcom,display-topology = <2 2 2>;
711 qcom,default-topology-index = <0>;
712 };
713 };
714};
715
716&dsi_sharp_qsync_fhd_cmd {
717 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
718 qcom,mdss-dsi-display-timings {
719 timing@0 {
720 qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02
721 02 00 02 04 00 0a 12];
722 qcom,display-topology = <2 2 2>;
723 qcom,default-topology-index = <0>;
724 qcom,partial-update-enabled = "single_roi";
725 qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
726 };
727
728 timing@1 {
729 qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04
730 04 02 02 04 00 0e 13];
731 qcom,display-topology = <2 2 2>;
732 qcom,default-topology-index = <0>;
733 qcom,partial-update-enabled = "single_roi";
734 qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
735 };
736
737 timing@2 {
738 qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03
739 02 01 02 04 00 0c 12];
740 qcom,display-topology = <2 2 2>;
741 qcom,default-topology-index = <0>;
742 qcom,partial-update-enabled = "single_roi";
743 qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
744 };
745 };
746};
747
748&dsi_r66451_amoled_144hz_cmd {
749 qcom,esd-check-enabled;
750 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
751 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
752 qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
753 qcom,mdss-dsi-panel-status-value = <0x1c>;
754 qcom,mdss-dsi-panel-status-read-length = <1>;
755 qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
756 qcom,mdss-dsi-display-timings {
757 timing@0 {
758 qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 17 09
759 09 09 02 04 00 1d 0e];
760 qcom,display-topology = <2 2 1>;
761 qcom,default-topology-index = <0>;
762 };
763 };
764};