| Luca Weiss | 9b02244 | 2023-04-14 14:47:36 +0200 | [diff] [blame^] | 1 | / { |
| 2 | psci { |
| 3 | compatible = "arm,psci-1.0"; |
| 4 | method = "smc"; |
| 5 | }; |
| 6 | |
| 7 | cpus { |
| 8 | #address-cells = <1>; |
| 9 | #size-cells = <0>; |
| 10 | cpu-map { |
| 11 | |
| 12 | cluster0 { |
| 13 | }; |
| 14 | |
| 15 | cluster1 { |
| 16 | core0 { |
| 17 | cpu = <&CPU0>; |
| 18 | }; |
| 19 | |
| 20 | core1 { |
| 21 | cpu = <&CPU1>; |
| 22 | }; |
| 23 | |
| 24 | core2 { |
| 25 | cpu = <&CPU2>; |
| 26 | }; |
| 27 | |
| 28 | core3 { |
| 29 | cpu = <&CPU3>; |
| 30 | }; |
| 31 | }; |
| 32 | }; |
| 33 | |
| 34 | CPU0: cpu@100 { |
| 35 | device_type = "cpu"; |
| 36 | compatible = "arm,cortex-a53"; |
| 37 | reg = <0x100>; |
| 38 | enable-method = "psci"; |
| 39 | cpu-release-addr = <0x0 0x90000000>; |
| 40 | capacity-dmips-mhz = <1024>; |
| 41 | sched-energy-costs = <&CPU_COST_0>; |
| 42 | next-level-cache = <&L2_1>; |
| 43 | #cooling-cells = <2>; |
| 44 | L2_1: l2-cache { |
| 45 | compatible = "arm,arch-cache"; |
| 46 | cache-level = <2>; |
| 47 | }; |
| 48 | |
| 49 | L1_I_100: l1-icache { |
| 50 | compatible = "arm,arch-cache"; |
| 51 | }; |
| 52 | |
| 53 | L1_D_100: l1-dcache { |
| 54 | compatible = "arm,arch-cache"; |
| 55 | }; |
| 56 | }; |
| 57 | |
| 58 | CPU1: cpu@101 { |
| 59 | device_type = "cpu"; |
| 60 | compatible = "arm,cortex-a53"; |
| 61 | reg = <0x101>; |
| 62 | enable-method = "psci"; |
| 63 | cpu-release-addr = <0x0 0x90000000>; |
| 64 | capacity-dmips-mhz = <1024>; |
| 65 | sched-energy-costs = <&CPU_COST_0>; |
| 66 | next-level-cache = <&L2_1>; |
| 67 | #cooling-cells = <2>; |
| 68 | L1_I_101: l1-icache { |
| 69 | compatible = "arm,arch-cache"; |
| 70 | }; |
| 71 | |
| 72 | L1_D_101: l1-dcache { |
| 73 | compatible = "arm,arch-cache"; |
| 74 | }; |
| 75 | }; |
| 76 | |
| 77 | CPU2: cpu@102 { |
| 78 | device_type = "cpu"; |
| 79 | compatible = "arm,cortex-a53"; |
| 80 | reg = <0x102>; |
| 81 | enable-method = "psci"; |
| 82 | cpu-release-addr = <0x0 0x90000000>; |
| 83 | capacity-dmips-mhz = <1024>; |
| 84 | sched-energy-costs = <&CPU_COST_0>; |
| 85 | next-level-cache = <&L2_1>; |
| 86 | #cooling-cells = <2>; |
| 87 | L1_I_102: l1-icache { |
| 88 | compatible = "arm,arch-cache"; |
| 89 | }; |
| 90 | |
| 91 | L1_D_102: l1-dcache { |
| 92 | compatible = "arm,arch-cache"; |
| 93 | }; |
| 94 | }; |
| 95 | |
| 96 | CPU3: cpu@103 { |
| 97 | device_type = "cpu"; |
| 98 | compatible = "arm,cortex-a53"; |
| 99 | reg = <0x103>; |
| 100 | enable-method = "psci"; |
| 101 | cpu-release-addr = <0x0 0x90000000>; |
| 102 | capacity-dmips-mhz = <1024>; |
| 103 | sched-energy-costs = <&CPU_COST_0>; |
| 104 | next-level-cache = <&L2_1>; |
| 105 | #cooling-cells = <2>; |
| 106 | L1_I_103: l1-icache { |
| 107 | compatible = "arm,arch-cache"; |
| 108 | }; |
| 109 | |
| 110 | L1_D_103: l1-dcache { |
| 111 | compatible = "arm,arch-cache"; |
| 112 | }; |
| 113 | }; |
| 114 | |
| 115 | }; |
| 116 | |
| 117 | energy_costs: energy-costs { |
| 118 | |
| 119 | CPU_COST_0: core-cost0 { |
| 120 | busy-cost-data = < |
| 121 | 656 159 |
| 122 | 682 172 |
| 123 | 748 207 |
| 124 | 827 244 |
| 125 | 853 256 |
| 126 | 893 283 |
| 127 | 958 327 |
| 128 | 1024 343 |
| 129 | >; |
| 130 | }; |
| 131 | }; |
| 132 | }; |