Luca Weiss | 9b02244 | 2023-04-14 14:47:36 +0200 | [diff] [blame^] | 1 | #include <dt-bindings/clock/qcom,audio-ext-clk.h> |
| 2 | #include <dt-bindings/sound/qcom,bolero-clk-rsc.h> |
| 3 | #include <dt-bindings/sound/audio-codec-port-types.h> |
| 4 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 5 | |
| 6 | &bolero { |
| 7 | qcom,num-macros = <3>; |
| 8 | qcom,bolero-version = <5>; |
| 9 | bolero-clk-rsc-mngr { |
| 10 | compatible = "qcom,bolero-clk-rsc-mngr"; |
| 11 | qcom,fs-gen-sequence = <0x3000 0x1>, |
| 12 | <0x3004 0x1>, <0x3080 0x2>; |
| 13 | qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; |
| 14 | qcom,va_mclk_mode_muxsel = <0x0a7a0000>; |
| 15 | clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk", |
| 16 | "va_core_clk", "va_npl_clk"; |
| 17 | clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>, |
| 18 | <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>, |
| 19 | <&clock_audio_va_1 0>, <&clock_audio_va_2 0>; |
| 20 | }; |
| 21 | |
| 22 | tx_macro: tx-macro@0a620000 { |
| 23 | compatible = "qcom,tx-macro"; |
| 24 | reg = <0x0a620000 0x0>; |
| 25 | clock-names = "tx_core_clk", "tx_npl_clk"; |
| 26 | clocks = <&clock_audio_tx_1 0>, |
| 27 | <&clock_audio_tx_2 0>; |
| 28 | qcom,tx-dmic-sample-rate = <2400000>; |
| 29 | qcom,is-used-swr-gpio = <0>; |
| 30 | }; |
| 31 | |
| 32 | rx_macro: rx-macro@0a600000 { |
| 33 | compatible = "qcom,rx-macro"; |
| 34 | reg = <0x0a600000 0x0>; |
| 35 | clock-names = "rx_core_clk", "rx_npl_clk"; |
| 36 | clocks = <&clock_audio_rx_1 0>, |
| 37 | <&clock_audio_rx_2 0>; |
| 38 | qcom,rx-swr-gpios = <&rx_swr_gpios>; |
| 39 | qcom,rx_mclk_mode_muxsel = <0x0a5640d8>; |
| 40 | qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>; |
| 41 | qcom,default-clk-id = <TX_CORE_CLK>; |
| 42 | swr1: rx_swr_master { |
| 43 | compatible = "qcom,swr-mstr"; |
| 44 | #address-cells = <2>; |
| 45 | #size-cells = <0>; |
| 46 | clock-names = "lpass_audio_hw_vote"; |
| 47 | clocks = <&lpass_audio_hw_vote 0>; |
| 48 | qcom,swr_master_id = <2>; |
| 49 | qcom,swrm-hctl-reg = <0x0a6a9098>; |
| 50 | qcom,mipi-sdw-block-packing-mode = <1>; |
| 51 | swrm-io-base = <0x0a610000 0x0>; |
| 52 | interrupts = <0 297 IRQ_TYPE_LEVEL_HIGH>; |
| 53 | interrupt-names = "swr_master_irq"; |
| 54 | qcom,swr-num-ports = <5>; |
| 55 | qcom,disable-div2-clk-switch = <1>; |
| 56 | qcom,swr-port-mapping = <1 HPH_L 0x1>, |
| 57 | <1 HPH_R 0x2>, <2 CLSH 0x1>, |
| 58 | <3 COMP_L 0x1>, <3 COMP_R 0x2>, |
| 59 | <4 LO 0x1>, <5 DSD_L 0x1>, |
| 60 | <5 DSD_R 0x2>; |
| 61 | qcom,swr-num-dev = <1>; |
| 62 | qcom,swr-clock-stop-mode0 = <1>; |
| 63 | rouleur_rx_slave: rouleur-rx-slave { |
| 64 | compatible = "qcom,rouleur-slave"; |
| 65 | reg = <0x0C 0x01170224>; |
| 66 | }; |
| 67 | }; |
| 68 | }; |
| 69 | |
| 70 | va_macro: va-macro@0a730000 { |
| 71 | compatible = "qcom,va-macro"; |
| 72 | reg = <0x0a730000 0x0>; |
| 73 | clock-names = "lpass_audio_hw_vote"; |
| 74 | clocks = <&lpass_audio_hw_vote 0>; |
| 75 | qcom,va-dmic-sample-rate = <600000>; |
| 76 | qcom,va-clk-mux-select = <1>; |
| 77 | qcom,va-island-mode-muxsel = <0x0a7a0000>; |
| 78 | qcom,default-clk-id = <TX_CORE_CLK>; |
| 79 | qcom,is-used-swr-gpio = <1>; |
| 80 | qcom,va-swr-gpios = <&va_swr_gpios>; |
| 81 | swr0: va_swr_master { |
| 82 | compatible = "qcom,swr-mstr"; |
| 83 | #address-cells = <2>; |
| 84 | #size-cells = <0>; |
| 85 | clock-names = "lpass_audio_hw_vote"; |
| 86 | clocks = <&lpass_audio_hw_vote 0>; |
| 87 | qcom,swr_master_id = <3>; |
| 88 | qcom,swrm-hctl-reg = <0x0a7ec100>; |
| 89 | qcom,mipi-sdw-block-packing-mode = <1>; |
| 90 | swrm-io-base = <0x0a740000 0x0>; |
| 91 | interrupts = |
| 92 | <0 296 IRQ_TYPE_LEVEL_HIGH>, |
| 93 | <0 79 IRQ_TYPE_LEVEL_HIGH>; |
| 94 | interrupt-names = "swr_master_irq", "swr_wake_irq"; |
| 95 | qcom,swr-wakeup-required = <1>; |
| 96 | qcom,swr-num-ports = <3>; |
| 97 | qcom,swr-port-mapping = <1 ADC1 0x1>, <1 ADC2 0x2>, |
| 98 | <1 ADC3 0x4>, <1 ADC4 0x8>, |
| 99 | <2 DMIC0 0x1>, <2 DMIC1 0x2>, |
| 100 | <2 DMIC2 0x4>, <2 DMIC3 0x8>, |
| 101 | <3 DMIC4 0x1>, <3 DMIC5 0x2>, |
| 102 | <3 DMIC6 0x4>, <3 DMIC7 0x8>; |
| 103 | qcom,swr-num-dev = <1>; |
| 104 | qcom,swr-clock-stop-mode0 = <1>; |
| 105 | qcom,swr-mstr-irq-wakeup-capable = <1>; |
| 106 | rouleur_tx_slave: rouleur-tx-slave { |
| 107 | compatible = "qcom,rouleur-slave"; |
| 108 | reg = <0x0C 0x01170223>; |
| 109 | }; |
| 110 | }; |
| 111 | }; |
| 112 | |
| 113 | rouleur_codec: rouleur-codec { |
| 114 | compatible = "qcom,rouleur-codec"; |
| 115 | qcom,split-codec = <1>; |
| 116 | qcom,pmic-spmi-node = <&pm2250_cdc>; |
| 117 | qcom,wcd-reset-reg = <0x0000F3DB>; |
| 118 | qcom,foundry-id-reg = <0x0000704D>; |
| 119 | qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>, |
| 120 | <0 HPH_R 0x2 0 HPH_R>, |
| 121 | <1 COMP_L 0x1 0 COMP_L>, <1 COMP_R 0x2 0 COMP_R>; |
| 122 | qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>, |
| 123 | <0 ADC2 0x2 0 ADC2>, <0 DMIC0 0x4 0 ADC3>, |
| 124 | <0 MBHC 0x8 0 ADC4>, <1 DMIC0 0x1 0 DMIC0>, |
| 125 | <1 DMIC1 0x2 0 DMIC1>, <1 ADC1 0x4 0 DMIC2>, |
| 126 | <1 MBHC 0x8 0 DMIC3>; |
| 127 | |
| 128 | qcom,rx-slave = <&rouleur_rx_slave>; |
| 129 | qcom,tx-slave = <&rouleur_tx_slave>; |
| 130 | |
| 131 | cdc-vdd-io-supply = <&L15A>; |
| 132 | qcom,cdc-vdd-io-voltage = <1800000 1800000>; |
| 133 | qcom,cdc-vdd-io-current = <10000>; |
| 134 | |
| 135 | cdc-vdd-cp-supply = <&S4A>; |
| 136 | qcom,cdc-vdd-cp-voltage = <2040000 2040000>; |
| 137 | qcom,cdc-vdd-cp-current = <300000>; |
| 138 | |
| 139 | cdc-pa-vpos-supply = <&S4A>; |
| 140 | qcom,cdc-pa-vpos-voltage = <2040000 2040000>; |
| 141 | qcom,cdc-pa-vpos-current = <2400000>; |
| 142 | |
| 143 | cdc-vdd-mic-bias-supply = <&L22A>; |
| 144 | qcom,cdc-vdd-mic-bias-voltage = <3000000 3304000>; |
| 145 | qcom,cdc-vdd-mic-bias-current = <50000>; |
| 146 | qcom,cdc-vdd-mic-bias-lpm-supported = <1>; |
| 147 | |
| 148 | qcom,cdc-micbias1-mv = <1800>; |
| 149 | qcom,cdc-micbias2-mv = <1800>; |
| 150 | qcom,cdc-micbias3-mv = <1800>; |
| 151 | |
| 152 | qcom,cdc-static-supplies = "cdc-vdd-cp", |
| 153 | "cdc-vdd-io", |
| 154 | "cdc-vdd-mic-bias"; |
| 155 | qcom,cdc-on-demand-supplies = "cdc-pa-vpos"; |
| 156 | }; |
| 157 | }; |
| 158 | |
| 159 | &scuba_snd { |
| 160 | qcom,model = "bengal-scubaidp-snd-card"; |
| 161 | qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; |
| 162 | qcom,wcn-btfm = <1>; |
| 163 | qcom,va-bolero-codec = <1>; |
| 164 | qcom,rxtx-bolero-codec = <1>; |
| 165 | qcom,audio-routing = |
| 166 | "AMIC1", "MIC BIAS1", |
| 167 | "MIC BIAS1", "Analog Mic1", |
| 168 | "AMIC2", "MIC BIAS2", |
| 169 | "MIC BIAS2", "Analog Mic2", |
| 170 | "AMIC3", "MIC BIAS3", |
| 171 | "MIC BIAS3", "Analog Mic3", |
| 172 | "TX DMIC0", "MIC BIAS3", |
| 173 | "MIC BIAS3", "Digital Mic0", |
| 174 | "TX DMIC1", "MIC BIAS3", |
| 175 | "MIC BIAS3", "Digital Mic1", |
| 176 | "TX DMIC2", "MIC BIAS1", |
| 177 | "MIC BIAS1", "Digital Mic2", |
| 178 | "TX DMIC3", "MIC BIAS1", |
| 179 | "MIC BIAS1", "Digital Mic3", |
| 180 | "IN1_HPHL", "HPHL_OUT", |
| 181 | "IN2_HPHR", "HPHR_OUT", |
| 182 | "SpkrMono WSA_IN", "LO", |
| 183 | "TX SWR_MIC0", "ADC1_OUTPUT", |
| 184 | "TX SWR_MIC1", "ADC2_OUTPUT", |
| 185 | "TX SWR_MIC2", "DMIC1_OUTPUT", |
| 186 | "TX SWR_MIC5", "DMIC2_OUTPUT", |
| 187 | "TX SWR_MIC0", "VA_TX_SWR_CLK", |
| 188 | "TX SWR_MIC1", "VA_TX_SWR_CLK", |
| 189 | "TX SWR_MIC2", "VA_TX_SWR_CLK", |
| 190 | "TX SWR_MIC3", "VA_TX_SWR_CLK", |
| 191 | "TX SWR_MIC4", "VA_TX_SWR_CLK", |
| 192 | "TX SWR_MIC5", "VA_TX_SWR_CLK", |
| 193 | "TX SWR_MIC6", "VA_TX_SWR_CLK", |
| 194 | "TX SWR_MIC7", "VA_TX_SWR_CLK", |
| 195 | "TX SWR_MIC8", "VA_TX_SWR_CLK", |
| 196 | "TX SWR_MIC9", "VA_TX_SWR_CLK", |
| 197 | "TX SWR_MIC10", "VA_TX_SWR_CLK", |
| 198 | "TX SWR_MIC11", "VA_TX_SWR_CLK", |
| 199 | "RX_TX DEC0_INP", "TX DEC0 MUX", |
| 200 | "RX_TX DEC1_INP", "TX DEC1 MUX", |
| 201 | "RX_TX DEC2_INP", "TX DEC2 MUX", |
| 202 | "RX_TX DEC3_INP", "TX DEC3 MUX", |
| 203 | "TX_AIF1 CAP", "VA_TX_SWR_CLK", |
| 204 | "TX_AIF2 CAP", "VA_TX_SWR_CLK", |
| 205 | "TX_AIF3 CAP", "VA_TX_SWR_CLK", |
| 206 | "VA DMIC0", "VA MIC BIAS3", |
| 207 | "VA DMIC1", "VA MIC BIAS3", |
| 208 | "VA DMIC2", "VA MIC BIAS1", |
| 209 | "VA DMIC3", "VA MIC BIAS1", |
| 210 | "VA MIC BIAS3", "Digital Mic0", |
| 211 | "VA MIC BIAS3", "Digital Mic1", |
| 212 | "VA MIC BIAS1", "Digital Mic2", |
| 213 | "VA MIC BIAS1", "Digital Mic3", |
| 214 | "VA SWR_MIC0", "ADC1_OUTPUT", |
| 215 | "VA SWR_MIC1", "ADC2_OUTPUT", |
| 216 | "VA SWR_MIC2", "DMIC1_OUTPUT", |
| 217 | "VA SWR_MIC5", "DMIC2_OUTPUT"; |
| 218 | qcom,msm-mbhc-hphl-swh = <1>; |
| 219 | qcom,msm-mbhc-gnd-swh = <1>; |
| 220 | qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; |
| 221 | qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; |
| 222 | |
| 223 | nvmem-cells = <&adsp_variant>; |
| 224 | nvmem-cell-names = "adsp_variant"; |
| 225 | asoc-codec = <&stub_codec>, <&bolero>; |
| 226 | asoc-codec-names = "msm-stub-codec.1", "bolero_codec"; |
| 227 | qcom,wsa-max-devs = <1>; |
| 228 | qcom,wsa-devs = <&wsa881x_i2c_e>; |
| 229 | qcom,wsa-aux-dev-prefix = "SpkrMono"; |
| 230 | qcom,codec-max-aux-devs = <1>; |
| 231 | qcom,codec-aux-devs = <&rouleur_codec>; |
| 232 | qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&bolero>, |
| 233 | <&lpi_tlmm>; |
| 234 | }; |
| 235 | |
| 236 | &qupv3_se1_i2c { |
| 237 | wsa881x_i2c_e: wsa881x-i2c-codec@e { |
| 238 | compatible = "qcom,wsa881x-i2c-codec"; |
| 239 | reg = <0x0e>; |
| 240 | clock-names = "wsa_mclk"; |
| 241 | clocks = <&wsa881x_analog_clk 0>; |
| 242 | qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>; |
| 243 | qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>; |
| 244 | }; |
| 245 | |
| 246 | wsa881x_i2c_44: wsa881x-i2c-codec@44 { |
| 247 | compatible = "qcom,wsa881x-i2c-codec"; |
| 248 | reg = <0x044>; |
| 249 | }; |
| 250 | }; |
| 251 | |
| 252 | &soc { |
| 253 | wsa881x_analog_reset_gpio: msm_cdc_pinctrl@106 { |
| 254 | compatible = "qcom,msm-cdc-pinctrl"; |
| 255 | pinctrl-names = "aud_active", "aud_sleep"; |
| 256 | pinctrl-0 = <&spkr_1_sd_n_active>; |
| 257 | pinctrl-1 = <&spkr_1_sd_n_sleep>; |
| 258 | }; |
| 259 | |
| 260 | wsa881x_analog_clk: wsa_ana_clk { |
| 261 | compatible = "qcom,audio-ref-clk"; |
| 262 | qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>; |
| 263 | qcom,codec-lpass-ext-clk-freq = <9600000>; |
| 264 | qcom,codec-lpass-clk-id = <0x301>; |
| 265 | #clock-cells = <1>; |
| 266 | }; |
| 267 | |
| 268 | clock_audio_rx_1: rx_core_clk { |
| 269 | compatible = "qcom,audio-ref-clk"; |
| 270 | qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>; |
| 271 | qcom,codec-lpass-ext-clk-freq = <22579200>; |
| 272 | qcom,codec-lpass-clk-id = <0x30E>; |
| 273 | #clock-cells = <1>; |
| 274 | }; |
| 275 | |
| 276 | clock_audio_rx_2: rx_npl_clk { |
| 277 | compatible = "qcom,audio-ref-clk"; |
| 278 | qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>; |
| 279 | qcom,codec-lpass-ext-clk-freq = <22579200>; |
| 280 | qcom,codec-lpass-clk-id = <0x30F>; |
| 281 | #clock-cells = <1>; |
| 282 | }; |
| 283 | |
| 284 | clock_audio_tx_1: tx_core_clk { |
| 285 | compatible = "qcom,audio-ref-clk"; |
| 286 | qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>; |
| 287 | qcom,codec-lpass-ext-clk-freq = <19200000>; |
| 288 | qcom,codec-lpass-clk-id = <0x30C>; |
| 289 | #clock-cells = <1>; |
| 290 | }; |
| 291 | |
| 292 | clock_audio_tx_2: tx_npl_clk { |
| 293 | compatible = "qcom,audio-ref-clk"; |
| 294 | qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>; |
| 295 | qcom,codec-lpass-ext-clk-freq = <19200000>; |
| 296 | qcom,codec-lpass-clk-id = <0x30D>; |
| 297 | #clock-cells = <1>; |
| 298 | }; |
| 299 | |
| 300 | clock_audio_va_1: va_core_clk { |
| 301 | compatible = "qcom,audio-ref-clk"; |
| 302 | qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>; |
| 303 | qcom,codec-lpass-ext-clk-freq = <19200000>; |
| 304 | qcom,codec-lpass-clk-id = <0x30B>; |
| 305 | #clock-cells = <1>; |
| 306 | }; |
| 307 | |
| 308 | clock_audio_va_2: va_npl_clk { |
| 309 | compatible = "qcom,audio-ref-clk"; |
| 310 | qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>; |
| 311 | qcom,codec-lpass-ext-clk-freq = <19200000>; |
| 312 | qcom,codec-lpass-clk-id = <0x310>; |
| 313 | #clock-cells = <1>; |
| 314 | }; |
| 315 | }; |
| 316 | |
| 317 | &va_cdc_dma_0_tx { |
| 318 | qcom,msm-dai-is-island-supported = <1>; |
| 319 | }; |