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Jason Robertsce082592010-05-13 15:57:33 +01001/*
2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20#include <linux/interrupt.h>
21#include <linux/delay.h>
22#include <linux/wait.h>
23#include <linux/mutex.h>
David Millerb8664b32010-08-04 22:57:51 -070024#include <linux/slab.h>
Jason Robertsce082592010-05-13 15:57:33 +010025#include <linux/pci.h>
26#include <linux/mtd/mtd.h>
27#include <linux/module.h>
28
29#include "denali.h"
30
31MODULE_LICENSE("GPL");
32
Chuanxiao5bac3ac2010-08-05 23:06:04 +080033/* We define a module parameter that allows the user to override
Jason Robertsce082592010-05-13 15:57:33 +010034 * the hardware and decide what timing mode should be used.
35 */
36#define NAND_DEFAULT_TIMINGS -1
37
38static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
39module_param(onfi_timing_mode, int, S_IRUGO);
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +080040MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
41 " -1 indicates use default timings");
Jason Robertsce082592010-05-13 15:57:33 +010042
43#define DENALI_NAND_NAME "denali-nand"
44
45/* We define a macro here that combines all interrupts this driver uses into
46 * a single constant value, for convenience. */
47#define DENALI_IRQ_ALL (INTR_STATUS0__DMA_CMD_COMP | \
48 INTR_STATUS0__ECC_TRANSACTION_DONE | \
49 INTR_STATUS0__ECC_ERR | \
50 INTR_STATUS0__PROGRAM_FAIL | \
51 INTR_STATUS0__LOAD_COMP | \
52 INTR_STATUS0__PROGRAM_COMP | \
53 INTR_STATUS0__TIME_OUT | \
54 INTR_STATUS0__ERASE_FAIL | \
55 INTR_STATUS0__RST_COMP | \
56 INTR_STATUS0__ERASE_COMP)
57
Chuanxiao5bac3ac2010-08-05 23:06:04 +080058/* indicates whether or not the internal value for the flash bank is
Chuanxiao Dongb292c342010-08-11 17:46:00 +080059 * valid or not */
Chuanxiao5bac3ac2010-08-05 23:06:04 +080060#define CHIP_SELECT_INVALID -1
Jason Robertsce082592010-05-13 15:57:33 +010061
62#define SUPPORT_8BITECC 1
63
Chuanxiao5bac3ac2010-08-05 23:06:04 +080064/* This macro divides two integers and rounds fractional values up
Jason Robertsce082592010-05-13 15:57:33 +010065 * to the nearest integer value. */
66#define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
67
68/* this macro allows us to convert from an MTD structure to our own
69 * device context (denali) structure.
70 */
71#define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
72
73/* These constants are defined by the driver to enable common driver
Chuanxiao Dongb292c342010-08-11 17:46:00 +080074 * configuration options. */
Jason Robertsce082592010-05-13 15:57:33 +010075#define SPARE_ACCESS 0x41
76#define MAIN_ACCESS 0x42
77#define MAIN_SPARE_ACCESS 0x43
78
79#define DENALI_READ 0
80#define DENALI_WRITE 0x100
81
82/* types of device accesses. We can issue commands and get status */
83#define COMMAND_CYCLE 0
84#define ADDR_CYCLE 1
85#define STATUS_CYCLE 2
86
Chuanxiao5bac3ac2010-08-05 23:06:04 +080087/* this is a helper macro that allows us to
Jason Robertsce082592010-05-13 15:57:33 +010088 * format the bank into the proper bits for the controller */
89#define BANK(x) ((x) << 24)
90
91/* List of platforms this NAND controller has be integrated into */
92static const struct pci_device_id denali_pci_ids[] = {
93 { PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 },
94 { PCI_VDEVICE(INTEL, 0x0809), INTEL_MRST },
95 { /* end: all zeroes */ }
96};
97
98
Chuanxiao5bac3ac2010-08-05 23:06:04 +080099/* these are static lookup tables that give us easy access to
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800100 * registers in the NAND controller.
Jason Robertsce082592010-05-13 15:57:33 +0100101 */
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800102static const uint32_t intr_status_addresses[4] = {INTR_STATUS0,
103 INTR_STATUS1,
104 INTR_STATUS2,
Jason Robertsce082592010-05-13 15:57:33 +0100105 INTR_STATUS3};
106
107static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0,
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800108 DEVICE_RESET__BANK1,
109 DEVICE_RESET__BANK2,
110 DEVICE_RESET__BANK3};
Jason Robertsce082592010-05-13 15:57:33 +0100111
112static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT,
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800113 INTR_STATUS1__TIME_OUT,
114 INTR_STATUS2__TIME_OUT,
115 INTR_STATUS3__TIME_OUT};
Jason Robertsce082592010-05-13 15:57:33 +0100116
117static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP,
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800118 INTR_STATUS1__RST_COMP,
119 INTR_STATUS2__RST_COMP,
120 INTR_STATUS3__RST_COMP};
Jason Robertsce082592010-05-13 15:57:33 +0100121
Jason Robertsce082592010-05-13 15:57:33 +0100122/* forward declarations */
123static void clear_interrupts(struct denali_nand_info *denali);
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800124static uint32_t wait_for_irq(struct denali_nand_info *denali,
125 uint32_t irq_mask);
126static void denali_irq_enable(struct denali_nand_info *denali,
127 uint32_t int_mask);
Jason Robertsce082592010-05-13 15:57:33 +0100128static uint32_t read_interrupt_status(struct denali_nand_info *denali);
129
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800130/* Certain operations for the denali NAND controller use
131 * an indexed mode to read/write data. The operation is
132 * performed by writing the address value of the command
133 * to the device memory followed by the data. This function
134 * abstracts this common operation.
Jason Robertsce082592010-05-13 15:57:33 +0100135*/
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800136static void index_addr(struct denali_nand_info *denali,
137 uint32_t address, uint32_t data)
Jason Robertsce082592010-05-13 15:57:33 +0100138{
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800139 iowrite32(address, denali->flash_mem);
140 iowrite32(data, denali->flash_mem + 0x10);
Jason Robertsce082592010-05-13 15:57:33 +0100141}
142
143/* Perform an indexed read of the device */
144static void index_addr_read_data(struct denali_nand_info *denali,
145 uint32_t address, uint32_t *pdata)
146{
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800147 iowrite32(address, denali->flash_mem);
Jason Robertsce082592010-05-13 15:57:33 +0100148 *pdata = ioread32(denali->flash_mem + 0x10);
149}
150
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800151/* We need to buffer some data for some of the NAND core routines.
Jason Robertsce082592010-05-13 15:57:33 +0100152 * The operations manage buffering that data. */
153static void reset_buf(struct denali_nand_info *denali)
154{
155 denali->buf.head = denali->buf.tail = 0;
156}
157
158static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
159{
160 BUG_ON(denali->buf.tail >= sizeof(denali->buf.buf));
161 denali->buf.buf[denali->buf.tail++] = byte;
162}
163
164/* reads the status of the device */
165static void read_status(struct denali_nand_info *denali)
166{
167 uint32_t cmd = 0x0;
168
169 /* initialize the data buffer to store status */
170 reset_buf(denali);
171
Chuanxiao Dongf0bc0c72010-08-11 17:14:59 +0800172 cmd = ioread32(denali->flash_reg + WRITE_PROTECT);
173 if (cmd)
174 write_byte_to_buf(denali, NAND_STATUS_WP);
175 else
176 write_byte_to_buf(denali, 0);
Jason Robertsce082592010-05-13 15:57:33 +0100177}
178
179/* resets a specific device connected to the core */
180static void reset_bank(struct denali_nand_info *denali)
181{
182 uint32_t irq_status = 0;
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800183 uint32_t irq_mask = reset_complete[denali->flash_bank] |
Jason Robertsce082592010-05-13 15:57:33 +0100184 operation_timeout[denali->flash_bank];
185 int bank = 0;
186
187 clear_interrupts(denali);
188
189 bank = device_reset_banks[denali->flash_bank];
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800190 iowrite32(bank, denali->flash_reg + DEVICE_RESET);
Jason Robertsce082592010-05-13 15:57:33 +0100191
192 irq_status = wait_for_irq(denali, irq_mask);
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800193
Jason Robertsce082592010-05-13 15:57:33 +0100194 if (irq_status & operation_timeout[denali->flash_bank])
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800195 dev_err(&denali->dev->dev, "reset bank failed.\n");
Jason Robertsce082592010-05-13 15:57:33 +0100196}
197
198/* Reset the flash controller */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800199static uint16_t denali_nand_reset(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +0100200{
201 uint32_t i;
202
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800203 dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n",
Jason Robertsce082592010-05-13 15:57:33 +0100204 __FILE__, __LINE__, __func__);
205
206 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++)
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800207 iowrite32(reset_complete[i] | operation_timeout[i],
Jason Robertsce082592010-05-13 15:57:33 +0100208 denali->flash_reg + intr_status_addresses[i]);
209
210 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) {
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800211 iowrite32(device_reset_banks[i],
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800212 denali->flash_reg + DEVICE_RESET);
213 while (!(ioread32(denali->flash_reg +
Chuanxiao Dong628bfd412010-08-11 17:53:29 +0800214 intr_status_addresses[i]) &
Jason Robertsce082592010-05-13 15:57:33 +0100215 (reset_complete[i] | operation_timeout[i])))
Chuanxiao Dong628bfd412010-08-11 17:53:29 +0800216 cpu_relax();
Jason Robertsce082592010-05-13 15:57:33 +0100217 if (ioread32(denali->flash_reg + intr_status_addresses[i]) &
218 operation_timeout[i])
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800219 dev_dbg(&denali->dev->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100220 "NAND Reset operation timed out on bank %d\n", i);
221 }
222
223 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++)
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800224 iowrite32(reset_complete[i] | operation_timeout[i],
Jason Robertsce082592010-05-13 15:57:33 +0100225 denali->flash_reg + intr_status_addresses[i]);
226
227 return PASS;
228}
229
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800230/* this routine calculates the ONFI timing values for a given mode and
231 * programs the clocking register accordingly. The mode is determined by
232 * the get_onfi_nand_para routine.
Jason Robertsce082592010-05-13 15:57:33 +0100233 */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800234static void nand_onfi_timing_set(struct denali_nand_info *denali,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800235 uint16_t mode)
Jason Robertsce082592010-05-13 15:57:33 +0100236{
237 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
238 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
239 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
240 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
241 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
242 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
243 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
244 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
245 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
246 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
247 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
248 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
249
250 uint16_t TclsRising = 1;
251 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
252 uint16_t dv_window = 0;
253 uint16_t en_lo, en_hi;
254 uint16_t acc_clks;
255 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
256
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800257 dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n",
Jason Robertsce082592010-05-13 15:57:33 +0100258 __FILE__, __LINE__, __func__);
259
260 en_lo = CEIL_DIV(Trp[mode], CLK_X);
261 en_hi = CEIL_DIV(Treh[mode], CLK_X);
262#if ONFI_BLOOM_TIME
263 if ((en_hi * CLK_X) < (Treh[mode] + 2))
264 en_hi++;
265#endif
266
267 if ((en_lo + en_hi) * CLK_X < Trc[mode])
268 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
269
270 if ((en_lo + en_hi) < CLK_MULTI)
271 en_lo += CLK_MULTI - en_lo - en_hi;
272
273 while (dv_window < 8) {
274 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
275
276 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
277
278 data_invalid =
279 data_invalid_rhoh <
280 data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;
281
282 dv_window = data_invalid - Trea[mode];
283
284 if (dv_window < 8)
285 en_lo++;
286 }
287
288 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
289
290 while (((acc_clks * CLK_X) - Trea[mode]) < 3)
291 acc_clks++;
292
293 if ((data_invalid - acc_clks * CLK_X) < 2)
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800294 dev_warn(&denali->dev->dev, "%s, Line %d: Warning!\n",
Jason Robertsce082592010-05-13 15:57:33 +0100295 __FILE__, __LINE__);
296
297 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
298 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
299 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
300 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
301 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
302 if (!TclsRising)
303 cs_cnt = CEIL_DIV(Tcs[mode], CLK_X);
304 if (cs_cnt == 0)
305 cs_cnt = 1;
306
307 if (Tcea[mode]) {
308 while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode])
309 cs_cnt++;
310 }
311
312#if MODE5_WORKAROUND
313 if (mode == 5)
314 acc_clks = 5;
315#endif
316
317 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
318 if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) &&
319 (ioread32(denali->flash_reg + DEVICE_ID) == 0x88))
320 acc_clks = 6;
321
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800322 iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
323 iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
324 iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
325 iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
326 iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
327 iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
328 iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
329 iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
Jason Robertsce082592010-05-13 15:57:33 +0100330}
331
Jason Robertsce082592010-05-13 15:57:33 +0100332/* queries the NAND device to see what ONFI modes it supports. */
333static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
334{
335 int i;
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800336 /* we needn't to do a reset here because driver has already
337 * reset all the banks before
338 * */
Jason Robertsce082592010-05-13 15:57:33 +0100339 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
340 ONFI_TIMING_MODE__VALUE))
341 return FAIL;
342
343 for (i = 5; i > 0; i--) {
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800344 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
345 (0x01 << i))
Jason Robertsce082592010-05-13 15:57:33 +0100346 break;
347 }
348
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800349 nand_onfi_timing_set(denali, i);
Jason Robertsce082592010-05-13 15:57:33 +0100350
351 /* By now, all the ONFI devices we know support the page cache */
352 /* rw feature. So here we enable the pipeline_rw_ahead feature */
353 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
354 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
355
356 return PASS;
357}
358
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800359static void get_samsung_nand_para(struct denali_nand_info *denali,
360 uint8_t device_id)
Jason Robertsce082592010-05-13 15:57:33 +0100361{
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800362 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
Jason Robertsce082592010-05-13 15:57:33 +0100363 /* Set timing register values according to datasheet */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800364 iowrite32(5, denali->flash_reg + ACC_CLKS);
365 iowrite32(20, denali->flash_reg + RE_2_WE);
366 iowrite32(12, denali->flash_reg + WE_2_RE);
367 iowrite32(14, denali->flash_reg + ADDR_2_DATA);
368 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
369 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
370 iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
Jason Robertsce082592010-05-13 15:57:33 +0100371 }
Jason Robertsce082592010-05-13 15:57:33 +0100372}
373
374static void get_toshiba_nand_para(struct denali_nand_info *denali)
375{
Jason Robertsce082592010-05-13 15:57:33 +0100376 uint32_t tmp;
377
378 /* Workaround to fix a controller bug which reports a wrong */
379 /* spare area size for some kind of Toshiba NAND device */
380 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
381 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800382 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
Jason Robertsce082592010-05-13 15:57:33 +0100383 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
384 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800385 iowrite32(tmp,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800386 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
Jason Robertsce082592010-05-13 15:57:33 +0100387#if SUPPORT_15BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800388 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100389#elif SUPPORT_8BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800390 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100391#endif
392 }
Jason Robertsce082592010-05-13 15:57:33 +0100393}
394
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800395static void get_hynix_nand_para(struct denali_nand_info *denali,
396 uint8_t device_id)
Jason Robertsce082592010-05-13 15:57:33 +0100397{
Jason Robertsce082592010-05-13 15:57:33 +0100398 uint32_t main_size, spare_size;
399
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800400 switch (device_id) {
Jason Robertsce082592010-05-13 15:57:33 +0100401 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
402 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800403 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
404 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
405 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800406 main_size = 4096 *
407 ioread32(denali->flash_reg + DEVICES_CONNECTED);
408 spare_size = 224 *
409 ioread32(denali->flash_reg + DEVICES_CONNECTED);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800410 iowrite32(main_size,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800411 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800412 iowrite32(spare_size,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800413 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800414 iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
Jason Robertsce082592010-05-13 15:57:33 +0100415#if SUPPORT_15BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800416 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100417#elif SUPPORT_8BITECC
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800418 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +0100419#endif
Jason Robertsce082592010-05-13 15:57:33 +0100420 break;
421 default:
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800422 dev_warn(&denali->dev->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100423 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
424 "Will use default parameter values instead.\n",
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800425 device_id);
Jason Robertsce082592010-05-13 15:57:33 +0100426 }
427}
428
429/* determines how many NAND chips are connected to the controller. Note for
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800430 * Intel CE4100 devices we don't support more than one device.
Jason Robertsce082592010-05-13 15:57:33 +0100431 */
432static void find_valid_banks(struct denali_nand_info *denali)
433{
434 uint32_t id[LLD_MAX_FLASH_BANKS];
435 int i;
436
437 denali->total_used_banks = 1;
438 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) {
439 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
440 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800441 index_addr_read_data(denali,
442 (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]);
Jason Robertsce082592010-05-13 15:57:33 +0100443
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800444 dev_dbg(&denali->dev->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100445 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
446
447 if (i == 0) {
448 if (!(id[i] & 0x0ff))
449 break; /* WTF? */
450 } else {
451 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
452 denali->total_used_banks++;
453 else
454 break;
455 }
456 }
457
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800458 if (denali->platform == INTEL_CE4100) {
Jason Robertsce082592010-05-13 15:57:33 +0100459 /* Platform limitations of the CE4100 device limit
460 * users to a single chip solution for NAND.
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800461 * Multichip support is not enabled.
462 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800463 if (denali->total_used_banks != 1) {
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800464 dev_err(&denali->dev->dev,
465 "Sorry, Intel CE4100 only supports "
Jason Robertsce082592010-05-13 15:57:33 +0100466 "a single NAND device.\n");
467 BUG();
468 }
469 }
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800470 dev_dbg(&denali->dev->dev,
Jason Robertsce082592010-05-13 15:57:33 +0100471 "denali->total_used_banks: %d\n", denali->total_used_banks);
472}
473
474static void detect_partition_feature(struct denali_nand_info *denali)
475{
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800476 /* For MRST platform, denali->fwblks represent the
477 * number of blocks firmware is taken,
478 * FW is in protect partition and MTD driver has no
479 * permission to access it. So let driver know how many
480 * blocks it can't touch.
481 * */
Jason Robertsce082592010-05-13 15:57:33 +0100482 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
483 if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) &
484 PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) {
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800485 denali->fwblks =
Jason Robertsce082592010-05-13 15:57:33 +0100486 ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) &
487 MIN_MAX_BANK_1__MIN_VALUE) *
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800488 denali->blksperchip)
Jason Robertsce082592010-05-13 15:57:33 +0100489 +
490 (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) &
491 MIN_BLK_ADDR_1__VALUE);
Chuanxiao.Dong66406522010-08-06 18:48:21 +0800492 } else
493 denali->fwblks = SPECTRA_START_BLOCK;
494 } else
495 denali->fwblks = SPECTRA_START_BLOCK;
Jason Robertsce082592010-05-13 15:57:33 +0100496}
497
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800498static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
Jason Robertsce082592010-05-13 15:57:33 +0100499{
500 uint16_t status = PASS;
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800501 uint32_t id_bytes[5], addr;
502 uint8_t i, maf_id, device_id;
Jason Robertsce082592010-05-13 15:57:33 +0100503
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800504 dev_dbg(&denali->dev->dev,
505 "%s, Line %d, Function: %s\n",
506 __FILE__, __LINE__, __func__);
Jason Robertsce082592010-05-13 15:57:33 +0100507
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800508 /* Use read id method to get device ID and other
509 * params. For some NAND chips, controller can't
510 * report the correct device ID by reading from
511 * DEVICE_ID register
512 * */
513 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
514 index_addr(denali, (uint32_t)addr | 0, 0x90);
515 index_addr(denali, (uint32_t)addr | 1, 0);
516 for (i = 0; i < 5; i++)
517 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
518 maf_id = id_bytes[0];
519 device_id = id_bytes[1];
Jason Robertsce082592010-05-13 15:57:33 +0100520
521 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
522 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
523 if (FAIL == get_onfi_nand_para(denali))
524 return FAIL;
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800525 } else if (maf_id == 0xEC) { /* Samsung NAND */
Chuanxiao Dong4c03bbd2010-08-06 15:45:19 +0800526 get_samsung_nand_para(denali, device_id);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800527 } else if (maf_id == 0x98) { /* Toshiba NAND */
Jason Robertsce082592010-05-13 15:57:33 +0100528 get_toshiba_nand_para(denali);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +0800529 } else if (maf_id == 0xAD) { /* Hynix NAND */
530 get_hynix_nand_para(denali, device_id);
Jason Robertsce082592010-05-13 15:57:33 +0100531 }
532
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800533 dev_info(&denali->dev->dev,
534 "Dump timing register values:"
535 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
536 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
Jason Robertsce082592010-05-13 15:57:33 +0100537 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
538 ioread32(denali->flash_reg + ACC_CLKS),
539 ioread32(denali->flash_reg + RE_2_WE),
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800540 ioread32(denali->flash_reg + RE_2_RE),
Jason Robertsce082592010-05-13 15:57:33 +0100541 ioread32(denali->flash_reg + WE_2_RE),
542 ioread32(denali->flash_reg + ADDR_2_DATA),
543 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
544 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
545 ioread32(denali->flash_reg + CS_SETUP_CNT));
546
Jason Robertsce082592010-05-13 15:57:33 +0100547 find_valid_banks(denali);
548
549 detect_partition_feature(denali);
550
Jason Robertsce082592010-05-13 15:57:33 +0100551 /* If the user specified to override the default timings
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800552 * with a specific ONFI mode, we apply those changes here.
Jason Robertsce082592010-05-13 15:57:33 +0100553 */
554 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800555 nand_onfi_timing_set(denali, onfi_timing_mode);
Jason Robertsce082592010-05-13 15:57:33 +0100556
557 return status;
558}
559
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800560static void denali_set_intr_modes(struct denali_nand_info *denali,
Jason Robertsce082592010-05-13 15:57:33 +0100561 uint16_t INT_ENABLE)
562{
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800563 dev_dbg(&denali->dev->dev, "%s, Line %d, Function: %s\n",
Jason Robertsce082592010-05-13 15:57:33 +0100564 __FILE__, __LINE__, __func__);
565
566 if (INT_ENABLE)
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800567 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
Jason Robertsce082592010-05-13 15:57:33 +0100568 else
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800569 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
Jason Robertsce082592010-05-13 15:57:33 +0100570}
571
572/* validation function to verify that the controlling software is making
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800573 * a valid request
Jason Robertsce082592010-05-13 15:57:33 +0100574 */
575static inline bool is_flash_bank_valid(int flash_bank)
576{
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800577 return (flash_bank >= 0 && flash_bank < 4);
Jason Robertsce082592010-05-13 15:57:33 +0100578}
579
580static void denali_irq_init(struct denali_nand_info *denali)
581{
582 uint32_t int_mask = 0;
583
584 /* Disable global interrupts */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800585 denali_set_intr_modes(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +0100586
587 int_mask = DENALI_IRQ_ALL;
588
589 /* Clear all status bits */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800590 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS0);
591 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS1);
592 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS2);
593 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS3);
Jason Robertsce082592010-05-13 15:57:33 +0100594
595 denali_irq_enable(denali, int_mask);
596}
597
598static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
599{
Chuanxiao Dongeda936e2010-07-27 14:17:37 +0800600 denali_set_intr_modes(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +0100601 free_irq(irqnum, denali);
602}
603
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800604static void denali_irq_enable(struct denali_nand_info *denali,
605 uint32_t int_mask)
Jason Robertsce082592010-05-13 15:57:33 +0100606{
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800607 iowrite32(int_mask, denali->flash_reg + INTR_EN0);
608 iowrite32(int_mask, denali->flash_reg + INTR_EN1);
609 iowrite32(int_mask, denali->flash_reg + INTR_EN2);
610 iowrite32(int_mask, denali->flash_reg + INTR_EN3);
Jason Robertsce082592010-05-13 15:57:33 +0100611}
612
613/* This function only returns when an interrupt that this driver cares about
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800614 * occurs. This is to reduce the overhead of servicing interrupts
Jason Robertsce082592010-05-13 15:57:33 +0100615 */
616static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
617{
Chuanxiao Donga99d1792010-07-27 11:32:21 +0800618 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
Jason Robertsce082592010-05-13 15:57:33 +0100619}
620
621/* Interrupts are cleared by writing a 1 to the appropriate status bit */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800622static inline void clear_interrupt(struct denali_nand_info *denali,
623 uint32_t irq_mask)
Jason Robertsce082592010-05-13 15:57:33 +0100624{
625 uint32_t intr_status_reg = 0;
626
627 intr_status_reg = intr_status_addresses[denali->flash_bank];
628
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800629 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
Jason Robertsce082592010-05-13 15:57:33 +0100630}
631
632static void clear_interrupts(struct denali_nand_info *denali)
633{
634 uint32_t status = 0x0;
635 spin_lock_irq(&denali->irq_lock);
636
637 status = read_interrupt_status(denali);
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800638 clear_interrupt(denali, status);
Jason Robertsce082592010-05-13 15:57:33 +0100639
Jason Robertsce082592010-05-13 15:57:33 +0100640 denali->irq_status = 0x0;
641 spin_unlock_irq(&denali->irq_lock);
642}
643
644static uint32_t read_interrupt_status(struct denali_nand_info *denali)
645{
646 uint32_t intr_status_reg = 0;
647
648 intr_status_reg = intr_status_addresses[denali->flash_bank];
649
650 return ioread32(denali->flash_reg + intr_status_reg);
651}
652
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800653/* This is the interrupt service routine. It handles all interrupts
654 * sent to this device. Note that on CE4100, this is a shared
655 * interrupt.
Jason Robertsce082592010-05-13 15:57:33 +0100656 */
657static irqreturn_t denali_isr(int irq, void *dev_id)
658{
659 struct denali_nand_info *denali = dev_id;
660 uint32_t irq_status = 0x0;
661 irqreturn_t result = IRQ_NONE;
662
663 spin_lock(&denali->irq_lock);
664
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800665 /* check to see if a valid NAND chip has
666 * been selected.
Jason Robertsce082592010-05-13 15:57:33 +0100667 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800668 if (is_flash_bank_valid(denali->flash_bank)) {
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800669 /* check to see if controller generated
Jason Robertsce082592010-05-13 15:57:33 +0100670 * the interrupt, since this is a shared interrupt */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800671 irq_status = denali_irq_detected(denali);
672 if (irq_status != 0) {
Jason Robertsce082592010-05-13 15:57:33 +0100673 /* handle interrupt */
674 /* first acknowledge it */
675 clear_interrupt(denali, irq_status);
676 /* store the status in the device context for someone
677 to read */
678 denali->irq_status |= irq_status;
679 /* notify anyone who cares that it happened */
680 complete(&denali->complete);
681 /* tell the OS that we've handled this */
682 result = IRQ_HANDLED;
683 }
684 }
685 spin_unlock(&denali->irq_lock);
686 return result;
687}
688#define BANK(x) ((x) << 24)
689
690static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
691{
692 unsigned long comp_res = 0;
693 uint32_t intr_status = 0;
694 bool retry = false;
695 unsigned long timeout = msecs_to_jiffies(1000);
696
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800697 do {
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800698 comp_res =
699 wait_for_completion_timeout(&denali->complete, timeout);
Jason Robertsce082592010-05-13 15:57:33 +0100700 spin_lock_irq(&denali->irq_lock);
701 intr_status = denali->irq_status;
702
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800703 if (intr_status & irq_mask) {
Jason Robertsce082592010-05-13 15:57:33 +0100704 denali->irq_status &= ~irq_mask;
705 spin_unlock_irq(&denali->irq_lock);
Jason Robertsce082592010-05-13 15:57:33 +0100706 /* our interrupt was detected */
707 break;
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800708 } else {
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800709 /* these are not the interrupts you are looking for -
710 * need to wait again */
Jason Robertsce082592010-05-13 15:57:33 +0100711 spin_unlock_irq(&denali->irq_lock);
Jason Robertsce082592010-05-13 15:57:33 +0100712 retry = true;
713 }
714 } while (comp_res != 0);
715
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800716 if (comp_res == 0) {
Jason Robertsce082592010-05-13 15:57:33 +0100717 /* timeout */
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800718 printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n",
719 intr_status, irq_mask);
Jason Robertsce082592010-05-13 15:57:33 +0100720
721 intr_status = 0;
722 }
723 return intr_status;
724}
725
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800726/* This helper function setups the registers for ECC and whether or not
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300727 * the spare area will be transferred. */
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800728static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
Jason Robertsce082592010-05-13 15:57:33 +0100729 bool transfer_spare)
730{
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800731 int ecc_en_flag = 0, transfer_spare_flag = 0;
Jason Robertsce082592010-05-13 15:57:33 +0100732
733 /* set ECC, transfer spare bits if needed */
734 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
735 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
736
737 /* Enable spare area/ECC per user's request. */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800738 iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
739 iowrite32(transfer_spare_flag,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800740 denali->flash_reg + TRANSFER_SPARE_REG);
Jason Robertsce082592010-05-13 15:57:33 +0100741}
742
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800743/* sends a pipeline command operation to the controller. See the Denali NAND
Chuanxiao Dongb292c342010-08-11 17:46:00 +0800744 * controller's user guide for more information (section 4.2.3.6).
Jason Robertsce082592010-05-13 15:57:33 +0100745 */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800746static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
747 bool ecc_en,
748 bool transfer_spare,
749 int access_type,
750 int op)
Jason Robertsce082592010-05-13 15:57:33 +0100751{
752 int status = PASS;
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800753 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0,
Jason Robertsce082592010-05-13 15:57:33 +0100754 irq_mask = 0;
755
Chuanxiao Donga99d1792010-07-27 11:32:21 +0800756 if (op == DENALI_READ)
757 irq_mask = INTR_STATUS0__LOAD_COMP;
758 else if (op == DENALI_WRITE)
759 irq_mask = 0;
760 else
761 BUG();
Jason Robertsce082592010-05-13 15:57:33 +0100762
763 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
764
Jason Robertsce082592010-05-13 15:57:33 +0100765 /* clear interrupts */
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800766 clear_interrupts(denali);
Jason Robertsce082592010-05-13 15:57:33 +0100767
768 addr = BANK(denali->flash_bank) | denali->page;
769
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800770 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800771 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800772 iowrite32(cmd, denali->flash_mem);
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800773 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
Jason Robertsce082592010-05-13 15:57:33 +0100774 /* read spare area */
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800775 cmd = MODE_10 | addr;
Jason Robertsce082592010-05-13 15:57:33 +0100776 index_addr(denali, (uint32_t)cmd, access_type);
777
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800778 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800779 iowrite32(cmd, denali->flash_mem);
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800780 } else if (op == DENALI_READ) {
Jason Robertsce082592010-05-13 15:57:33 +0100781 /* setup page read request for access type */
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800782 cmd = MODE_10 | addr;
Jason Robertsce082592010-05-13 15:57:33 +0100783 index_addr(denali, (uint32_t)cmd, access_type);
784
785 /* page 33 of the NAND controller spec indicates we should not
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800786 use the pipeline commands in Spare area only mode. So we
Jason Robertsce082592010-05-13 15:57:33 +0100787 don't.
788 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800789 if (access_type == SPARE_ACCESS) {
Jason Robertsce082592010-05-13 15:57:33 +0100790 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800791 iowrite32(cmd, denali->flash_mem);
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800792 } else {
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800793 index_addr(denali, (uint32_t)cmd,
794 0x2000 | op | page_count);
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800795
796 /* wait for command to be accepted
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800797 * can always use status0 bit as the
798 * mask is identical for each
Jason Robertsce082592010-05-13 15:57:33 +0100799 * bank. */
800 irq_status = wait_for_irq(denali, irq_mask);
801
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800802 if (irq_status == 0) {
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800803 dev_err(&denali->dev->dev,
804 "cmd, page, addr on timeout "
805 "(0x%x, 0x%x, 0x%x)\n",
806 cmd, denali->page, addr);
Jason Robertsce082592010-05-13 15:57:33 +0100807 status = FAIL;
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800808 } else {
Jason Robertsce082592010-05-13 15:57:33 +0100809 cmd = MODE_01 | addr;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800810 iowrite32(cmd, denali->flash_mem);
Jason Robertsce082592010-05-13 15:57:33 +0100811 }
812 }
813 }
814 return status;
815}
816
817/* helper function that simply writes a buffer to the flash */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800818static int write_data_to_flash_mem(struct denali_nand_info *denali,
819 const uint8_t *buf,
820 int len)
Jason Robertsce082592010-05-13 15:57:33 +0100821{
822 uint32_t i = 0, *buf32;
823
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800824 /* verify that the len is a multiple of 4. see comment in
825 * read_data_from_flash_mem() */
Jason Robertsce082592010-05-13 15:57:33 +0100826 BUG_ON((len % 4) != 0);
827
828 /* write the data to the flash memory */
829 buf32 = (uint32_t *)buf;
830 for (i = 0; i < len / 4; i++)
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +0800831 iowrite32(*buf32++, denali->flash_mem + 0x10);
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800832 return i*4; /* intent is to return the number of bytes read */
Jason Robertsce082592010-05-13 15:57:33 +0100833}
834
835/* helper function that simply reads a buffer from the flash */
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800836static int read_data_from_flash_mem(struct denali_nand_info *denali,
837 uint8_t *buf,
838 int len)
Jason Robertsce082592010-05-13 15:57:33 +0100839{
840 uint32_t i = 0, *buf32;
841
842 /* we assume that len will be a multiple of 4, if not
843 * it would be nice to know about it ASAP rather than
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800844 * have random failures...
845 * This assumption is based on the fact that this
846 * function is designed to be used to read flash pages,
Jason Robertsce082592010-05-13 15:57:33 +0100847 * which are typically multiples of 4...
848 */
849
850 BUG_ON((len % 4) != 0);
851
852 /* transfer the data from the flash */
853 buf32 = (uint32_t *)buf;
854 for (i = 0; i < len / 4; i++)
Jason Robertsce082592010-05-13 15:57:33 +0100855 *buf32++ = ioread32(denali->flash_mem + 0x10);
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800856 return i*4; /* intent is to return the number of bytes read */
Jason Robertsce082592010-05-13 15:57:33 +0100857}
858
859/* writes OOB data to the device */
860static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
861{
862 struct denali_nand_info *denali = mtd_to_denali(mtd);
863 uint32_t irq_status = 0;
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800864 uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP |
Jason Robertsce082592010-05-13 15:57:33 +0100865 INTR_STATUS0__PROGRAM_FAIL;
866 int status = 0;
867
868 denali->page = page;
869
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800870 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800871 DENALI_WRITE) == PASS) {
Jason Robertsce082592010-05-13 15:57:33 +0100872 write_data_to_flash_mem(denali, buf, mtd->oobsize);
873
Jason Robertsce082592010-05-13 15:57:33 +0100874 /* wait for operation to complete */
875 irq_status = wait_for_irq(denali, irq_mask);
876
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800877 if (irq_status == 0) {
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800878 dev_err(&denali->dev->dev, "OOB write failed\n");
Jason Robertsce082592010-05-13 15:57:33 +0100879 status = -EIO;
880 }
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800881 } else {
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800882 dev_err(&denali->dev->dev, "unable to send pipeline command\n");
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800883 status = -EIO;
Jason Robertsce082592010-05-13 15:57:33 +0100884 }
885 return status;
886}
887
888/* reads OOB data from the device */
889static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
890{
891 struct denali_nand_info *denali = mtd_to_denali(mtd);
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800892 uint32_t irq_mask = INTR_STATUS0__LOAD_COMP,
893 irq_status = 0, addr = 0x0, cmd = 0x0;
Jason Robertsce082592010-05-13 15:57:33 +0100894
895 denali->page = page;
896
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800897 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800898 DENALI_READ) == PASS) {
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800899 read_data_from_flash_mem(denali, buf, mtd->oobsize);
Jason Robertsce082592010-05-13 15:57:33 +0100900
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800901 /* wait for command to be accepted
Jason Robertsce082592010-05-13 15:57:33 +0100902 * can always use status0 bit as the mask is identical for each
903 * bank. */
904 irq_status = wait_for_irq(denali, irq_mask);
905
906 if (irq_status == 0)
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +0800907 dev_err(&denali->dev->dev, "page on OOB timeout %d\n",
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800908 denali->page);
Jason Robertsce082592010-05-13 15:57:33 +0100909
910 /* We set the device back to MAIN_ACCESS here as I observed
911 * instability with the controller if you do a block erase
912 * and the last transaction was a SPARE_ACCESS. Block erase
913 * is reliable (according to the MTD test infrastructure)
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800914 * if you are in MAIN_ACCESS.
Jason Robertsce082592010-05-13 15:57:33 +0100915 */
916 addr = BANK(denali->flash_bank) | denali->page;
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800917 cmd = MODE_10 | addr;
Jason Robertsce082592010-05-13 15:57:33 +0100918 index_addr(denali, (uint32_t)cmd, MAIN_ACCESS);
Jason Robertsce082592010-05-13 15:57:33 +0100919 }
920}
921
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800922/* this function examines buffers to see if they contain data that
Jason Robertsce082592010-05-13 15:57:33 +0100923 * indicate that the buffer is part of an erased region of flash.
924 */
925bool is_erased(uint8_t *buf, int len)
926{
927 int i = 0;
928 for (i = 0; i < len; i++)
Jason Robertsce082592010-05-13 15:57:33 +0100929 if (buf[i] != 0xFF)
Jason Robertsce082592010-05-13 15:57:33 +0100930 return false;
Jason Robertsce082592010-05-13 15:57:33 +0100931 return true;
932}
933#define ECC_SECTOR_SIZE 512
934
935#define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
936#define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
937#define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800938#define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
939#define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
Jason Robertsce082592010-05-13 15:57:33 +0100940#define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
941
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800942static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800943 uint32_t irq_status)
Jason Robertsce082592010-05-13 15:57:33 +0100944{
945 bool check_erased_page = false;
946
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800947 if (irq_status & INTR_STATUS0__ECC_ERR) {
Jason Robertsce082592010-05-13 15:57:33 +0100948 /* read the ECC errors. we'll ignore them for now */
949 uint32_t err_address = 0, err_correction_info = 0;
950 uint32_t err_byte = 0, err_sector = 0, err_device = 0;
951 uint32_t err_correction_value = 0;
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800952 denali_set_intr_modes(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +0100953
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800954 do {
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800955 err_address = ioread32(denali->flash_reg +
Jason Robertsce082592010-05-13 15:57:33 +0100956 ECC_ERROR_ADDRESS);
957 err_sector = ECC_SECTOR(err_address);
958 err_byte = ECC_BYTE(err_address);
959
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800960 err_correction_info = ioread32(denali->flash_reg +
Jason Robertsce082592010-05-13 15:57:33 +0100961 ERR_CORRECTION_INFO);
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800962 err_correction_value =
Jason Robertsce082592010-05-13 15:57:33 +0100963 ECC_CORRECTION_VALUE(err_correction_info);
964 err_device = ECC_ERR_DEVICE(err_correction_info);
965
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800966 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800967 /* If err_byte is larger than ECC_SECTOR_SIZE,
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300968 * means error happened in OOB, so we ignore
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800969 * it. It's no need for us to correct it
970 * err_device is represented the NAND error
971 * bits are happened in if there are more
972 * than one NAND connected.
973 * */
974 if (err_byte < ECC_SECTOR_SIZE) {
975 int offset;
976 offset = (err_sector *
977 ECC_SECTOR_SIZE +
978 err_byte) *
979 denali->devnum +
980 err_device;
Jason Robertsce082592010-05-13 15:57:33 +0100981 /* correct the ECC error */
982 buf[offset] ^= err_correction_value;
983 denali->mtd.ecc_stats.corrected++;
Jason Robertsce082592010-05-13 15:57:33 +0100984 }
Chuanxiao Dong345b1d32010-07-27 10:41:53 +0800985 } else {
Chuanxiao5bac3ac2010-08-05 23:06:04 +0800986 /* if the error is not correctable, need to
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +0800987 * look at the page to see if it is an erased
988 * page. if so, then it's not a real ECC error
989 * */
Jason Robertsce082592010-05-13 15:57:33 +0100990 check_erased_page = true;
991 }
Jason Robertsce082592010-05-13 15:57:33 +0100992 } while (!ECC_LAST_ERR(err_correction_info));
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +0800993 /* Once handle all ecc errors, controller will triger
994 * a ECC_TRANSACTION_DONE interrupt, so here just wait
995 * for a while for this interrupt
996 * */
997 while (!(read_interrupt_status(denali) &
998 INTR_STATUS0__ECC_TRANSACTION_DONE))
999 cpu_relax();
1000 clear_interrupts(denali);
1001 denali_set_intr_modes(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001002 }
1003 return check_erased_page;
1004}
1005
1006/* programs the controller to either enable/disable DMA transfers */
David Woodhouseaadff492010-05-13 16:12:43 +01001007static void denali_enable_dma(struct denali_nand_info *denali, bool en)
Jason Robertsce082592010-05-13 15:57:33 +01001008{
1009 uint32_t reg_val = 0x0;
1010
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001011 if (en)
1012 reg_val = DMA_ENABLE__FLAG;
Jason Robertsce082592010-05-13 15:57:33 +01001013
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001014 iowrite32(reg_val, denali->flash_reg + DMA_ENABLE);
Jason Robertsce082592010-05-13 15:57:33 +01001015 ioread32(denali->flash_reg + DMA_ENABLE);
1016}
1017
1018/* setups the HW to perform the data DMA */
David Woodhouseaadff492010-05-13 16:12:43 +01001019static void denali_setup_dma(struct denali_nand_info *denali, int op)
Jason Robertsce082592010-05-13 15:57:33 +01001020{
1021 uint32_t mode = 0x0;
1022 const int page_count = 1;
1023 dma_addr_t addr = denali->buf.dma_buf;
1024
1025 mode = MODE_10 | BANK(denali->flash_bank);
1026
1027 /* DMA is a four step process */
1028
1029 /* 1. setup transfer type and # of pages */
1030 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1031
1032 /* 2. set memory high address bits 23:8 */
1033 index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200);
1034
1035 /* 3. set memory low address bits 23:8 */
1036 index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300);
1037
1038 /* 4. interrupt when complete, burst len = 64 bytes*/
1039 index_addr(denali, mode | 0x14000, 0x2400);
1040}
1041
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001042/* writes a page. user specifies type, and this function handles the
Chuanxiao Dongb292c342010-08-11 17:46:00 +08001043 * configuration details. */
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001044static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
Jason Robertsce082592010-05-13 15:57:33 +01001045 const uint8_t *buf, bool raw_xfer)
1046{
1047 struct denali_nand_info *denali = mtd_to_denali(mtd);
1048 struct pci_dev *pci_dev = denali->dev;
1049
1050 dma_addr_t addr = denali->buf.dma_buf;
1051 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1052
1053 uint32_t irq_status = 0;
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001054 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP |
Jason Robertsce082592010-05-13 15:57:33 +01001055 INTR_STATUS0__PROGRAM_FAIL;
1056
1057 /* if it is a raw xfer, we want to disable ecc, and send
1058 * the spare area.
1059 * !raw_xfer - enable ecc
1060 * raw_xfer - transfer spare
1061 */
1062 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1063
1064 /* copy buffer into DMA buffer */
1065 memcpy(denali->buf.buf, buf, mtd->writesize);
1066
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001067 if (raw_xfer) {
Jason Robertsce082592010-05-13 15:57:33 +01001068 /* transfer the data to the spare area */
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001069 memcpy(denali->buf.buf + mtd->writesize,
1070 chip->oob_poi,
1071 mtd->oobsize);
Jason Robertsce082592010-05-13 15:57:33 +01001072 }
1073
1074 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE);
1075
1076 clear_interrupts(denali);
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001077 denali_enable_dma(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001078
David Woodhouseaadff492010-05-13 16:12:43 +01001079 denali_setup_dma(denali, DENALI_WRITE);
Jason Robertsce082592010-05-13 15:57:33 +01001080
1081 /* wait for operation to complete */
1082 irq_status = wait_for_irq(denali, irq_mask);
1083
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001084 if (irq_status == 0) {
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +08001085 dev_err(&denali->dev->dev,
1086 "timeout on write_page (type = %d)\n",
1087 raw_xfer);
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001088 denali->status =
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +08001089 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ?
1090 NAND_STATUS_FAIL : PASS;
Jason Robertsce082592010-05-13 15:57:33 +01001091 }
1092
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001093 denali_enable_dma(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +01001094 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE);
1095}
1096
1097/* NAND core entry points */
1098
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001099/* this is the callback that the NAND core calls to write a page. Since
Chuanxiao Dongb292c342010-08-11 17:46:00 +08001100 * writing a page with ECC or without is similar, all the work is done
1101 * by write_page above.
1102 * */
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001103static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
Jason Robertsce082592010-05-13 15:57:33 +01001104 const uint8_t *buf)
1105{
1106 /* for regular page writes, we let HW handle all the ECC
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001107 * data written to the device. */
Jason Robertsce082592010-05-13 15:57:33 +01001108 write_page(mtd, chip, buf, false);
1109}
1110
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001111/* This is the callback that the NAND core calls to write a page without ECC.
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001112 * raw access is similar to ECC page writes, so all the work is done in the
Chuanxiao Dongb292c342010-08-11 17:46:00 +08001113 * write_page() function above.
Jason Robertsce082592010-05-13 15:57:33 +01001114 */
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001115static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
Jason Robertsce082592010-05-13 15:57:33 +01001116 const uint8_t *buf)
1117{
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001118 /* for raw page writes, we want to disable ECC and simply write
Jason Robertsce082592010-05-13 15:57:33 +01001119 whatever data is in the buffer. */
1120 write_page(mtd, chip, buf, true);
1121}
1122
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001123static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
Jason Robertsce082592010-05-13 15:57:33 +01001124 int page)
1125{
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001126 return write_oob_data(mtd, chip->oob_poi, page);
Jason Robertsce082592010-05-13 15:57:33 +01001127}
1128
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001129static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
Jason Robertsce082592010-05-13 15:57:33 +01001130 int page, int sndcmd)
1131{
1132 read_oob_data(mtd, chip->oob_poi, page);
1133
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001134 return 0; /* notify NAND core to send command to
1135 NAND device. */
Jason Robertsce082592010-05-13 15:57:33 +01001136}
1137
1138static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1139 uint8_t *buf, int page)
1140{
1141 struct denali_nand_info *denali = mtd_to_denali(mtd);
1142 struct pci_dev *pci_dev = denali->dev;
1143
1144 dma_addr_t addr = denali->buf.dma_buf;
1145 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1146
1147 uint32_t irq_status = 0;
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001148 uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE |
Jason Robertsce082592010-05-13 15:57:33 +01001149 INTR_STATUS0__ECC_ERR;
1150 bool check_erased_page = false;
1151
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001152 if (page != denali->page) {
1153 dev_err(&denali->dev->dev, "IN %s: page %d is not"
1154 " equal to denali->page %d, investigate!!",
1155 __func__, page, denali->page);
1156 BUG();
1157 }
1158
Jason Robertsce082592010-05-13 15:57:33 +01001159 setup_ecc_for_xfer(denali, true, false);
1160
David Woodhouseaadff492010-05-13 16:12:43 +01001161 denali_enable_dma(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001162 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1163
1164 clear_interrupts(denali);
David Woodhouseaadff492010-05-13 16:12:43 +01001165 denali_setup_dma(denali, DENALI_READ);
Jason Robertsce082592010-05-13 15:57:33 +01001166
1167 /* wait for operation to complete */
1168 irq_status = wait_for_irq(denali, irq_mask);
1169
1170 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1171
1172 memcpy(buf, denali->buf.buf, mtd->writesize);
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001173
Chuanxiao Dong8ae61eb2010-08-10 00:07:01 +08001174 check_erased_page = handle_ecc(denali, buf, irq_status);
David Woodhouseaadff492010-05-13 16:12:43 +01001175 denali_enable_dma(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +01001176
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001177 if (check_erased_page) {
Jason Robertsce082592010-05-13 15:57:33 +01001178 read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
1179
1180 /* check ECC failures that may have occurred on erased pages */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001181 if (check_erased_page) {
Jason Robertsce082592010-05-13 15:57:33 +01001182 if (!is_erased(buf, denali->mtd.writesize))
Jason Robertsce082592010-05-13 15:57:33 +01001183 denali->mtd.ecc_stats.failed++;
Jason Robertsce082592010-05-13 15:57:33 +01001184 if (!is_erased(buf, denali->mtd.oobsize))
Jason Robertsce082592010-05-13 15:57:33 +01001185 denali->mtd.ecc_stats.failed++;
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001186 }
Jason Robertsce082592010-05-13 15:57:33 +01001187 }
1188 return 0;
1189}
1190
1191static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1192 uint8_t *buf, int page)
1193{
1194 struct denali_nand_info *denali = mtd_to_denali(mtd);
1195 struct pci_dev *pci_dev = denali->dev;
1196
1197 dma_addr_t addr = denali->buf.dma_buf;
1198 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1199
1200 uint32_t irq_status = 0;
1201 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP;
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001202
Chuanxiao Dong7d8a26f2010-08-11 18:19:23 +08001203 if (page != denali->page) {
1204 dev_err(&denali->dev->dev, "IN %s: page %d is not"
1205 " equal to denali->page %d, investigate!!",
1206 __func__, page, denali->page);
1207 BUG();
1208 }
1209
Jason Robertsce082592010-05-13 15:57:33 +01001210 setup_ecc_for_xfer(denali, false, true);
David Woodhouseaadff492010-05-13 16:12:43 +01001211 denali_enable_dma(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001212
1213 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1214
1215 clear_interrupts(denali);
David Woodhouseaadff492010-05-13 16:12:43 +01001216 denali_setup_dma(denali, DENALI_READ);
Jason Robertsce082592010-05-13 15:57:33 +01001217
1218 /* wait for operation to complete */
1219 irq_status = wait_for_irq(denali, irq_mask);
1220
1221 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1222
David Woodhouseaadff492010-05-13 16:12:43 +01001223 denali_enable_dma(denali, false);
Jason Robertsce082592010-05-13 15:57:33 +01001224
1225 memcpy(buf, denali->buf.buf, mtd->writesize);
1226 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1227
1228 return 0;
1229}
1230
1231static uint8_t denali_read_byte(struct mtd_info *mtd)
1232{
1233 struct denali_nand_info *denali = mtd_to_denali(mtd);
1234 uint8_t result = 0xff;
1235
1236 if (denali->buf.head < denali->buf.tail)
Jason Robertsce082592010-05-13 15:57:33 +01001237 result = denali->buf.buf[denali->buf.head++];
Jason Robertsce082592010-05-13 15:57:33 +01001238
Jason Robertsce082592010-05-13 15:57:33 +01001239 return result;
1240}
1241
1242static void denali_select_chip(struct mtd_info *mtd, int chip)
1243{
1244 struct denali_nand_info *denali = mtd_to_denali(mtd);
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +08001245
Jason Robertsce082592010-05-13 15:57:33 +01001246 spin_lock_irq(&denali->irq_lock);
1247 denali->flash_bank = chip;
1248 spin_unlock_irq(&denali->irq_lock);
1249}
1250
1251static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1252{
1253 struct denali_nand_info *denali = mtd_to_denali(mtd);
1254 int status = denali->status;
1255 denali->status = 0;
1256
Jason Robertsce082592010-05-13 15:57:33 +01001257 return status;
1258}
1259
1260static void denali_erase(struct mtd_info *mtd, int page)
1261{
1262 struct denali_nand_info *denali = mtd_to_denali(mtd);
1263
1264 uint32_t cmd = 0x0, irq_status = 0;
1265
Jason Robertsce082592010-05-13 15:57:33 +01001266 /* clear interrupts */
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001267 clear_interrupts(denali);
Jason Robertsce082592010-05-13 15:57:33 +01001268
1269 /* setup page read request for access type */
1270 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1271 index_addr(denali, (uint32_t)cmd, 0x1);
1272
1273 /* wait for erase to complete or failure to occur */
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001274 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP |
Jason Robertsce082592010-05-13 15:57:33 +01001275 INTR_STATUS0__ERASE_FAIL);
1276
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +08001277 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ?
1278 NAND_STATUS_FAIL : PASS;
Jason Robertsce082592010-05-13 15:57:33 +01001279}
1280
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001281static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
Jason Robertsce082592010-05-13 15:57:33 +01001282 int page)
1283{
1284 struct denali_nand_info *denali = mtd_to_denali(mtd);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +08001285 uint32_t addr, id;
1286 int i;
Jason Robertsce082592010-05-13 15:57:33 +01001287
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001288 switch (cmd) {
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001289 case NAND_CMD_PAGEPROG:
1290 break;
1291 case NAND_CMD_STATUS:
1292 read_status(denali);
1293 break;
1294 case NAND_CMD_READID:
Florian Fainelli42af8b52010-08-30 18:32:20 +02001295 case NAND_CMD_PARAM:
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001296 reset_buf(denali);
Chuanxiao Dongef41e1b2010-08-06 00:48:49 +08001297 /*sometimes ManufactureId read from register is not right
1298 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1299 * So here we send READID cmd to NAND insteand
1300 * */
1301 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1302 index_addr(denali, (uint32_t)addr | 0, 0x90);
1303 index_addr(denali, (uint32_t)addr | 1, 0);
1304 for (i = 0; i < 5; i++) {
1305 index_addr_read_data(denali,
1306 (uint32_t)addr | 2,
1307 &id);
1308 write_byte_to_buf(denali, id);
Chuanxiao Donga99d1792010-07-27 11:32:21 +08001309 }
1310 break;
1311 case NAND_CMD_READ0:
1312 case NAND_CMD_SEQIN:
1313 denali->page = page;
1314 break;
1315 case NAND_CMD_RESET:
1316 reset_bank(denali);
1317 break;
1318 case NAND_CMD_READOOB:
1319 /* TODO: Read OOB data */
1320 break;
1321 default:
1322 printk(KERN_ERR ": unsupported command"
1323 " received 0x%x\n", cmd);
1324 break;
Jason Robertsce082592010-05-13 15:57:33 +01001325 }
1326}
1327
1328/* stubs for ECC functions not used by the NAND core */
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001329static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
Jason Robertsce082592010-05-13 15:57:33 +01001330 uint8_t *ecc_code)
1331{
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +08001332 struct denali_nand_info *denali = mtd_to_denali(mtd);
1333 dev_err(&denali->dev->dev,
1334 "denali_ecc_calculate called unexpectedly\n");
Jason Robertsce082592010-05-13 15:57:33 +01001335 BUG();
1336 return -EIO;
1337}
1338
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001339static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
Jason Robertsce082592010-05-13 15:57:33 +01001340 uint8_t *read_ecc, uint8_t *calc_ecc)
1341{
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +08001342 struct denali_nand_info *denali = mtd_to_denali(mtd);
1343 dev_err(&denali->dev->dev,
1344 "denali_ecc_correct called unexpectedly\n");
Jason Robertsce082592010-05-13 15:57:33 +01001345 BUG();
1346 return -EIO;
1347}
1348
1349static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
1350{
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +08001351 struct denali_nand_info *denali = mtd_to_denali(mtd);
1352 dev_err(&denali->dev->dev,
1353 "denali_ecc_hwctl called unexpectedly\n");
Jason Robertsce082592010-05-13 15:57:33 +01001354 BUG();
1355}
1356/* end NAND core entry points */
1357
1358/* Initialization code to bring the device up to a known good state */
1359static void denali_hw_init(struct denali_nand_info *denali)
1360{
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001361 /* tell driver how many bit controller will skip before
1362 * writing ECC code in OOB, this register may be already
1363 * set by firmware. So we read this value out.
1364 * if this value is 0, just let it be.
1365 * */
1366 denali->bbtskipbytes = ioread32(denali->flash_reg +
1367 SPARE_AREA_SKIP_BYTES);
Chuanxiao Dongeda936e2010-07-27 14:17:37 +08001368 denali_nand_reset(denali);
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001369 iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1370 iowrite32(CHIP_EN_DONT_CARE__FLAG,
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +08001371 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
Jason Robertsce082592010-05-13 15:57:33 +01001372
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001373 iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
Jason Robertsce082592010-05-13 15:57:33 +01001374
1375 /* Should set value for these registers when init */
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001376 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1377 iowrite32(1, denali->flash_reg + ECC_ENABLE);
Chuanxiao Dong5eab6aaa2010-08-12 10:07:18 +08001378 denali_nand_timing_set(denali);
1379 denali_irq_init(denali);
Jason Robertsce082592010-05-13 15:57:33 +01001380}
1381
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001382/* Althogh controller spec said SLC ECC is forceb to be 4bit,
1383 * but denali controller in MRST only support 15bit and 8bit ECC
1384 * correction
1385 * */
1386#define ECC_8BITS 14
1387static struct nand_ecclayout nand_8bit_oob = {
1388 .eccbytes = 14,
Jason Robertsce082592010-05-13 15:57:33 +01001389};
1390
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001391#define ECC_15BITS 26
1392static struct nand_ecclayout nand_15bit_oob = {
1393 .eccbytes = 26,
Jason Robertsce082592010-05-13 15:57:33 +01001394};
1395
1396static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1397static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1398
1399static struct nand_bbt_descr bbt_main_descr = {
1400 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1401 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1402 .offs = 8,
1403 .len = 4,
1404 .veroffs = 12,
1405 .maxblocks = 4,
1406 .pattern = bbt_pattern,
1407};
1408
1409static struct nand_bbt_descr bbt_mirror_descr = {
1410 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1411 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1412 .offs = 8,
1413 .len = 4,
1414 .veroffs = 12,
1415 .maxblocks = 4,
1416 .pattern = mirror_pattern,
1417};
1418
Uwe Kleine-König421f91d2010-06-11 12:17:00 +02001419/* initialize driver data structures */
Jason Robertsce082592010-05-13 15:57:33 +01001420void denali_drv_init(struct denali_nand_info *denali)
1421{
1422 denali->idx = 0;
1423
1424 /* setup interrupt handler */
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001425 /* the completion object will be used to notify
Jason Robertsce082592010-05-13 15:57:33 +01001426 * the callee that the interrupt is done */
1427 init_completion(&denali->complete);
1428
1429 /* the spinlock will be used to synchronize the ISR
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001430 * with any element that might be access shared
Jason Robertsce082592010-05-13 15:57:33 +01001431 * data (interrupt status) */
1432 spin_lock_init(&denali->irq_lock);
1433
1434 /* indicate that MTD has not selected a valid bank yet */
1435 denali->flash_bank = CHIP_SELECT_INVALID;
1436
1437 /* initialize our irq_status variable to indicate no interrupts */
1438 denali->irq_status = 0;
1439}
1440
1441/* driver entry point */
1442static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1443{
1444 int ret = -ENODEV;
1445 resource_size_t csr_base, mem_base;
1446 unsigned long csr_len, mem_len;
1447 struct denali_nand_info *denali;
1448
Jason Robertsce082592010-05-13 15:57:33 +01001449 denali = kzalloc(sizeof(*denali), GFP_KERNEL);
1450 if (!denali)
1451 return -ENOMEM;
1452
1453 ret = pci_enable_device(dev);
1454 if (ret) {
1455 printk(KERN_ERR "Spectra: pci_enable_device failed.\n");
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001456 goto failed_alloc_memery;
Jason Robertsce082592010-05-13 15:57:33 +01001457 }
1458
1459 if (id->driver_data == INTEL_CE4100) {
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001460 /* Due to a silicon limitation, we can only support
1461 * ONFI timing mode 1 and below.
1462 */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001463 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +08001464 printk(KERN_ERR "Intel CE4100 only supports"
1465 " ONFI timing mode 1 or below\n");
Jason Robertsce082592010-05-13 15:57:33 +01001466 ret = -EINVAL;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001467 goto failed_enable_dev;
Jason Robertsce082592010-05-13 15:57:33 +01001468 }
1469 denali->platform = INTEL_CE4100;
1470 mem_base = pci_resource_start(dev, 0);
1471 mem_len = pci_resource_len(dev, 1);
1472 csr_base = pci_resource_start(dev, 1);
1473 csr_len = pci_resource_len(dev, 1);
1474 } else {
1475 denali->platform = INTEL_MRST;
1476 csr_base = pci_resource_start(dev, 0);
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001477 csr_len = pci_resource_len(dev, 0);
Jason Robertsce082592010-05-13 15:57:33 +01001478 mem_base = pci_resource_start(dev, 1);
1479 mem_len = pci_resource_len(dev, 1);
1480 if (!mem_len) {
1481 mem_base = csr_base + csr_len;
1482 mem_len = csr_len;
Jason Robertsce082592010-05-13 15:57:33 +01001483 }
1484 }
1485
1486 /* Is 32-bit DMA supported? */
1487 ret = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
1488
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001489 if (ret) {
Jason Robertsce082592010-05-13 15:57:33 +01001490 printk(KERN_ERR "Spectra: no usable DMA configuration\n");
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001491 goto failed_enable_dev;
Jason Robertsce082592010-05-13 15:57:33 +01001492 }
Chuanxiao Dongbdca6da2010-07-27 11:28:09 +08001493 denali->buf.dma_buf =
1494 pci_map_single(dev, denali->buf.buf,
1495 DENALI_BUF_SIZE,
1496 PCI_DMA_BIDIRECTIONAL);
Jason Robertsce082592010-05-13 15:57:33 +01001497
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001498 if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) {
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +08001499 dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n");
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001500 goto failed_enable_dev;
Jason Robertsce082592010-05-13 15:57:33 +01001501 }
1502
1503 pci_set_master(dev);
1504 denali->dev = dev;
Chuanxiao Dong5eab6aaa2010-08-12 10:07:18 +08001505 denali->mtd.dev.parent = &dev->dev;
Jason Robertsce082592010-05-13 15:57:33 +01001506
1507 ret = pci_request_regions(dev, DENALI_NAND_NAME);
1508 if (ret) {
1509 printk(KERN_ERR "Spectra: Unable to request memory regions\n");
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001510 goto failed_dma_map;
Jason Robertsce082592010-05-13 15:57:33 +01001511 }
1512
1513 denali->flash_reg = ioremap_nocache(csr_base, csr_len);
1514 if (!denali->flash_reg) {
1515 printk(KERN_ERR "Spectra: Unable to remap memory region\n");
1516 ret = -ENOMEM;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001517 goto failed_req_regions;
Jason Robertsce082592010-05-13 15:57:33 +01001518 }
Jason Robertsce082592010-05-13 15:57:33 +01001519
1520 denali->flash_mem = ioremap_nocache(mem_base, mem_len);
1521 if (!denali->flash_mem) {
1522 printk(KERN_ERR "Spectra: ioremap_nocache failed!");
Jason Robertsce082592010-05-13 15:57:33 +01001523 ret = -ENOMEM;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001524 goto failed_remap_reg;
Jason Robertsce082592010-05-13 15:57:33 +01001525 }
1526
Jason Robertsce082592010-05-13 15:57:33 +01001527 denali_hw_init(denali);
1528 denali_drv_init(denali);
1529
Chuanxiao Dong5eab6aaa2010-08-12 10:07:18 +08001530 /* denali_isr register is done after all the hardware
1531 * initilization is finished*/
Jason Robertsce082592010-05-13 15:57:33 +01001532 if (request_irq(dev->irq, denali_isr, IRQF_SHARED,
1533 DENALI_NAND_NAME, denali)) {
1534 printk(KERN_ERR "Spectra: Unable to allocate IRQ\n");
1535 ret = -ENODEV;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001536 goto failed_remap_mem;
Jason Robertsce082592010-05-13 15:57:33 +01001537 }
1538
1539 /* now that our ISR is registered, we can enable interrupts */
Chuanxiao Dongeda936e2010-07-27 14:17:37 +08001540 denali_set_intr_modes(denali, true);
Jason Robertsce082592010-05-13 15:57:33 +01001541
1542 pci_set_drvdata(dev, denali);
1543
Chuanxiao Dong5eab6aaa2010-08-12 10:07:18 +08001544 denali->mtd.name = "denali-nand";
Jason Robertsce082592010-05-13 15:57:33 +01001545 denali->mtd.owner = THIS_MODULE;
1546 denali->mtd.priv = &denali->nand;
1547
1548 /* register the driver with the NAND core subsystem */
1549 denali->nand.select_chip = denali_select_chip;
1550 denali->nand.cmdfunc = denali_cmdfunc;
1551 denali->nand.read_byte = denali_read_byte;
1552 denali->nand.waitfunc = denali_waitfunc;
1553
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001554 /* scan for NAND devices attached to the controller
Jason Robertsce082592010-05-13 15:57:33 +01001555 * this is the first stage in a two step process to register
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001556 * with the nand subsystem */
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001557 if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) {
Jason Robertsce082592010-05-13 15:57:33 +01001558 ret = -ENXIO;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001559 goto failed_req_irq;
Jason Robertsce082592010-05-13 15:57:33 +01001560 }
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001561
Chuanxiao.Dong66406522010-08-06 18:48:21 +08001562 /* MTD supported page sizes vary by kernel. We validate our
1563 * kernel supports the device here.
1564 */
1565 if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
1566 ret = -ENODEV;
1567 printk(KERN_ERR "Spectra: device size not supported by this "
1568 "version of MTD.");
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001569 goto failed_req_irq;
Chuanxiao.Dong66406522010-08-06 18:48:21 +08001570 }
1571
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001572 /* support for multi nand
1573 * MTD known nothing about multi nand,
1574 * so we should tell it the real pagesize
1575 * and anything necessery
1576 */
1577 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1578 denali->nand.chipsize <<= (denali->devnum - 1);
1579 denali->nand.page_shift += (denali->devnum - 1);
1580 denali->nand.pagemask = (denali->nand.chipsize >>
1581 denali->nand.page_shift) - 1;
1582 denali->nand.bbt_erase_shift += (denali->devnum - 1);
1583 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1584 denali->nand.chip_shift += (denali->devnum - 1);
1585 denali->mtd.writesize <<= (denali->devnum - 1);
1586 denali->mtd.oobsize <<= (denali->devnum - 1);
1587 denali->mtd.erasesize <<= (denali->devnum - 1);
1588 denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
1589 denali->bbtskipbytes *= denali->devnum;
1590
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001591 /* second stage of the NAND scan
1592 * this stage requires information regarding ECC and
1593 * bad block management. */
Jason Robertsce082592010-05-13 15:57:33 +01001594
1595 /* Bad block management */
1596 denali->nand.bbt_td = &bbt_main_descr;
1597 denali->nand.bbt_md = &bbt_mirror_descr;
1598
1599 /* skip the scan for now until we have OOB read and write support */
1600 denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
1601 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1602
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001603 /* Denali Controller only support 15bit and 8bit ECC in MRST,
1604 * so just let controller do 15bit ECC for MLC and 8bit ECC for
1605 * SLC if possible.
1606 * */
1607 if (denali->nand.cellinfo & 0xc &&
1608 (denali->mtd.oobsize > (denali->bbtskipbytes +
1609 ECC_15BITS * (denali->mtd.writesize /
1610 ECC_SECTOR_SIZE)))) {
1611 /* if MLC OOB size is large enough, use 15bit ECC*/
1612 denali->nand.ecc.layout = &nand_15bit_oob;
1613 denali->nand.ecc.bytes = ECC_15BITS;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001614 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001615 } else if (denali->mtd.oobsize < (denali->bbtskipbytes +
1616 ECC_8BITS * (denali->mtd.writesize /
1617 ECC_SECTOR_SIZE))) {
1618 printk(KERN_ERR "Your NAND chip OOB is not large enough to"
1619 " contain 8bit ECC correction codes");
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001620 goto failed_req_irq;
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001621 } else {
1622 denali->nand.ecc.layout = &nand_8bit_oob;
1623 denali->nand.ecc.bytes = ECC_8BITS;
Chuanxiao Dong24c3fa32010-08-09 23:59:23 +08001624 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
Jason Robertsce082592010-05-13 15:57:33 +01001625 }
1626
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001627 denali->nand.ecc.bytes *= denali->devnum;
Chuanxiao Dongdb9a32102010-08-06 18:02:03 +08001628 denali->nand.ecc.layout->eccbytes *=
1629 denali->mtd.writesize / ECC_SECTOR_SIZE;
1630 denali->nand.ecc.layout->oobfree[0].offset =
1631 denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
1632 denali->nand.ecc.layout->oobfree[0].length =
1633 denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
1634 denali->bbtskipbytes;
1635
Chuanxiao.Dong66406522010-08-06 18:48:21 +08001636 /* Let driver know the total blocks number and
1637 * how many blocks contained by each nand chip.
1638 * blksperchip will help driver to know how many
1639 * blocks is taken by FW.
1640 * */
1641 denali->totalblks = denali->mtd.size >>
1642 denali->nand.phys_erase_shift;
1643 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1644
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001645 /* These functions are required by the NAND core framework, otherwise,
1646 * the NAND core will assert. However, we don't need them, so we'll stub
1647 * them out. */
Jason Robertsce082592010-05-13 15:57:33 +01001648 denali->nand.ecc.calculate = denali_ecc_calculate;
1649 denali->nand.ecc.correct = denali_ecc_correct;
1650 denali->nand.ecc.hwctl = denali_ecc_hwctl;
1651
1652 /* override the default read operations */
Chuanxiao Dong08b9ab92010-08-06 18:19:09 +08001653 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
Jason Robertsce082592010-05-13 15:57:33 +01001654 denali->nand.ecc.read_page = denali_read_page;
1655 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1656 denali->nand.ecc.write_page = denali_write_page;
1657 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1658 denali->nand.ecc.read_oob = denali_read_oob;
1659 denali->nand.ecc.write_oob = denali_write_oob;
1660 denali->nand.erase_cmd = denali_erase;
1661
Chuanxiao Dong345b1d32010-07-27 10:41:53 +08001662 if (nand_scan_tail(&denali->mtd)) {
Jason Robertsce082592010-05-13 15:57:33 +01001663 ret = -ENXIO;
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001664 goto failed_req_irq;
Jason Robertsce082592010-05-13 15:57:33 +01001665 }
1666
1667 ret = add_mtd_device(&denali->mtd);
1668 if (ret) {
Chuanxiao Dong7cfffac2010-08-10 00:16:51 +08001669 dev_err(&dev->dev, "Spectra: Failed to register MTD: %d\n",
1670 ret);
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001671 goto failed_req_irq;
Jason Robertsce082592010-05-13 15:57:33 +01001672 }
1673 return 0;
1674
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001675failed_req_irq:
Jason Robertsce082592010-05-13 15:57:33 +01001676 denali_irq_cleanup(dev->irq, denali);
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001677failed_remap_mem:
Jason Robertsce082592010-05-13 15:57:33 +01001678 iounmap(denali->flash_mem);
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001679failed_remap_reg:
1680 iounmap(denali->flash_reg);
1681failed_req_regions:
Jason Robertsce082592010-05-13 15:57:33 +01001682 pci_release_regions(dev);
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001683failed_dma_map:
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001684 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
Jason Robertsce082592010-05-13 15:57:33 +01001685 PCI_DMA_BIDIRECTIONAL);
Chuanxiao Dong5c0eb902010-08-09 18:37:00 +08001686failed_enable_dev:
1687 pci_disable_device(dev);
1688failed_alloc_memery:
Jason Robertsce082592010-05-13 15:57:33 +01001689 kfree(denali);
1690 return ret;
1691}
1692
1693/* driver exit point */
1694static void denali_pci_remove(struct pci_dev *dev)
1695{
1696 struct denali_nand_info *denali = pci_get_drvdata(dev);
1697
Jason Robertsce082592010-05-13 15:57:33 +01001698 nand_release(&denali->mtd);
1699 del_mtd_device(&denali->mtd);
1700
1701 denali_irq_cleanup(dev->irq, denali);
1702
1703 iounmap(denali->flash_reg);
1704 iounmap(denali->flash_mem);
1705 pci_release_regions(dev);
1706 pci_disable_device(dev);
Chuanxiao5bac3ac2010-08-05 23:06:04 +08001707 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
Jason Robertsce082592010-05-13 15:57:33 +01001708 PCI_DMA_BIDIRECTIONAL);
1709 pci_set_drvdata(dev, NULL);
1710 kfree(denali);
1711}
1712
1713MODULE_DEVICE_TABLE(pci, denali_pci_ids);
1714
1715static struct pci_driver denali_pci_driver = {
1716 .name = DENALI_NAND_NAME,
1717 .id_table = denali_pci_ids,
1718 .probe = denali_pci_probe,
1719 .remove = denali_pci_remove,
1720};
1721
1722static int __devinit denali_init(void)
1723{
Michal Marek9b5705a22011-04-05 16:59:03 +02001724 printk(KERN_INFO "Spectra MTD driver\n");
Jason Robertsce082592010-05-13 15:57:33 +01001725 return pci_register_driver(&denali_pci_driver);
1726}
1727
1728/* Free memory */
1729static void __devexit denali_exit(void)
1730{
1731 pci_unregister_driver(&denali_pci_driver);
1732}
1733
1734module_init(denali_init);
1735module_exit(denali_exit);