blob: bbfb1a68fb1170d1a48f45d03f3ce08d38496f31 [file] [log] [blame]
Ben Skeggs6ee73862009-12-11 19:24:15 +10001/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
2/*
3 * Copyright 1996-1997 David J. McKay
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h,v 1.6 2002/01/25 21:56:06 tsi Exp $ */
25
26#ifndef __NVREG_H_
27#define __NVREG_H_
28
29#define NV_PMC_OFFSET 0x00000000
30#define NV_PMC_SIZE 0x00001000
31
32#define NV_PBUS_OFFSET 0x00001000
33#define NV_PBUS_SIZE 0x00001000
34
35#define NV_PFIFO_OFFSET 0x00002000
36#define NV_PFIFO_SIZE 0x00002000
37
38#define NV_HDIAG_OFFSET 0x00005000
39#define NV_HDIAG_SIZE 0x00001000
40
41#define NV_PRAM_OFFSET 0x00006000
42#define NV_PRAM_SIZE 0x00001000
43
44#define NV_PVIDEO_OFFSET 0x00008000
45#define NV_PVIDEO_SIZE 0x00001000
46
47#define NV_PTIMER_OFFSET 0x00009000
48#define NV_PTIMER_SIZE 0x00001000
49
50#define NV_PPM_OFFSET 0x0000A000
51#define NV_PPM_SIZE 0x00001000
52
53#define NV_PTV_OFFSET 0x0000D000
54#define NV_PTV_SIZE 0x00001000
55
56#define NV_PRMVGA_OFFSET 0x000A0000
57#define NV_PRMVGA_SIZE 0x00020000
58
59#define NV_PRMVIO0_OFFSET 0x000C0000
60#define NV_PRMVIO_SIZE 0x00002000
61#define NV_PRMVIO1_OFFSET 0x000C2000
62
63#define NV_PFB_OFFSET 0x00100000
64#define NV_PFB_SIZE 0x00001000
65
66#define NV_PEXTDEV_OFFSET 0x00101000
67#define NV_PEXTDEV_SIZE 0x00001000
68
69#define NV_PME_OFFSET 0x00200000
70#define NV_PME_SIZE 0x00001000
71
72#define NV_PROM_OFFSET 0x00300000
73#define NV_PROM_SIZE 0x00010000
74
75#define NV_PGRAPH_OFFSET 0x00400000
76#define NV_PGRAPH_SIZE 0x00010000
77
78#define NV_PCRTC0_OFFSET 0x00600000
79#define NV_PCRTC0_SIZE 0x00002000 /* empirical */
80
81#define NV_PRMCIO0_OFFSET 0x00601000
82#define NV_PRMCIO_SIZE 0x00002000
83#define NV_PRMCIO1_OFFSET 0x00603000
84
85#define NV50_DISPLAY_OFFSET 0x00610000
86#define NV50_DISPLAY_SIZE 0x0000FFFF
87
88#define NV_PRAMDAC0_OFFSET 0x00680000
89#define NV_PRAMDAC0_SIZE 0x00002000
90
91#define NV_PRMDIO0_OFFSET 0x00681000
92#define NV_PRMDIO_SIZE 0x00002000
93#define NV_PRMDIO1_OFFSET 0x00683000
94
95#define NV_PRAMIN_OFFSET 0x00700000
96#define NV_PRAMIN_SIZE 0x00100000
97
98#define NV_FIFO_OFFSET 0x00800000
99#define NV_FIFO_SIZE 0x00800000
100
101#define NV_PMC_BOOT_0 0x00000000
102#define NV_PMC_ENABLE 0x00000200
103
104#define NV_VIO_VSE2 0x000003c3
105#define NV_VIO_SRX 0x000003c4
106
107#define NV_CIO_CRX__COLOR 0x000003d4
108#define NV_CIO_CR__COLOR 0x000003d5
109
110#define NV_PBUS_DEBUG_1 0x00001084
111#define NV_PBUS_DEBUG_4 0x00001098
112#define NV_PBUS_DEBUG_DUALHEAD_CTL 0x000010f0
113#define NV_PBUS_POWERCTRL_1 0x00001584
114#define NV_PBUS_POWERCTRL_2 0x00001588
115#define NV_PBUS_POWERCTRL_4 0x00001590
116#define NV_PBUS_PCI_NV_19 0x0000184C
117#define NV_PBUS_PCI_NV_20 0x00001850
118# define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0)
119# define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0)
120
121#define NV_PFIFO_RAMHT 0x00002210
122
123#define NV_PTV_TV_INDEX 0x0000d220
124#define NV_PTV_TV_DATA 0x0000d224
125#define NV_PTV_HFILTER 0x0000d310
126#define NV_PTV_HFILTER2 0x0000d390
127#define NV_PTV_VFILTER 0x0000d510
128
129#define NV_PRMVIO_MISC__WRITE 0x000c03c2
130#define NV_PRMVIO_SRX 0x000c03c4
131#define NV_PRMVIO_SR 0x000c03c5
132# define NV_VIO_SR_RESET_INDEX 0x00
133# define NV_VIO_SR_CLOCK_INDEX 0x01
134# define NV_VIO_SR_PLANE_MASK_INDEX 0x02
135# define NV_VIO_SR_CHAR_MAP_INDEX 0x03
136# define NV_VIO_SR_MEM_MODE_INDEX 0x04
137#define NV_PRMVIO_MISC__READ 0x000c03cc
138#define NV_PRMVIO_GRX 0x000c03ce
139#define NV_PRMVIO_GX 0x000c03cf
140# define NV_VIO_GX_SR_INDEX 0x00
141# define NV_VIO_GX_SREN_INDEX 0x01
142# define NV_VIO_GX_CCOMP_INDEX 0x02
143# define NV_VIO_GX_ROP_INDEX 0x03
144# define NV_VIO_GX_READ_MAP_INDEX 0x04
145# define NV_VIO_GX_MODE_INDEX 0x05
146# define NV_VIO_GX_MISC_INDEX 0x06
147# define NV_VIO_GX_DONT_CARE_INDEX 0x07
148# define NV_VIO_GX_BIT_MASK_INDEX 0x08
149
Ben Skeggs6ee73862009-12-11 19:24:15 +1000150#define NV_PCRTC_INTR_0 0x00600100
151# define NV_PCRTC_INTR_0_VBLANK (1 << 0)
152#define NV_PCRTC_INTR_EN_0 0x00600140
153#define NV_PCRTC_START 0x00600800
154#define NV_PCRTC_CONFIG 0x00600804
155# define NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA (1 << 0)
Francisco Jerez63f7fcf2010-10-22 04:31:02 +0200156# define NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC (4 << 0)
157# define NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC (2 << 0)
Ben Skeggs6ee73862009-12-11 19:24:15 +1000158#define NV_PCRTC_CURSOR_CONFIG 0x00600810
159# define NV_PCRTC_CURSOR_CONFIG_ENABLE_ENABLE (1 << 0)
160# define NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE (1 << 4)
161# define NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM (1 << 8)
162# define NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32 (1 << 12)
163# define NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 (1 << 16)
164# define NV_PCRTC_CURSOR_CONFIG_CUR_LINES_32 (2 << 24)
165# define NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 (4 << 24)
166# define NV_PCRTC_CURSOR_CONFIG_CUR_BLEND_ALPHA (1 << 28)
167
168/* note: PCRTC_GPIO is not available on nv10, and in fact aliases 0x600810 */
169#define NV_PCRTC_GPIO 0x00600818
170#define NV_PCRTC_GPIO_EXT 0x0060081c
171#define NV_PCRTC_830 0x00600830
172#define NV_PCRTC_834 0x00600834
173#define NV_PCRTC_850 0x00600850
174#define NV_PCRTC_ENGINE_CTRL 0x00600860
175# define NV_CRTC_FSEL_I2C (1 << 4)
176# define NV_CRTC_FSEL_OVERLAY (1 << 12)
177
178#define NV_PRMCIO_ARX 0x006013c0
179#define NV_PRMCIO_AR__WRITE 0x006013c0
180#define NV_PRMCIO_AR__READ 0x006013c1
181# define NV_CIO_AR_MODE_INDEX 0x10
182# define NV_CIO_AR_OSCAN_INDEX 0x11
183# define NV_CIO_AR_PLANE_INDEX 0x12
184# define NV_CIO_AR_HPP_INDEX 0x13
185# define NV_CIO_AR_CSEL_INDEX 0x14
186#define NV_PRMCIO_INP0 0x006013c2
187#define NV_PRMCIO_CRX__COLOR 0x006013d4
188#define NV_PRMCIO_CR__COLOR 0x006013d5
189 /* Standard VGA CRTC registers */
190# define NV_CIO_CR_HDT_INDEX 0x00 /* horizontal display total */
191# define NV_CIO_CR_HDE_INDEX 0x01 /* horizontal display end */
192# define NV_CIO_CR_HBS_INDEX 0x02 /* horizontal blanking start */
193# define NV_CIO_CR_HBE_INDEX 0x03 /* horizontal blanking end */
194# define NV_CIO_CR_HBE_4_0 4:0
195# define NV_CIO_CR_HRS_INDEX 0x04 /* horizontal retrace start */
196# define NV_CIO_CR_HRE_INDEX 0x05 /* horizontal retrace end */
197# define NV_CIO_CR_HRE_4_0 4:0
198# define NV_CIO_CR_HRE_HBE_5 7:7
199# define NV_CIO_CR_VDT_INDEX 0x06 /* vertical display total */
200# define NV_CIO_CR_OVL_INDEX 0x07 /* overflow bits */
201# define NV_CIO_CR_OVL_VDT_8 0:0
202# define NV_CIO_CR_OVL_VDE_8 1:1
203# define NV_CIO_CR_OVL_VRS_8 2:2
204# define NV_CIO_CR_OVL_VBS_8 3:3
205# define NV_CIO_CR_OVL_VDT_9 5:5
206# define NV_CIO_CR_OVL_VDE_9 6:6
207# define NV_CIO_CR_OVL_VRS_9 7:7
208# define NV_CIO_CR_RSAL_INDEX 0x08 /* normally "preset row scan" */
209# define NV_CIO_CR_CELL_HT_INDEX 0x09 /* cell height?! normally "max scan line" */
210# define NV_CIO_CR_CELL_HT_VBS_9 5:5
211# define NV_CIO_CR_CELL_HT_SCANDBL 7:7
212# define NV_CIO_CR_CURS_ST_INDEX 0x0a /* cursor start */
213# define NV_CIO_CR_CURS_END_INDEX 0x0b /* cursor end */
214# define NV_CIO_CR_SA_HI_INDEX 0x0c /* screen start address high */
215# define NV_CIO_CR_SA_LO_INDEX 0x0d /* screen start address low */
216# define NV_CIO_CR_TCOFF_HI_INDEX 0x0e /* cursor offset high */
217# define NV_CIO_CR_TCOFF_LO_INDEX 0x0f /* cursor offset low */
218# define NV_CIO_CR_VRS_INDEX 0x10 /* vertical retrace start */
219# define NV_CIO_CR_VRE_INDEX 0x11 /* vertical retrace end */
220# define NV_CIO_CR_VRE_3_0 3:0
221# define NV_CIO_CR_VDE_INDEX 0x12 /* vertical display end */
222# define NV_CIO_CR_OFFSET_INDEX 0x13 /* sets screen pitch */
223# define NV_CIO_CR_ULINE_INDEX 0x14 /* underline location */
224# define NV_CIO_CR_VBS_INDEX 0x15 /* vertical blank start */
225# define NV_CIO_CR_VBE_INDEX 0x16 /* vertical blank end */
226# define NV_CIO_CR_MODE_INDEX 0x17 /* crtc mode control */
227# define NV_CIO_CR_LCOMP_INDEX 0x18 /* line compare */
228 /* Extended VGA CRTC registers */
229# define NV_CIO_CRE_RPC0_INDEX 0x19 /* repaint control 0 */
230# define NV_CIO_CRE_RPC0_OFFSET_10_8 7:5
231# define NV_CIO_CRE_RPC1_INDEX 0x1a /* repaint control 1 */
232# define NV_CIO_CRE_RPC1_LARGE 2:2
233# define NV_CIO_CRE_FF_INDEX 0x1b /* fifo control */
234# define NV_CIO_CRE_ENH_INDEX 0x1c /* enhanced? */
235# define NV_CIO_SR_LOCK_INDEX 0x1f /* crtc lock */
236# define NV_CIO_SR_UNLOCK_RW_VALUE 0x57
237# define NV_CIO_SR_LOCK_VALUE 0x99
238# define NV_CIO_CRE_FFLWM__INDEX 0x20 /* fifo low water mark */
239# define NV_CIO_CRE_21 0x21 /* vga shadow crtc lock */
240# define NV_CIO_CRE_LSR_INDEX 0x25 /* ? */
241# define NV_CIO_CRE_LSR_VDT_10 0:0
242# define NV_CIO_CRE_LSR_VDE_10 1:1
243# define NV_CIO_CRE_LSR_VRS_10 2:2
244# define NV_CIO_CRE_LSR_VBS_10 3:3
245# define NV_CIO_CRE_LSR_HBE_6 4:4
246# define NV_CIO_CR_ARX_INDEX 0x26 /* attribute index -- ro copy of 0x60.3c0 */
247# define NV_CIO_CRE_CHIP_ID_INDEX 0x27 /* chip revision */
248# define NV_CIO_CRE_PIXEL_INDEX 0x28
249# define NV_CIO_CRE_PIXEL_FORMAT 1:0
250# define NV_CIO_CRE_HEB__INDEX 0x2d /* horizontal extra bits? */
251# define NV_CIO_CRE_HEB_HDT_8 0:0
252# define NV_CIO_CRE_HEB_HDE_8 1:1
253# define NV_CIO_CRE_HEB_HBS_8 2:2
254# define NV_CIO_CRE_HEB_HRS_8 3:3
255# define NV_CIO_CRE_HEB_ILC_8 4:4
256# define NV_CIO_CRE_2E 0x2e /* some scratch or dummy reg to force writes to sink in */
257# define NV_CIO_CRE_HCUR_ADDR2_INDEX 0x2f /* cursor */
258# define NV_CIO_CRE_HCUR_ADDR0_INDEX 0x30 /* pixmap */
259# define NV_CIO_CRE_HCUR_ADDR0_ADR 6:0
260# define NV_CIO_CRE_HCUR_ASI 7:7
261# define NV_CIO_CRE_HCUR_ADDR1_INDEX 0x31 /* address */
262# define NV_CIO_CRE_HCUR_ADDR1_ENABLE 0:0
263# define NV_CIO_CRE_HCUR_ADDR1_CUR_DBL 1:1
264# define NV_CIO_CRE_HCUR_ADDR1_ADR 7:2
265# define NV_CIO_CRE_LCD__INDEX 0x33
266# define NV_CIO_CRE_LCD_LCD_SELECT 0:0
Francisco Jerezcd2fb2e2010-09-28 20:47:58 +0200267# define NV_CIO_CRE_LCD_ROUTE_MASK 0x3b
Ben Skeggs6ee73862009-12-11 19:24:15 +1000268# define NV_CIO_CRE_DDC0_STATUS__INDEX 0x36
269# define NV_CIO_CRE_DDC0_WR__INDEX 0x37
270# define NV_CIO_CRE_ILACE__INDEX 0x39 /* interlace */
271# define NV_CIO_CRE_SCRATCH3__INDEX 0x3b
272# define NV_CIO_CRE_SCRATCH4__INDEX 0x3c
273# define NV_CIO_CRE_DDC_STATUS__INDEX 0x3e
274# define NV_CIO_CRE_DDC_WR__INDEX 0x3f
275# define NV_CIO_CRE_EBR_INDEX 0x41 /* extra bits ? (vertical) */
276# define NV_CIO_CRE_EBR_VDT_11 0:0
277# define NV_CIO_CRE_EBR_VDE_11 2:2
278# define NV_CIO_CRE_EBR_VRS_11 4:4
279# define NV_CIO_CRE_EBR_VBS_11 6:6
Francisco Jerezc1003d92011-05-24 15:57:14 +0200280# define NV_CIO_CRE_42 0x42
281# define NV_CIO_CRE_42_OFFSET_11 6:6
Ben Skeggs6ee73862009-12-11 19:24:15 +1000282# define NV_CIO_CRE_43 0x43
283# define NV_CIO_CRE_44 0x44 /* head control */
284# define NV_CIO_CRE_CSB 0x45 /* colour saturation boost */
285# define NV_CIO_CRE_RCR 0x46
286# define NV_CIO_CRE_RCR_ENDIAN_BIG 7:7
287# define NV_CIO_CRE_47 0x47 /* extended fifo lwm, used on nv30+ */
288# define NV_CIO_CRE_49 0x49
289# define NV_CIO_CRE_4B 0x4b /* given patterns in 0x[2-3][a-c] regs, probably scratch 6 */
290# define NV_CIO_CRE_TVOUT_LATENCY 0x52
291# define NV_CIO_CRE_53 0x53 /* `fp_htiming' according to Haiku */
292# define NV_CIO_CRE_54 0x54 /* `fp_vtiming' according to Haiku */
293# define NV_CIO_CRE_57 0x57 /* index reg for cr58 */
294# define NV_CIO_CRE_58 0x58 /* data reg for cr57 */
295# define NV_CIO_CRE_59 0x59 /* related to on/off-chip-ness of digital outputs */
296# define NV_CIO_CRE_5B 0x5B /* newer colour saturation reg */
297# define NV_CIO_CRE_85 0x85
298# define NV_CIO_CRE_86 0x86
299#define NV_PRMCIO_INP0__COLOR 0x006013da
300
301#define NV_PRAMDAC_CU_START_POS 0x00680300
302# define NV_PRAMDAC_CU_START_POS_X 15:0
303# define NV_PRAMDAC_CU_START_POS_Y 31:16
304#define NV_RAMDAC_NV10_CURSYNC 0x00680404
305
306#define NV_PRAMDAC_NVPLL_COEFF 0x00680500
307#define NV_PRAMDAC_MPLL_COEFF 0x00680504
308#define NV_PRAMDAC_VPLL_COEFF 0x00680508
309# define NV30_RAMDAC_ENABLE_VCO2 (8 << 4)
310
311#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050c
312# define NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE (4 << 0)
313# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL (1 << 8)
314# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL (2 << 8)
315# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL (4 << 8)
316# define NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 (8 << 8)
317# define NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 (1 << 16)
318# define NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 (2 << 16)
319# define NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 (4 << 16)
320# define NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2 (8 << 16)
321# define NV_PRAMDAC_PLL_COEFF_SELECT_TV_CLK_SOURCE_VIP (1 << 20)
322# define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 (1 << 28)
323# define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2 (2 << 28)
324
325#define NV_PRAMDAC_PLL_SETUP_CONTROL 0x00680510
326#define NV_RAMDAC_VPLL2 0x00680520
327#define NV_PRAMDAC_SEL_CLK 0x00680524
328#define NV_RAMDAC_DITHER_NV11 0x00680528
329#define NV_PRAMDAC_DACCLK 0x0068052c
330# define NV_PRAMDAC_DACCLK_SEL_DACCLK (1 << 0)
331
332#define NV_RAMDAC_NVPLL_B 0x00680570
333#define NV_RAMDAC_MPLL_B 0x00680574
334#define NV_RAMDAC_VPLL_B 0x00680578
335#define NV_RAMDAC_VPLL2_B 0x0068057c
336# define NV31_RAMDAC_ENABLE_VCO2 (8 << 28)
337#define NV_PRAMDAC_580 0x00680580
338# define NV_RAMDAC_580_VPLL1_ACTIVE (1 << 8)
339# define NV_RAMDAC_580_VPLL2_ACTIVE (1 << 28)
340
341#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600
342# define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON (3 << 4)
343# define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL (1 << 8)
344# define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL (1 << 12)
345# define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM (2 << 16)
346# define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS (1 << 20)
347# define NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG (2 << 28)
348#define NV_PRAMDAC_TEST_CONTROL 0x00680608
349# define NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED (1 << 12)
350# define NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF (1 << 16)
351# define NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI (1 << 28)
352#define NV_PRAMDAC_TESTPOINT_DATA 0x00680610
353# define NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK (8 << 28)
354#define NV_PRAMDAC_630 0x00680630
355#define NV_PRAMDAC_634 0x00680634
356
357#define NV_PRAMDAC_TV_SETUP 0x00680700
358#define NV_PRAMDAC_TV_VTOTAL 0x00680720
359#define NV_PRAMDAC_TV_VSKEW 0x00680724
360#define NV_PRAMDAC_TV_VSYNC_DELAY 0x00680728
361#define NV_PRAMDAC_TV_HTOTAL 0x0068072c
362#define NV_PRAMDAC_TV_HSKEW 0x00680730
363#define NV_PRAMDAC_TV_HSYNC_DELAY 0x00680734
364#define NV_PRAMDAC_TV_HSYNC_DELAY2 0x00680738
365
366#define NV_PRAMDAC_TV_SETUP 0x00680700
367
368#define NV_PRAMDAC_FP_VDISPLAY_END 0x00680800
369#define NV_PRAMDAC_FP_VTOTAL 0x00680804
370#define NV_PRAMDAC_FP_VCRTC 0x00680808
371#define NV_PRAMDAC_FP_VSYNC_START 0x0068080c
372#define NV_PRAMDAC_FP_VSYNC_END 0x00680810
373#define NV_PRAMDAC_FP_VVALID_START 0x00680814
374#define NV_PRAMDAC_FP_VVALID_END 0x00680818
375#define NV_PRAMDAC_FP_HDISPLAY_END 0x00680820
376#define NV_PRAMDAC_FP_HTOTAL 0x00680824
377#define NV_PRAMDAC_FP_HCRTC 0x00680828
378#define NV_PRAMDAC_FP_HSYNC_START 0x0068082c
379#define NV_PRAMDAC_FP_HSYNC_END 0x00680830
380#define NV_PRAMDAC_FP_HVALID_START 0x00680834
381#define NV_PRAMDAC_FP_HVALID_END 0x00680838
382
383#define NV_RAMDAC_FP_DITHER 0x0068083c
384#define NV_PRAMDAC_FP_TG_CONTROL 0x00680848
385# define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS (1 << 0)
386# define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE (2 << 0)
387# define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS (1 << 4)
388# define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE (2 << 4)
389# define NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE (0 << 8)
390# define NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER (1 << 8)
391# define NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE (2 << 8)
392# define NV_PRAMDAC_FP_TG_CONTROL_READ_PROG (1 << 20)
393# define NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 (1 << 24)
394# define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS (1 << 28)
395# define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE (2 << 28)
396#define NV_PRAMDAC_FP_MARGIN_COLOR 0x0068084c
397#define NV_PRAMDAC_850 0x00680850
398#define NV_PRAMDAC_85C 0x0068085c
399#define NV_PRAMDAC_FP_DEBUG_0 0x00680880
400# define NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE (1 << 0)
401# define NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE (1 << 4)
402/* This doesn't seem to be essential for tmds, but still often set */
403# define NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED (8 << 4)
404# define NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR (1 << 8)
405# define NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR (1 << 12)
406# define NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND (1 << 20)
407# define NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND (1 << 24)
408# define NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK (1 << 28)
409#define NV_PRAMDAC_FP_DEBUG_1 0x00680884
410# define NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE 11:0
411# define NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE (1 << 12)
412# define NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE 27:16
413# define NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE (1 << 28)
414#define NV_PRAMDAC_FP_DEBUG_2 0x00680888
415#define NV_PRAMDAC_FP_DEBUG_3 0x0068088C
416
417/* see NV_PRAMDAC_INDIR_TMDS in rules.xml */
418#define NV_PRAMDAC_FP_TMDS_CONTROL 0x006808b0
419# define NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE (1 << 16)
420#define NV_PRAMDAC_FP_TMDS_DATA 0x006808b4
421
422#define NV_PRAMDAC_8C0 0x006808c0
423
424/* Some kind of switch */
425#define NV_PRAMDAC_900 0x00680900
426#define NV_PRAMDAC_A20 0x00680A20
427#define NV_PRAMDAC_A24 0x00680A24
428#define NV_PRAMDAC_A34 0x00680A34
429
430#define NV_PRAMDAC_CTV 0x00680c00
431
432/* names fabricated from NV_USER_DAC info */
433#define NV_PRMDIO_PIXEL_MASK 0x006813c6
434# define NV_PRMDIO_PIXEL_MASK_MASK 0xff
435#define NV_PRMDIO_READ_MODE_ADDRESS 0x006813c7
436#define NV_PRMDIO_WRITE_MODE_ADDRESS 0x006813c8
437#define NV_PRMDIO_PALETTE_DATA 0x006813c9
438
439#define NV_PGRAPH_DEBUG_0 0x00400080
440#define NV_PGRAPH_DEBUG_1 0x00400084
441#define NV_PGRAPH_DEBUG_2_NV04 0x00400088
442#define NV_PGRAPH_DEBUG_2 0x00400620
443#define NV_PGRAPH_DEBUG_3 0x0040008c
444#define NV_PGRAPH_DEBUG_4 0x00400090
445#define NV_PGRAPH_INTR 0x00400100
446#define NV_PGRAPH_INTR_EN 0x00400140
447#define NV_PGRAPH_CTX_CONTROL 0x00400144
448#define NV_PGRAPH_CTX_CONTROL_NV04 0x00400170
449#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C
450#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540
451#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544
452#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548
453#define NV_PGRAPH_BETA_AND 0x00400608
454#define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610
455#define NV_PGRAPH_BOFFSET0 0x00400640
456#define NV_PGRAPH_BOFFSET1 0x00400644
457#define NV_PGRAPH_BOFFSET2 0x00400648
458#define NV_PGRAPH_BLIMIT0 0x00400684
459#define NV_PGRAPH_BLIMIT1 0x00400688
460#define NV_PGRAPH_BLIMIT2 0x0040068c
461#define NV_PGRAPH_STATUS 0x00400700
462#define NV_PGRAPH_SURFACE 0x00400710
463#define NV_PGRAPH_STATE 0x00400714
464#define NV_PGRAPH_FIFO 0x00400720
465#define NV_PGRAPH_PATTERN_SHAPE 0x00400810
466#define NV_PGRAPH_TILE 0x00400b00
467
468#define NV_PVIDEO_INTR_EN 0x00008140
469#define NV_PVIDEO_BUFFER 0x00008700
470#define NV_PVIDEO_STOP 0x00008704
471#define NV_PVIDEO_UVPLANE_BASE(buff) (0x00008800+(buff)*4)
472#define NV_PVIDEO_UVPLANE_LIMIT(buff) (0x00008808+(buff)*4)
473#define NV_PVIDEO_UVPLANE_OFFSET_BUFF(buff) (0x00008820+(buff)*4)
474#define NV_PVIDEO_BASE(buff) (0x00008900+(buff)*4)
475#define NV_PVIDEO_LIMIT(buff) (0x00008908+(buff)*4)
476#define NV_PVIDEO_LUMINANCE(buff) (0x00008910+(buff)*4)
477#define NV_PVIDEO_CHROMINANCE(buff) (0x00008918+(buff)*4)
478#define NV_PVIDEO_OFFSET_BUFF(buff) (0x00008920+(buff)*4)
479#define NV_PVIDEO_SIZE_IN(buff) (0x00008928+(buff)*4)
480#define NV_PVIDEO_POINT_IN(buff) (0x00008930+(buff)*4)
481#define NV_PVIDEO_DS_DX(buff) (0x00008938+(buff)*4)
482#define NV_PVIDEO_DT_DY(buff) (0x00008940+(buff)*4)
483#define NV_PVIDEO_POINT_OUT(buff) (0x00008948+(buff)*4)
484#define NV_PVIDEO_SIZE_OUT(buff) (0x00008950+(buff)*4)
485#define NV_PVIDEO_FORMAT(buff) (0x00008958+(buff)*4)
486# define NV_PVIDEO_FORMAT_PLANAR (1 << 0)
487# define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8 (1 << 16)
488# define NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY (1 << 20)
489# define NV_PVIDEO_FORMAT_MATRIX_ITURBT709 (1 << 24)
490#define NV_PVIDEO_COLOR_KEY 0x00008B00
491
492/* NV04 overlay defines from VIDIX & Haiku */
493#define NV_PVIDEO_INTR_EN_0 0x00680140
494#define NV_PVIDEO_STEP_SIZE 0x00680200
495#define NV_PVIDEO_CONTROL_Y 0x00680204
496#define NV_PVIDEO_CONTROL_X 0x00680208
497#define NV_PVIDEO_BUFF0_START_ADDRESS 0x0068020c
498#define NV_PVIDEO_BUFF0_PITCH_LENGTH 0x00680214
499#define NV_PVIDEO_BUFF0_OFFSET 0x0068021c
500#define NV_PVIDEO_BUFF1_START_ADDRESS 0x00680210
501#define NV_PVIDEO_BUFF1_PITCH_LENGTH 0x00680218
502#define NV_PVIDEO_BUFF1_OFFSET 0x00680220
503#define NV_PVIDEO_OE_STATE 0x00680224
504#define NV_PVIDEO_SU_STATE 0x00680228
505#define NV_PVIDEO_RM_STATE 0x0068022c
506#define NV_PVIDEO_WINDOW_START 0x00680230
507#define NV_PVIDEO_WINDOW_SIZE 0x00680234
508#define NV_PVIDEO_FIFO_THRES_SIZE 0x00680238
509#define NV_PVIDEO_FIFO_BURST_LENGTH 0x0068023c
510#define NV_PVIDEO_KEY 0x00680240
511#define NV_PVIDEO_OVERLAY 0x00680244
512#define NV_PVIDEO_RED_CSC_OFFSET 0x00680280
513#define NV_PVIDEO_GREEN_CSC_OFFSET 0x00680284
514#define NV_PVIDEO_BLUE_CSC_OFFSET 0x00680288
515#define NV_PVIDEO_CSC_ADJUST 0x0068028c
516
517#endif