blob: dbbd35b899856c18dcc271583ca566a70a73ab0d [file] [log] [blame]
Shawn Guo082d33d2013-04-02 13:15:16 +08001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Anson Huang22724cf12014-01-20 20:02:38 +080013#include <dt-bindings/gpio/gpio.h>
Anson Huang8e4422a2013-12-19 16:07:24 -050014#include <dt-bindings/input/input.h>
15
Shawn Guo082d33d2013-04-02 13:15:16 +080016/ {
17 memory {
18 reg = <0x10000000 0x40000000>;
19 };
20
21 regulators {
22 compatible = "simple-bus";
Shawn Guo56160e32014-02-07 23:22:50 +080023 #address-cells = <1>;
24 #size-cells = <0>;
Shawn Guo082d33d2013-04-02 13:15:16 +080025
Shawn Guo56160e32014-02-07 23:22:50 +080026 reg_usb_otg_vbus: regulator@0 {
Shawn Guo082d33d2013-04-02 13:15:16 +080027 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080028 reg = <0>;
Shawn Guo082d33d2013-04-02 13:15:16 +080029 regulator-name = "usb_otg_vbus";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
32 gpio = <&gpio3 22 0>;
33 enable-active-high;
34 };
Nicolin Chenfdbfb432013-06-13 19:51:00 +080035
Shawn Guo56160e32014-02-07 23:22:50 +080036 reg_usb_h1_vbus: regulator@1 {
Peter Chen015fa462013-08-12 16:46:24 +080037 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080038 reg = <1>;
Peter Chen015fa462013-08-12 16:46:24 +080039 regulator-name = "usb_h1_vbus";
40 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>;
42 gpio = <&gpio1 29 0>;
43 enable-active-high;
44 };
45
Shawn Guo56160e32014-02-07 23:22:50 +080046 reg_audio: regulator@2 {
Nicolin Chenfdbfb432013-06-13 19:51:00 +080047 compatible = "regulator-fixed";
Shawn Guo56160e32014-02-07 23:22:50 +080048 reg = <2>;
Nicolin Chenfdbfb432013-06-13 19:51:00 +080049 regulator-name = "wm8962-supply";
50 gpio = <&gpio4 10 0>;
51 enable-active-high;
52 };
Shawn Guo082d33d2013-04-02 13:15:16 +080053 };
54
55 gpio-keys {
56 compatible = "gpio-keys";
Anson Huang8e4422a2013-12-19 16:07:24 -050057 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_gpio_keys>;
59
60 power {
61 label = "Power Button";
Anson Huang22724cf12014-01-20 20:02:38 +080062 gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
Anson Huang8e4422a2013-12-19 16:07:24 -050063 gpio-key,wakeup;
64 linux,code = <KEY_POWER>;
65 };
Shawn Guo082d33d2013-04-02 13:15:16 +080066
67 volume-up {
68 label = "Volume Up";
Anson Huang22724cf12014-01-20 20:02:38 +080069 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
Fabio Estevam6c306402013-07-19 10:40:23 -030070 gpio-key,wakeup;
Anson Huang8e4422a2013-12-19 16:07:24 -050071 linux,code = <KEY_VOLUMEUP>;
Shawn Guo082d33d2013-04-02 13:15:16 +080072 };
73
74 volume-down {
75 label = "Volume Down";
Anson Huang22724cf12014-01-20 20:02:38 +080076 gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
Fabio Estevam6c306402013-07-19 10:40:23 -030077 gpio-key,wakeup;
Anson Huang8e4422a2013-12-19 16:07:24 -050078 linux,code = <KEY_VOLUMEDOWN>;
Shawn Guo082d33d2013-04-02 13:15:16 +080079 };
80 };
Nicolin Chen77b38fc2013-06-14 13:22:46 +080081
82 sound {
83 compatible = "fsl,imx6q-sabresd-wm8962",
84 "fsl,imx-audio-wm8962";
85 model = "wm8962-audio";
86 ssi-controller = <&ssi2>;
87 audio-codec = <&codec>;
88 audio-routing =
89 "Headphone Jack", "HPOUTL",
90 "Headphone Jack", "HPOUTR",
91 "Ext Spk", "SPKOUTL",
92 "Ext Spk", "SPKOUTR",
93 "MICBIAS", "AMIC",
94 "IN3R", "MICBIAS",
95 "DMIC", "MICBIAS",
96 "DMICDAT", "DMIC";
97 mux-int-port = <2>;
98 mux-ext-port = <3>;
99 };
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300100
101 backlight {
102 compatible = "pwm-backlight";
103 pwms = <&pwm1 0 5000000>;
104 brightness-levels = <0 4 8 16 32 64 128 255>;
105 default-brightness-level = <7>;
106 status = "okay";
107 };
Vincent Stehlé702bfbe2014-03-05 19:58:39 +0100108
109 leds {
110 compatible = "gpio-leds";
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_gpio_leds>;
113
114 red {
115 gpios = <&gpio1 2 0>;
116 default-state = "on";
117 };
118 };
Shawn Guo082d33d2013-04-02 13:15:16 +0800119};
120
Nicolin Chen48828702013-06-14 13:19:57 +0800121&audmux {
122 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800123 pinctrl-0 = <&pinctrl_audmux>;
Nicolin Chen48828702013-06-14 13:19:57 +0800124 status = "okay";
125};
126
Huang Shijie9110ede2013-06-21 10:19:11 +0800127&ecspi1 {
128 fsl,spi-num-chipselects = <1>;
129 cs-gpios = <&gpio4 9 0>;
130 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800131 pinctrl-0 = <&pinctrl_ecspi1>;
Huang Shijie9110ede2013-06-21 10:19:11 +0800132 status = "okay";
133
134 flash: m25p80@0 {
135 #address-cells = <1>;
136 #size-cells = <1>;
137 compatible = "st,m25p32";
138 spi-max-frequency = <20000000>;
139 reg = <0>;
140 };
141};
142
Shawn Guo082d33d2013-04-02 13:15:16 +0800143&fec {
144 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800145 pinctrl-0 = <&pinctrl_enet>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800146 phy-mode = "rgmii";
Fabio Estevamc5f592d2013-09-27 11:12:41 -0300147 phy-reset-gpios = <&gpio1 25 0>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800148 status = "okay";
149};
150
Fabio Estevamad704562014-04-22 10:04:59 -0300151&hdmi {
152 ddc-i2c-bus = <&i2c2>;
153 status = "okay";
154};
155
Nicolin Chen20426fe2013-06-13 19:51:01 +0800156&i2c1 {
157 clock-frequency = <100000>;
158 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800159 pinctrl-0 = <&pinctrl_i2c1>;
Nicolin Chen20426fe2013-06-13 19:51:01 +0800160 status = "okay";
161
162 codec: wm8962@1a {
163 compatible = "wlf,wm8962";
164 reg = <0x1a>;
Shawn Guoa94f8ec2013-07-18 14:42:28 +0800165 clocks = <&clks 201>;
Nicolin Chen20426fe2013-06-13 19:51:01 +0800166 DCVDD-supply = <&reg_audio>;
167 DBVDD-supply = <&reg_audio>;
168 AVDD-supply = <&reg_audio>;
169 CPVDD-supply = <&reg_audio>;
170 MICVDD-supply = <&reg_audio>;
171 PLLVDD-supply = <&reg_audio>;
172 SPKVDD1-supply = <&reg_audio>;
173 SPKVDD2-supply = <&reg_audio>;
174 gpio-cfg = <
175 0x0000 /* 0:Default */
176 0x0000 /* 1:Default */
177 0x0013 /* 2:FN_DMICCLK */
178 0x0000 /* 3:Default */
179 0x8014 /* 4:FN_DMICCDAT */
180 0x0000 /* 5:Default */
181 >;
182 };
183};
184
Fabio Estevam4b444bb2013-12-24 01:04:49 -0200185&i2c2 {
186 clock-frequency = <100000>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_i2c2>;
189 status = "okay";
190
191 pmic: pfuze100@08 {
192 compatible = "fsl,pfuze100";
193 reg = <0x08>;
194
195 regulators {
196 sw1a_reg: sw1ab {
197 regulator-min-microvolt = <300000>;
198 regulator-max-microvolt = <1875000>;
199 regulator-boot-on;
200 regulator-always-on;
201 regulator-ramp-delay = <6250>;
202 };
203
204 sw1c_reg: sw1c {
205 regulator-min-microvolt = <300000>;
206 regulator-max-microvolt = <1875000>;
207 regulator-boot-on;
208 regulator-always-on;
209 regulator-ramp-delay = <6250>;
210 };
211
212 sw2_reg: sw2 {
213 regulator-min-microvolt = <800000>;
214 regulator-max-microvolt = <3300000>;
215 regulator-boot-on;
216 regulator-always-on;
217 };
218
219 sw3a_reg: sw3a {
220 regulator-min-microvolt = <400000>;
221 regulator-max-microvolt = <1975000>;
222 regulator-boot-on;
223 regulator-always-on;
224 };
225
226 sw3b_reg: sw3b {
227 regulator-min-microvolt = <400000>;
228 regulator-max-microvolt = <1975000>;
229 regulator-boot-on;
230 regulator-always-on;
231 };
232
233 sw4_reg: sw4 {
234 regulator-min-microvolt = <800000>;
235 regulator-max-microvolt = <3300000>;
236 };
237
238 swbst_reg: swbst {
239 regulator-min-microvolt = <5000000>;
240 regulator-max-microvolt = <5150000>;
241 };
242
243 snvs_reg: vsnvs {
244 regulator-min-microvolt = <1000000>;
245 regulator-max-microvolt = <3000000>;
246 regulator-boot-on;
247 regulator-always-on;
248 };
249
250 vref_reg: vrefddr {
251 regulator-boot-on;
252 regulator-always-on;
253 };
254
255 vgen1_reg: vgen1 {
256 regulator-min-microvolt = <800000>;
257 regulator-max-microvolt = <1550000>;
258 };
259
260 vgen2_reg: vgen2 {
261 regulator-min-microvolt = <800000>;
262 regulator-max-microvolt = <1550000>;
263 };
264
265 vgen3_reg: vgen3 {
266 regulator-min-microvolt = <1800000>;
267 regulator-max-microvolt = <3300000>;
268 };
269
270 vgen4_reg: vgen4 {
271 regulator-min-microvolt = <1800000>;
272 regulator-max-microvolt = <3300000>;
273 regulator-always-on;
274 };
275
276 vgen5_reg: vgen5 {
277 regulator-min-microvolt = <1800000>;
278 regulator-max-microvolt = <3300000>;
279 regulator-always-on;
280 };
281
282 vgen6_reg: vgen6 {
283 regulator-min-microvolt = <1800000>;
284 regulator-max-microvolt = <3300000>;
285 regulator-always-on;
286 };
287 };
288 };
289};
290
Fabio Estevam38501172013-07-24 17:20:03 -0300291&i2c3 {
292 clock-frequency = <100000>;
293 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800294 pinctrl-0 = <&pinctrl_i2c3>;
Fabio Estevam38501172013-07-24 17:20:03 -0300295 status = "okay";
296
297 egalax_ts@04 {
298 compatible = "eeti,egalax_ts";
299 reg = <0x04>;
300 interrupt-parent = <&gpio6>;
301 interrupts = <7 2>;
302 wakeup-gpios = <&gpio6 7 0>;
303 };
304};
305
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800306&iomuxc {
307 pinctrl-names = "default";
308 pinctrl-0 = <&pinctrl_hog>;
309
Shawn Guo817c27a2013-10-23 15:36:09 +0800310 imx6qdl-sabresd {
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800311 pinctrl_hog: hoggrp {
312 fsl,pins = <
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800313 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
314 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
315 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
316 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
317 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
Fabio Estevam38501172013-07-24 17:20:03 -0300318 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
Peter Chen015fa462013-08-12 16:46:24 +0800319 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
Peter Chene3c68c82013-08-12 16:51:39 +0800320 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
Fabio Estevamc5f592d2013-09-27 11:12:41 -0300321 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800322 >;
323 };
Shawn Guo817c27a2013-10-23 15:36:09 +0800324
325 pinctrl_audmux: audmuxgrp {
326 fsl,pins = <
Nicolin Chen77112dd2014-02-08 10:14:28 +0800327 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
328 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
329 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
330 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
Shawn Guo817c27a2013-10-23 15:36:09 +0800331 >;
332 };
333
334 pinctrl_ecspi1: ecspi1grp {
335 fsl,pins = <
336 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
337 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
338 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
339 >;
340 };
341
342 pinctrl_enet: enetgrp {
343 fsl,pins = <
344 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
345 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
346 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
347 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
348 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
349 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
350 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
351 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
352 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
353 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
354 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
355 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
356 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
357 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
358 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
359 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
360 >;
361 };
362
Anson Huang8e4422a2013-12-19 16:07:24 -0500363 pinctrl_gpio_keys: gpio_keysgrp {
364 fsl,pins = <
365 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
366 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
367 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
368 >;
369 };
370
Shawn Guo817c27a2013-10-23 15:36:09 +0800371 pinctrl_i2c1: i2c1grp {
372 fsl,pins = <
373 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
374 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
375 >;
376 };
377
Fabio Estevam4b444bb2013-12-24 01:04:49 -0200378 pinctrl_i2c2: i2c2grp {
379 fsl,pins = <
380 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
381 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
382 >;
383 };
384
Shawn Guo817c27a2013-10-23 15:36:09 +0800385 pinctrl_i2c3: i2c3grp {
386 fsl,pins = <
387 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
388 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
389 >;
390 };
391
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200392 pinctrl_pcie: pciegrp {
393 fsl,pins = <
394 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
395 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
396 >;
397 };
398
Shawn Guo817c27a2013-10-23 15:36:09 +0800399 pinctrl_pwm1: pwm1grp {
400 fsl,pins = <
401 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
402 >;
403 };
404
405 pinctrl_uart1: uart1grp {
406 fsl,pins = <
407 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
408 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
409 >;
410 };
411
412 pinctrl_usbotg: usbotggrp {
413 fsl,pins = <
414 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
415 >;
416 };
417
418 pinctrl_usdhc2: usdhc2grp {
419 fsl,pins = <
420 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
421 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
422 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
423 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
424 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
425 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
426 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
427 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
428 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
429 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
430 >;
431 };
432
433 pinctrl_usdhc3: usdhc3grp {
434 fsl,pins = <
435 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
436 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
437 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
438 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
439 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
440 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
441 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
442 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
443 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
444 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
445 >;
446 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800447 };
Vincent Stehlé702bfbe2014-03-05 19:58:39 +0100448
449 gpio_leds {
450 pinctrl_gpio_leds: gpioledsgrp {
451 fsl,pins = <
452 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
453 >;
454 };
455 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800456};
457
Shawn Guob7fb7102013-07-16 22:15:18 +0800458&ldb {
459 status = "okay";
460
461 lvds-channel@1 {
462 fsl,data-mapping = "spwg";
463 fsl,data-width = <18>;
464 status = "okay";
465
466 display-timings {
467 native-mode = <&timing0>;
468 timing0: hsd100pxn1 {
469 clock-frequency = <65000000>;
470 hactive = <1024>;
471 vactive = <768>;
472 hback-porch = <220>;
473 hfront-porch = <40>;
474 vback-porch = <21>;
475 vfront-porch = <7>;
476 hsync-len = <60>;
477 vsync-len = <10>;
478 };
479 };
480 };
481};
482
Marek Vasut9d4ebb32014-04-21 22:56:49 +0200483&pcie {
484 pinctrl-names = "default";
485 pinctrl-0 = <&pinctrl_pcie>;
486 power-on-gpio = <&gpio3 19 0>;
487 reset-gpio = <&gpio7 12 0>;
488 status = "okay";
489};
490
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300491&pwm1 {
492 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800493 pinctrl-0 = <&pinctrl_pwm1>;
Rogerio Pimentel2f35c0c2013-10-11 16:48:16 -0300494 status = "okay";
495};
496
Nicolin Chen48828702013-06-14 13:19:57 +0800497&ssi2 {
498 fsl,mode = "i2s-slave";
499 status = "okay";
500};
501
Shawn Guo082d33d2013-04-02 13:15:16 +0800502&uart1 {
503 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800504 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800505 status = "okay";
506};
507
508&usbh1 {
Peter Chen015fa462013-08-12 16:46:24 +0800509 vbus-supply = <&reg_usb_h1_vbus>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800510 status = "okay";
511};
512
513&usbotg {
514 vbus-supply = <&reg_usb_otg_vbus>;
515 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800516 pinctrl-0 = <&pinctrl_usbotg>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800517 disable-over-current;
518 status = "okay";
519};
520
521&usdhc2 {
522 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800523 pinctrl-0 = <&pinctrl_usdhc2>;
Fabio Estevame3678172013-09-17 13:46:23 -0300524 bus-width = <8>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800525 cd-gpios = <&gpio2 2 0>;
526 wp-gpios = <&gpio2 3 0>;
527 status = "okay";
528};
529
530&usdhc3 {
531 pinctrl-names = "default";
Shawn Guo817c27a2013-10-23 15:36:09 +0800532 pinctrl-0 = <&pinctrl_usdhc3>;
Fabio Estevame3678172013-09-17 13:46:23 -0300533 bus-width = <8>;
Shawn Guo082d33d2013-04-02 13:15:16 +0800534 cd-gpios = <&gpio2 0 0>;
535 wp-gpios = <&gpio2 1 0>;
536 status = "okay";
537};