blob: 3d6ba4bbc55dbf89c251135414533a0476b99579 [file] [log] [blame]
Joseph Loa1425d42013-10-08 12:50:06 +08001/dts-v1/;
2
3#include "tegra124.dtsi"
4
5/ {
6 model = "NVIDIA Tegra124 Venice2";
7 compatible = "nvidia,venice2", "nvidia,tegra124";
8
9 memory {
10 reg = <0x80000000 0x80000000>;
11 };
12
13 serial@70006000 {
14 status = "okay";
15 };
16
Stephen Warren9d5b2502013-12-03 16:44:35 -070017 i2c@7000c000 {
18 status = "okay";
19 clock-frequency = <100000>;
20 };
21
22 i2c@7000c400 {
23 status = "okay";
24 clock-frequency = <100000>;
25 };
26
27 i2c@7000c500 {
28 status = "okay";
29 clock-frequency = <100000>;
30 };
31
32 i2c@7000c700 {
33 status = "okay";
34 clock-frequency = <100000>;
35 };
36
37 i2c@7000d000 {
38 status = "okay";
39 clock-frequency = <100000>;
40 };
41
Joseph Loa1425d42013-10-08 12:50:06 +080042 pmc@7000e400 {
43 nvidia,invert-interrupt;
Joseph Lo6ec1d122013-10-11 17:58:39 +080044 nvidia,suspend-mode = <1>;
45 nvidia,cpu-pwr-good-time = <500>;
46 nvidia,cpu-pwr-off-time = <300>;
47 nvidia,core-pwr-good-time = <641 3845>;
48 nvidia,core-pwr-off-time = <61036>;
49 nvidia,core-power-req-active-high;
50 nvidia,sys-clock-req-active-high;
Joseph Loa1425d42013-10-08 12:50:06 +080051 };
Joseph Lo3b86baf2013-10-08 15:47:40 +080052
Stephen Warren784c7442013-10-31 17:23:05 -060053 sdhci@700b0400 {
54 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
55 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
56 status = "okay";
57 bus-width = <4>;
58 };
59
60 sdhci@700b0600 {
61 status = "okay";
62 bus-width = <8>;
63 };
64
Joseph Lo3b86baf2013-10-08 15:47:40 +080065 clocks {
66 compatible = "simple-bus";
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 clk32k_in: clock@0 {
71 compatible = "fixed-clock";
72 reg=<0>;
73 #clock-cells = <0>;
74 clock-frequency = <32768>;
75 };
76 };
Joseph Loa1425d42013-10-08 12:50:06 +080077};