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gerrit-public.fairphone.software / kernel / msm-4.19 / 9d6c1dc4f9136227b39faf98ae46d0228fe1fa19 / . / drivers / media / i2c / smiapp-pll.h
blob: b98d143b64e1821e31c3dff993918e852c13832b [file] [log] [blame]
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]1/*
Mauro Carvalho Chehabcb7a01a2012-08-14 16:23:43 -0300[diff] [blame]2 * drivers/media/i2c/smiapp-pll.h
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]3 *
4 * Generic driver for SMIA/SMIA++ compliant camera modules
5 *
6 * Copyright (C) 2012 Nokia Corporation
Sakari Ailus8c5dff92012-10-28 06:44:17 -0300[diff] [blame]7 * Contact: Sakari Ailus <sakari.ailus@iki.fi>
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]17 */
18
19#ifndef SMIAPP_PLL_H
20#define SMIAPP_PLL_H
21
Sakari Ailusf5984bb2012-10-20 10:35:25 -0300[diff] [blame]22/* CSI-2 or CCP-2 */
23#define SMIAPP_PLL_BUS_TYPE_CSI2 0x00
24#define SMIAPP_PLL_BUS_TYPE_PARALLEL 0x01
25
26/* op pix clock is for all lanes in total normally */
27#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
28#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
29
Sakari Ailuse3f8bc82014-09-16 09:07:11 -0300[diff] [blame]30struct smiapp_pll_branch {
31 uint16_t sys_clk_div;
32 uint16_t pix_clk_div;
33 uint32_t sys_clk_freq_hz;
34 uint32_t pix_clk_freq_hz;
35};
36
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]37struct smiapp_pll {
Sakari Ailusf5984bb2012-10-20 10:35:25 -0300[diff] [blame]38 /* input values */
39 uint8_t bus_type;
40 union {
41 struct {
42 uint8_t lanes;
43 } csi2;
44 struct {
45 uint8_t bus_width;
46 } parallel;
47 };
Sakari Ailus19e9f5f2014-04-08 18:14:42 -0300[diff] [blame]48 unsigned long flags;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]49 uint8_t binning_horizontal;
50 uint8_t binning_vertical;
51 uint8_t scale_m;
52 uint8_t scale_n;
53 uint8_t bits_per_pixel;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]54 uint32_t link_freq;
Sakari Ailusfff888c2014-09-16 09:04:35 -0300[diff] [blame]55 uint32_t ext_clk_freq_hz;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]56
Sakari Ailusf5984bb2012-10-20 10:35:25 -0300[diff] [blame]57 /* output values */
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]58 uint16_t pre_pll_clk_div;
59 uint16_t pll_multiplier;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]60 uint32_t pll_ip_clk_freq_hz;
61 uint32_t pll_op_clk_freq_hz;
Sakari Ailuse3f8bc82014-09-16 09:07:11 -0300[diff] [blame]62 struct smiapp_pll_branch vt;
63 struct smiapp_pll_branch op;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]64
65 uint32_t pixel_rate_csi;
Sakari Ailuse7c329a2014-04-01 19:18:09 -0300[diff] [blame]66 uint32_t pixel_rate_pixel_array;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]67};
68
Laurent Pinchart6ec84a22012-10-22 11:40:56 -0300[diff] [blame]69struct smiapp_pll_branch_limits {
70 uint16_t min_sys_clk_div;
71 uint16_t max_sys_clk_div;
72 uint32_t min_sys_clk_freq_hz;
73 uint32_t max_sys_clk_freq_hz;
74 uint16_t min_pix_clk_div;
75 uint16_t max_pix_clk_div;
76 uint32_t min_pix_clk_freq_hz;
77 uint32_t max_pix_clk_freq_hz;
78};
79
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]80struct smiapp_pll_limits {
81 /* Strict PLL limits */
82 uint32_t min_ext_clk_freq_hz;
83 uint32_t max_ext_clk_freq_hz;
84 uint16_t min_pre_pll_clk_div;
85 uint16_t max_pre_pll_clk_div;
86 uint32_t min_pll_ip_freq_hz;
87 uint32_t max_pll_ip_freq_hz;
88 uint16_t min_pll_multiplier;
89 uint16_t max_pll_multiplier;
90 uint32_t min_pll_op_freq_hz;
91 uint32_t max_pll_op_freq_hz;
92
Laurent Pinchart6ec84a22012-10-22 11:40:56 -0300[diff] [blame]93 struct smiapp_pll_branch_limits vt;
94 struct smiapp_pll_branch_limits op;
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]95
96 /* Other relevant limits */
97 uint32_t min_line_length_pck_bin;
98 uint32_t min_line_length_pck;
99};
100
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]101struct device;
102
Laurent Pinchart8f7e91a2012-10-22 11:40:57 -0300[diff] [blame]103int smiapp_pll_calculate(struct device *dev,
104 const struct smiapp_pll_limits *limits,
Sakari Ailuscf1c5fa2011-12-07 13:45:25 -0300[diff] [blame]105 struct smiapp_pll *pll);
106
107#endif /* SMIAPP_PLL_H */