Thomas Petazzoni | a47172e | 2014-02-17 15:23:29 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Device Tree file for Marvell Armada 385 evaluation board |
| 3 | * (DB-88F6820) |
| 4 | * |
| 5 | * Copyright (C) 2014 Marvell |
| 6 | * |
| 7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
| 14 | /dts-v1/; |
| 15 | #include "armada-385.dtsi" |
| 16 | |
| 17 | / { |
| 18 | model = "Marvell Armada 385 Development Board"; |
| 19 | compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x"; |
| 20 | |
| 21 | chosen { |
| 22 | bootargs = "console=ttyS0,115200 earlyprintk"; |
| 23 | }; |
| 24 | |
| 25 | memory { |
| 26 | device_type = "memory"; |
| 27 | reg = <0x00000000 0x10000000>; /* 256 MB */ |
| 28 | }; |
| 29 | |
| 30 | soc { |
| 31 | ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 |
| 32 | MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; |
| 33 | |
| 34 | internal-regs { |
| 35 | spi@10600 { |
| 36 | status = "okay"; |
| 37 | |
| 38 | spi-flash@0 { |
| 39 | #address-cells = <1>; |
| 40 | #size-cells = <1>; |
| 41 | compatible = "w25q32"; |
| 42 | reg = <0>; /* Chip select 0 */ |
| 43 | spi-max-frequency = <108000000>; |
| 44 | }; |
| 45 | }; |
| 46 | |
| 47 | i2c@11000 { |
| 48 | status = "okay"; |
| 49 | clock-frequency = <100000>; |
| 50 | }; |
| 51 | |
| 52 | i2c@11100 { |
| 53 | status = "okay"; |
| 54 | clock-frequency = <100000>; |
| 55 | }; |
| 56 | |
| 57 | serial@12000 { |
Thomas Petazzoni | a47172e | 2014-02-17 15:23:29 +0100 | [diff] [blame] | 58 | status = "okay"; |
| 59 | }; |
| 60 | |
| 61 | ethernet@30000 { |
| 62 | status = "okay"; |
| 63 | phy = <&phy1>; |
Thomas Petazzoni | 0d2e637 | 2014-03-06 15:41:55 +0100 | [diff] [blame] | 64 | phy-mode = "rgmii-id"; |
Thomas Petazzoni | a47172e | 2014-02-17 15:23:29 +0100 | [diff] [blame] | 65 | }; |
| 66 | |
Gregory CLEMENT | 9e81775 | 2014-05-15 12:17:40 +0200 | [diff] [blame^] | 67 | usb@50000 { |
| 68 | status = "ok"; |
| 69 | }; |
| 70 | |
Thomas Petazzoni | a47172e | 2014-02-17 15:23:29 +0100 | [diff] [blame] | 71 | ethernet@70000 { |
| 72 | status = "okay"; |
| 73 | phy = <&phy0>; |
Thomas Petazzoni | 0d2e637 | 2014-03-06 15:41:55 +0100 | [diff] [blame] | 74 | phy-mode = "rgmii-id"; |
Thomas Petazzoni | a47172e | 2014-02-17 15:23:29 +0100 | [diff] [blame] | 75 | }; |
| 76 | |
| 77 | mdio { |
| 78 | phy0: ethernet-phy@0 { |
| 79 | reg = <0>; |
| 80 | }; |
| 81 | |
| 82 | phy1: ethernet-phy@1 { |
| 83 | reg = <1>; |
| 84 | }; |
| 85 | }; |
Ezequiel Garcia | 4de29e6 | 2014-03-13 17:24:32 -0300 | [diff] [blame] | 86 | |
Thomas Petazzoni | d175b6e | 2014-04-15 17:00:04 +0200 | [diff] [blame] | 87 | sata@a8000 { |
| 88 | status = "okay"; |
| 89 | }; |
| 90 | |
| 91 | sata@e0000 { |
| 92 | status = "okay"; |
| 93 | }; |
| 94 | |
Ezequiel Garcia | 4de29e6 | 2014-03-13 17:24:32 -0300 | [diff] [blame] | 95 | flash@d0000 { |
| 96 | status = "okay"; |
| 97 | num-cs = <1>; |
| 98 | marvell,nand-keep-config; |
| 99 | marvell,nand-enable-arbiter; |
| 100 | nand-on-flash-bbt; |
| 101 | |
| 102 | partition@0 { |
| 103 | label = "U-Boot"; |
| 104 | reg = <0 0x800000>; |
| 105 | }; |
| 106 | partition@800000 { |
| 107 | label = "Linux"; |
| 108 | reg = <0x800000 0x800000>; |
| 109 | }; |
| 110 | partition@1000000 { |
| 111 | label = "Filesystem"; |
| 112 | reg = <0x1000000 0x3f000000>; |
| 113 | }; |
| 114 | }; |
Thomas Petazzoni | 6eccc52 | 2014-04-14 16:41:16 +0200 | [diff] [blame] | 115 | |
| 116 | sdhci@d8000 { |
| 117 | clock-frequency = <200000000>; |
| 118 | broken-cd; |
| 119 | wp-inverted; |
| 120 | bus-width = <8>; |
| 121 | status = "okay"; |
| 122 | }; |
Gregory CLEMENT | 87e2fc3 | 2014-05-15 12:17:39 +0200 | [diff] [blame] | 123 | |
| 124 | usb3@f0000 { |
| 125 | status = "okay"; |
| 126 | }; |
| 127 | |
| 128 | usb3@f8000 { |
| 129 | status = "okay"; |
| 130 | }; |
Thomas Petazzoni | a47172e | 2014-02-17 15:23:29 +0100 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | pcie-controller { |
| 134 | status = "okay"; |
| 135 | /* |
| 136 | * The two PCIe units are accessible through |
| 137 | * standard PCIe slots on the board. |
| 138 | */ |
| 139 | pcie@1,0 { |
| 140 | /* Port 0, Lane 0 */ |
| 141 | status = "okay"; |
| 142 | }; |
| 143 | pcie@2,0 { |
| 144 | /* Port 1, Lane 0 */ |
| 145 | status = "okay"; |
| 146 | }; |
| 147 | }; |
| 148 | }; |
| 149 | }; |