Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #include <linux/seq_file.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 30 | #include <drm/drmP.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 31 | #include "radeon.h" |
Daniel Vetter | e699037 | 2010-03-11 21:19:17 +0000 | [diff] [blame] | 32 | #include "radeon_asic.h" |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 33 | #include "rs400d.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 34 | |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 35 | /* This files gather functions specifics to : rs400,rs480 */ |
| 36 | static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 37 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 38 | void rs400_gart_adjust_size(struct radeon_device *rdev) |
| 39 | { |
| 40 | /* Check gart size */ |
| 41 | switch (rdev->mc.gtt_size/(1024*1024)) { |
| 42 | case 32: |
| 43 | case 64: |
| 44 | case 128: |
| 45 | case 256: |
| 46 | case 512: |
| 47 | case 1024: |
| 48 | case 2048: |
| 49 | break; |
| 50 | default: |
| 51 | DRM_ERROR("Unable to use IGP GART size %uM\n", |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 52 | (unsigned)(rdev->mc.gtt_size >> 20)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 53 | DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); |
| 54 | DRM_ERROR("Forcing to 32M GART size\n"); |
| 55 | rdev->mc.gtt_size = 32 * 1024 * 1024; |
| 56 | return; |
| 57 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 58 | } |
| 59 | |
| 60 | void rs400_gart_tlb_flush(struct radeon_device *rdev) |
| 61 | { |
| 62 | uint32_t tmp; |
| 63 | unsigned int timeout = rdev->usec_timeout; |
| 64 | |
| 65 | WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); |
| 66 | do { |
| 67 | tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); |
| 68 | if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) |
| 69 | break; |
| 70 | DRM_UDELAY(1); |
| 71 | timeout--; |
| 72 | } while (timeout > 0); |
| 73 | WREG32_MC(RS480_GART_CACHE_CNTRL, 0); |
| 74 | } |
| 75 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 76 | int rs400_gart_init(struct radeon_device *rdev) |
| 77 | { |
| 78 | int r; |
| 79 | |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 80 | if (rdev->gart.ptr) { |
Joe Perches | fce7d61 | 2010-10-30 21:08:30 +0000 | [diff] [blame] | 81 | WARN(1, "RS400 GART already initialized\n"); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 82 | return 0; |
| 83 | } |
| 84 | /* Check gart size */ |
| 85 | switch(rdev->mc.gtt_size / (1024 * 1024)) { |
| 86 | case 32: |
| 87 | case 64: |
| 88 | case 128: |
| 89 | case 256: |
| 90 | case 512: |
| 91 | case 1024: |
| 92 | case 2048: |
| 93 | break; |
| 94 | default: |
| 95 | return -EINVAL; |
| 96 | } |
| 97 | /* Initialize common gart structure */ |
| 98 | r = radeon_gart_init(rdev); |
| 99 | if (r) |
| 100 | return r; |
| 101 | if (rs400_debugfs_pcie_gart_info_init(rdev)) |
| 102 | DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); |
| 103 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
| 104 | return radeon_gart_table_ram_alloc(rdev); |
| 105 | } |
| 106 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 107 | int rs400_gart_enable(struct radeon_device *rdev) |
| 108 | { |
| 109 | uint32_t size_reg; |
| 110 | uint32_t tmp; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 111 | |
| 112 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
| 113 | tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; |
| 114 | WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); |
| 115 | /* Check gart size */ |
| 116 | switch(rdev->mc.gtt_size / (1024 * 1024)) { |
| 117 | case 32: |
| 118 | size_reg = RS480_VA_SIZE_32MB; |
| 119 | break; |
| 120 | case 64: |
| 121 | size_reg = RS480_VA_SIZE_64MB; |
| 122 | break; |
| 123 | case 128: |
| 124 | size_reg = RS480_VA_SIZE_128MB; |
| 125 | break; |
| 126 | case 256: |
| 127 | size_reg = RS480_VA_SIZE_256MB; |
| 128 | break; |
| 129 | case 512: |
| 130 | size_reg = RS480_VA_SIZE_512MB; |
| 131 | break; |
| 132 | case 1024: |
| 133 | size_reg = RS480_VA_SIZE_1GB; |
| 134 | break; |
| 135 | case 2048: |
| 136 | size_reg = RS480_VA_SIZE_2GB; |
| 137 | break; |
| 138 | default: |
| 139 | return -EINVAL; |
| 140 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 141 | /* It should be fine to program it to max value */ |
| 142 | if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { |
| 143 | WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); |
| 144 | WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); |
| 145 | } else { |
| 146 | WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); |
| 147 | WREG32(RS480_AGP_BASE_2, 0); |
| 148 | } |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 149 | tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); |
| 150 | tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 151 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { |
| 152 | WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); |
| 153 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
| 154 | WREG32(RADEON_BUS_CNTL, tmp); |
| 155 | } else { |
| 156 | WREG32(RADEON_MC_AGP_LOCATION, tmp); |
| 157 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
| 158 | WREG32(RADEON_BUS_CNTL, tmp); |
| 159 | } |
| 160 | /* Table should be in 32bits address space so ignore bits above. */ |
Dave Airlie | ed10f95 | 2009-06-29 18:29:11 +1000 | [diff] [blame] | 161 | tmp = (u32)rdev->gart.table_addr & 0xfffff000; |
| 162 | tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; |
| 163 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 164 | WREG32_MC(RS480_GART_BASE, tmp); |
| 165 | /* TODO: more tweaking here */ |
| 166 | WREG32_MC(RS480_GART_FEATURE_ID, |
| 167 | (RS480_TLB_ENABLE | |
| 168 | RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); |
| 169 | /* Disable snooping */ |
| 170 | WREG32_MC(RS480_AGP_MODE_CNTL, |
| 171 | (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); |
| 172 | /* Disable AGP mode */ |
| 173 | /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, |
| 174 | * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ |
| 175 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { |
Alex Deucher | acf88de | 2013-08-26 17:52:12 -0400 | [diff] [blame] | 176 | tmp = RREG32_MC(RS480_MC_MISC_CNTL); |
| 177 | tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN; |
| 178 | WREG32_MC(RS480_MC_MISC_CNTL, tmp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 179 | } else { |
Alex Deucher | acf88de | 2013-08-26 17:52:12 -0400 | [diff] [blame] | 180 | tmp = RREG32_MC(RS480_MC_MISC_CNTL); |
| 181 | tmp |= RS480_GART_INDEX_REG_EN; |
| 182 | WREG32_MC(RS480_MC_MISC_CNTL, tmp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 183 | } |
| 184 | /* Enable gart */ |
| 185 | WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); |
| 186 | rs400_gart_tlb_flush(rdev); |
Tormod Volden | fcf4de5 | 2011-08-31 21:54:07 +0000 | [diff] [blame] | 187 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
| 188 | (unsigned)(rdev->mc.gtt_size >> 20), |
| 189 | (unsigned long long)rdev->gart.table_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 190 | rdev->gart.ready = true; |
| 191 | return 0; |
| 192 | } |
| 193 | |
| 194 | void rs400_gart_disable(struct radeon_device *rdev) |
| 195 | { |
| 196 | uint32_t tmp; |
| 197 | |
| 198 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
| 199 | tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; |
| 200 | WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); |
| 201 | WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); |
| 202 | } |
| 203 | |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 204 | void rs400_gart_fini(struct radeon_device *rdev) |
| 205 | { |
Jerome Glisse | f927456 | 2010-03-17 14:44:29 +0000 | [diff] [blame] | 206 | radeon_gart_fini(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 207 | rs400_gart_disable(rdev); |
| 208 | radeon_gart_table_ram_free(rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 209 | } |
| 210 | |
Michel Dänzer | 77497f2 | 2014-07-17 19:01:07 +0900 | [diff] [blame] | 211 | #define RS400_PTE_UNSNOOPED (1 << 0) |
Alex Deucher | d75ee3b | 2011-01-24 23:24:59 -0500 | [diff] [blame] | 212 | #define RS400_PTE_WRITEABLE (1 << 2) |
| 213 | #define RS400_PTE_READABLE (1 << 3) |
| 214 | |
Michel Dänzer | 77497f2 | 2014-07-17 19:01:07 +0900 | [diff] [blame] | 215 | void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, |
| 216 | uint64_t addr, uint32_t flags) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 217 | { |
Dave Airlie | ed10f95 | 2009-06-29 18:29:11 +1000 | [diff] [blame] | 218 | uint32_t entry; |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 219 | u32 *gtt = rdev->gart.ptr; |
Dave Airlie | ed10f95 | 2009-06-29 18:29:11 +1000 | [diff] [blame] | 220 | |
Dave Airlie | ed10f95 | 2009-06-29 18:29:11 +1000 | [diff] [blame] | 221 | entry = (lower_32_bits(addr) & PAGE_MASK) | |
Michel Dänzer | 77497f2 | 2014-07-17 19:01:07 +0900 | [diff] [blame] | 222 | ((upper_32_bits(addr) & 0xff) << 4); |
| 223 | if (flags & RADEON_GART_PAGE_READ) |
| 224 | addr |= RS400_PTE_READABLE; |
| 225 | if (flags & RADEON_GART_PAGE_WRITE) |
| 226 | addr |= RS400_PTE_WRITEABLE; |
| 227 | if (!(flags & RADEON_GART_PAGE_SNOOP)) |
| 228 | entry |= RS400_PTE_UNSNOOPED; |
Dave Airlie | ed10f95 | 2009-06-29 18:29:11 +1000 | [diff] [blame] | 229 | entry = cpu_to_le32(entry); |
Jerome Glisse | c9a1be9 | 2011-11-03 11:16:49 -0400 | [diff] [blame] | 230 | gtt[i] = entry; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 231 | } |
| 232 | |
Dave Airlie | a17538f | 2010-02-05 13:41:54 +1000 | [diff] [blame] | 233 | int rs400_mc_wait_for_idle(struct radeon_device *rdev) |
| 234 | { |
| 235 | unsigned i; |
| 236 | uint32_t tmp; |
| 237 | |
| 238 | for (i = 0; i < rdev->usec_timeout; i++) { |
| 239 | /* read MC_STATUS */ |
Alex Deucher | d75ee3b | 2011-01-24 23:24:59 -0500 | [diff] [blame] | 240 | tmp = RREG32(RADEON_MC_STATUS); |
| 241 | if (tmp & RADEON_MC_IDLE) { |
Dave Airlie | a17538f | 2010-02-05 13:41:54 +1000 | [diff] [blame] | 242 | return 0; |
| 243 | } |
| 244 | DRM_UDELAY(1); |
| 245 | } |
| 246 | return -1; |
| 247 | } |
| 248 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 249 | static void rs400_gpu_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 250 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 251 | /* FIXME: is this correct ? */ |
| 252 | r420_pipes_init(rdev); |
Dave Airlie | a17538f | 2010-02-05 13:41:54 +1000 | [diff] [blame] | 253 | if (rs400_mc_wait_for_idle(rdev)) { |
| 254 | printk(KERN_WARNING "rs400: Failed to wait MC idle while " |
Alex Deucher | d75ee3b | 2011-01-24 23:24:59 -0500 | [diff] [blame] | 255 | "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 256 | } |
| 257 | } |
| 258 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 259 | static void rs400_mc_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 260 | { |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 261 | u64 base; |
| 262 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 263 | rs400_gart_adjust_size(rdev); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 264 | rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 265 | /* DDR for all card after R300 & IGP */ |
| 266 | rdev->mc.vram_is_ddr = true; |
| 267 | rdev->mc.vram_width = 128; |
Dave Airlie | 2a0f891 | 2009-07-11 04:44:47 +1000 | [diff] [blame] | 268 | r100_vram_init_sizes(rdev); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 269 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
| 270 | radeon_vram_location(rdev, &rdev->mc, base); |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 271 | rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 272 | radeon_gtt_location(rdev, &rdev->mc); |
Alex Deucher | b2f8ccd | 2010-03-21 11:09:24 -0400 | [diff] [blame] | 273 | radeon_update_bandwidth_info(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 274 | } |
| 275 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 276 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
| 277 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 278 | unsigned long flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 279 | uint32_t r; |
| 280 | |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 281 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 282 | WREG32(RS480_NB_MC_INDEX, reg & 0xff); |
| 283 | r = RREG32(RS480_NB_MC_DATA); |
| 284 | WREG32(RS480_NB_MC_INDEX, 0xff); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 285 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 286 | return r; |
| 287 | } |
| 288 | |
| 289 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 290 | { |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 291 | unsigned long flags; |
| 292 | |
| 293 | spin_lock_irqsave(&rdev->mc_idx_lock, flags); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 294 | WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); |
| 295 | WREG32(RS480_NB_MC_DATA, (v)); |
| 296 | WREG32(RS480_NB_MC_INDEX, 0xff); |
Alex Deucher | 0a5b7b0 | 2013-09-03 19:00:09 -0400 | [diff] [blame] | 297 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 298 | } |
| 299 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 300 | #if defined(CONFIG_DEBUG_FS) |
| 301 | static int rs400_debugfs_gart_info(struct seq_file *m, void *data) |
| 302 | { |
| 303 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
| 304 | struct drm_device *dev = node->minor->dev; |
| 305 | struct radeon_device *rdev = dev->dev_private; |
| 306 | uint32_t tmp; |
| 307 | |
| 308 | tmp = RREG32(RADEON_HOST_PATH_CNTL); |
| 309 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); |
| 310 | tmp = RREG32(RADEON_BUS_CNTL); |
| 311 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); |
| 312 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
| 313 | seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); |
| 314 | if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { |
| 315 | tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); |
| 316 | seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); |
| 317 | tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); |
| 318 | seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); |
| 319 | tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); |
| 320 | seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); |
Alex Deucher | d75ee3b | 2011-01-24 23:24:59 -0500 | [diff] [blame] | 321 | tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 322 | seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); |
Alex Deucher | d75ee3b | 2011-01-24 23:24:59 -0500 | [diff] [blame] | 323 | tmp = RREG32(RS690_HDP_FB_LOCATION); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 324 | seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); |
| 325 | } else { |
| 326 | tmp = RREG32(RADEON_AGP_BASE); |
| 327 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); |
| 328 | tmp = RREG32(RS480_AGP_BASE_2); |
| 329 | seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); |
| 330 | tmp = RREG32(RADEON_MC_AGP_LOCATION); |
| 331 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); |
| 332 | } |
| 333 | tmp = RREG32_MC(RS480_GART_BASE); |
| 334 | seq_printf(m, "GART_BASE 0x%08x\n", tmp); |
| 335 | tmp = RREG32_MC(RS480_GART_FEATURE_ID); |
| 336 | seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); |
| 337 | tmp = RREG32_MC(RS480_AGP_MODE_CNTL); |
| 338 | seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); |
| 339 | tmp = RREG32_MC(RS480_MC_MISC_CNTL); |
| 340 | seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); |
| 341 | tmp = RREG32_MC(0x5F); |
| 342 | seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); |
| 343 | tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); |
| 344 | seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); |
| 345 | tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); |
| 346 | seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); |
| 347 | tmp = RREG32_MC(0x3B); |
| 348 | seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); |
| 349 | tmp = RREG32_MC(0x3C); |
| 350 | seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); |
| 351 | tmp = RREG32_MC(0x30); |
| 352 | seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); |
| 353 | tmp = RREG32_MC(0x31); |
| 354 | seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); |
| 355 | tmp = RREG32_MC(0x32); |
| 356 | seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); |
| 357 | tmp = RREG32_MC(0x33); |
| 358 | seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); |
| 359 | tmp = RREG32_MC(0x34); |
| 360 | seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); |
| 361 | tmp = RREG32_MC(0x35); |
| 362 | seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); |
| 363 | tmp = RREG32_MC(0x36); |
| 364 | seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); |
| 365 | tmp = RREG32_MC(0x37); |
| 366 | seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); |
| 367 | return 0; |
| 368 | } |
| 369 | |
| 370 | static struct drm_info_list rs400_gart_info_list[] = { |
| 371 | {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, |
| 372 | }; |
| 373 | #endif |
| 374 | |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 375 | static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 376 | { |
| 377 | #if defined(CONFIG_DEBUG_FS) |
| 378 | return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); |
| 379 | #else |
| 380 | return 0; |
| 381 | #endif |
| 382 | } |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 383 | |
Lauri Kasanen | 1109ca0 | 2012-08-31 13:43:50 -0400 | [diff] [blame] | 384 | static void rs400_mc_program(struct radeon_device *rdev) |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 385 | { |
| 386 | struct r100_mc_save save; |
| 387 | |
| 388 | /* Stops all mc clients */ |
| 389 | r100_mc_stop(rdev, &save); |
| 390 | |
| 391 | /* Wait for mc idle */ |
Dave Airlie | a17538f | 2010-02-05 13:41:54 +1000 | [diff] [blame] | 392 | if (rs400_mc_wait_for_idle(rdev)) |
| 393 | dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 394 | WREG32(R_000148_MC_FB_LOCATION, |
| 395 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
| 396 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
| 397 | |
| 398 | r100_mc_resume(rdev, &save); |
| 399 | } |
| 400 | |
| 401 | static int rs400_startup(struct radeon_device *rdev) |
| 402 | { |
| 403 | int r; |
| 404 | |
Dave Airlie | 08a370f | 2010-03-31 13:42:50 +1000 | [diff] [blame] | 405 | r100_set_common_regs(rdev); |
| 406 | |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 407 | rs400_mc_program(rdev); |
| 408 | /* Resume clock */ |
| 409 | r300_clock_startup(rdev); |
| 410 | /* Initialize GPU configuration (# pipes, ...) */ |
| 411 | rs400_gpu_init(rdev); |
Dave Airlie | 17e15b0 | 2009-11-05 15:36:53 +1000 | [diff] [blame] | 412 | r100_enable_bm(rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 413 | /* Initialize GART (initialize after TTM so we can allocate |
| 414 | * memory through TTM but finalize after TTM) */ |
| 415 | r = rs400_gart_enable(rdev); |
| 416 | if (r) |
| 417 | return r; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 418 | |
| 419 | /* allocate wb buffer */ |
| 420 | r = radeon_wb_init(rdev); |
| 421 | if (r) |
| 422 | return r; |
| 423 | |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 424 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); |
| 425 | if (r) { |
| 426 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); |
| 427 | return r; |
| 428 | } |
| 429 | |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 430 | /* Enable IRQ */ |
Adis Hamzić | e49f395 | 2013-06-02 16:47:54 +0200 | [diff] [blame] | 431 | if (!rdev->irq.installed) { |
| 432 | r = radeon_irq_kms_init(rdev); |
| 433 | if (r) |
| 434 | return r; |
| 435 | } |
| 436 | |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 437 | r100_irq_set(rdev); |
Jerome Glisse | cafe660 | 2010-01-07 12:39:21 +0100 | [diff] [blame] | 438 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 439 | /* 1M ring buffer */ |
| 440 | r = r100_cp_init(rdev, 1024 * 1024); |
| 441 | if (r) { |
Paul Bolle | ec4f2ac | 2011-01-28 23:32:04 +0100 | [diff] [blame] | 442 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 443 | return r; |
| 444 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 445 | |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 446 | r = radeon_ib_pool_init(rdev); |
| 447 | if (r) { |
| 448 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 449 | return r; |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 450 | } |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 451 | |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 452 | return 0; |
| 453 | } |
| 454 | |
| 455 | int rs400_resume(struct radeon_device *rdev) |
| 456 | { |
Jerome Glisse | 6b7746e | 2012-02-20 17:57:20 -0500 | [diff] [blame] | 457 | int r; |
| 458 | |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 459 | /* Make sur GART are not working */ |
| 460 | rs400_gart_disable(rdev); |
| 461 | /* Resume clock before doing reset */ |
| 462 | r300_clock_startup(rdev); |
Dave Airlie | ea1495a | 2009-10-27 11:57:53 +1100 | [diff] [blame] | 463 | /* setup MC before calling post tables */ |
| 464 | rs400_mc_program(rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 465 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 466 | if (radeon_asic_reset(rdev)) { |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 467 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 468 | RREG32(R_000E40_RBBM_STATUS), |
| 469 | RREG32(R_0007C0_CP_STAT)); |
| 470 | } |
| 471 | /* post */ |
| 472 | radeon_combios_asic_init(rdev->ddev); |
| 473 | /* Resume clock after posting */ |
| 474 | r300_clock_startup(rdev); |
Dave Airlie | 550e2d9 | 2009-12-09 14:15:38 +1000 | [diff] [blame] | 475 | /* Initialize surface registers */ |
| 476 | radeon_surface_init(rdev); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 477 | |
| 478 | rdev->accel_working = true; |
Jerome Glisse | 6b7746e | 2012-02-20 17:57:20 -0500 | [diff] [blame] | 479 | r = rs400_startup(rdev); |
| 480 | if (r) { |
| 481 | rdev->accel_working = false; |
| 482 | } |
| 483 | return r; |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 484 | } |
| 485 | |
| 486 | int rs400_suspend(struct radeon_device *rdev) |
| 487 | { |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 488 | radeon_pm_suspend(rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 489 | r100_cp_disable(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 490 | radeon_wb_disable(rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 491 | r100_irq_disable(rdev); |
| 492 | rs400_gart_disable(rdev); |
| 493 | return 0; |
| 494 | } |
| 495 | |
| 496 | void rs400_fini(struct radeon_device *rdev) |
| 497 | { |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 498 | radeon_pm_fini(rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 499 | r100_cp_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 500 | radeon_wb_fini(rdev); |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 501 | radeon_ib_pool_fini(rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 502 | radeon_gem_fini(rdev); |
| 503 | rs400_gart_fini(rdev); |
| 504 | radeon_irq_kms_fini(rdev); |
| 505 | radeon_fence_driver_fini(rdev); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 506 | radeon_bo_fini(rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 507 | radeon_atombios_fini(rdev); |
| 508 | kfree(rdev->bios); |
| 509 | rdev->bios = NULL; |
| 510 | } |
| 511 | |
| 512 | int rs400_init(struct radeon_device *rdev) |
| 513 | { |
| 514 | int r; |
| 515 | |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 516 | /* Disable VGA */ |
| 517 | r100_vga_render_disable(rdev); |
| 518 | /* Initialize scratch registers */ |
| 519 | radeon_scratch_init(rdev); |
| 520 | /* Initialize surface registers */ |
| 521 | radeon_surface_init(rdev); |
| 522 | /* TODO: disable VGA need to use VGA request */ |
Dave Airlie | 4c712e6 | 2010-07-15 12:13:50 +1000 | [diff] [blame] | 523 | /* restore some register to sane defaults */ |
| 524 | r100_restore_sanity(rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 525 | /* BIOS*/ |
| 526 | if (!radeon_get_bios(rdev)) { |
| 527 | if (ASIC_IS_AVIVO(rdev)) |
| 528 | return -EINVAL; |
| 529 | } |
| 530 | if (rdev->is_atom_bios) { |
| 531 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
| 532 | return -EINVAL; |
| 533 | } else { |
| 534 | r = radeon_combios_init(rdev); |
| 535 | if (r) |
| 536 | return r; |
| 537 | } |
| 538 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 539 | if (radeon_asic_reset(rdev)) { |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 540 | dev_warn(rdev->dev, |
| 541 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
| 542 | RREG32(R_000E40_RBBM_STATUS), |
| 543 | RREG32(R_0007C0_CP_STAT)); |
| 544 | } |
| 545 | /* check if cards are posted or not */ |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 546 | if (radeon_boot_test_post_card(rdev) == false) |
| 547 | return -EINVAL; |
| 548 | |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 549 | /* Initialize clocks */ |
| 550 | radeon_get_clock_info(rdev->ddev); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 551 | /* initialize memory controller */ |
| 552 | rs400_mc_init(rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 553 | /* Fence driver */ |
Jerome Glisse | 30eb77f | 2011-11-20 20:45:34 +0000 | [diff] [blame] | 554 | r = radeon_fence_driver_init(rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 555 | if (r) |
| 556 | return r; |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 557 | /* Memory manager */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 558 | r = radeon_bo_init(rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 559 | if (r) |
| 560 | return r; |
| 561 | r = rs400_gart_init(rdev); |
| 562 | if (r) |
| 563 | return r; |
| 564 | r300_set_reg_safe(rdev); |
Jerome Glisse | b15ba51 | 2011-11-15 11:48:34 -0500 | [diff] [blame] | 565 | |
Alex Deucher | 6c7bcce | 2013-12-18 14:07:14 -0500 | [diff] [blame] | 566 | /* Initialize power management */ |
| 567 | radeon_pm_init(rdev); |
| 568 | |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 569 | rdev->accel_working = true; |
| 570 | r = rs400_startup(rdev); |
| 571 | if (r) { |
| 572 | /* Somethings want wront with the accel init stop accel */ |
| 573 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 574 | r100_cp_fini(rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 575 | radeon_wb_fini(rdev); |
Christian König | 2898c34 | 2012-07-05 11:55:34 +0200 | [diff] [blame] | 576 | radeon_ib_pool_fini(rdev); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 577 | rs400_gart_fini(rdev); |
| 578 | radeon_irq_kms_fini(rdev); |
| 579 | rdev->accel_working = false; |
| 580 | } |
| 581 | return 0; |
| 582 | } |