blob: d195e884b3b529617031250bbe1ecb5184fdd201 [file] [log] [blame]
Andrew Lunne2eaa332014-02-15 13:59:53 +01001/*
2 * Marvell RD88F6181 Common Board descrition
3 *
4 * Andrew Lunn <andrew@lunn.ch>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * This file contains the definitions that are common between the two
11 * variants of the Marvell Kirkwood Development Board.
12 */
13
14#include "kirkwood.dtsi"
15#include "kirkwood-6281.dtsi"
16
17/ {
18 memory {
19 device_type = "memory";
20 reg = <0x00000000 0x20000000>;
21 };
22
23 chosen {
24 bootargs = "console=ttyS0,115200n8";
Sebastian Hesselbarthab833612014-04-30 14:56:30 +020025 stdout-path = &uart0;
Andrew Lunne2eaa332014-02-15 13:59:53 +010026 };
27
28 mbus {
29 pcie-controller {
30 status = "okay";
31
32 pcie@1,0 {
33 status = "okay";
34 };
35 };
36 };
37
38 ocp@f1000000 {
Sebastian Hesselbartha9483962014-04-30 14:56:32 +020039 pinctrl: pin-controller@10000 {
Andrew Lunne2eaa332014-02-15 13:59:53 +010040 pinctrl-names = "default";
41
42 pmx_sdio_cd: pmx-sdio-cd {
43 marvell,pins = "mpp28";
44 marvell,function = "gpio";
45 };
46 };
47
48 serial@12000 {
49 status = "okay";
50
51 };
52
53 sata@80000 {
54 status = "okay";
55 nr-ports = <2>;
56 };
57 mvsdio@90000 {
58 pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
59 pinctrl-names = "default";
60 status = "okay";
61 cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
62 /* No WP GPIO */
63 };
64 };
65
66 dsa@0 {
67 compatible = "marvell,dsa";
68 #address-cells = <2>;
69 #size-cells = <0>;
70
Andrew Lunn4f5e01e2014-09-01 19:35:41 +020071 dsa,ethernet = <&eth0port>;
72 dsa,mii-bus = <&mdio>;
Andrew Lunne2eaa332014-02-15 13:59:53 +010073
74 switch@0 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 port@0 {
79 reg = <0>;
80 label = "lan1";
81 };
82
83 port@1 {
84 reg = <1>;
85 label = "lan2";
86 };
87
88 port@2 {
89 reg = <2>;
90 label = "lan3";
91 };
92
93 port@3 {
94 reg = <3>;
95 label = "lan4";
96 };
97
98 port@5 {
99 reg = <5>;
100 label = "cpu";
101 };
102 };
103 };
104};
105
106&nand {
107 status = "okay";
108
109 partition@0 {
110 label = "u-boot";
111 reg = <0x0000000 0x100000>;
112 read-only;
113 };
114
115 partition@100000 {
116 label = "uImage";
117 reg = <0x0100000 0x200000>;
118 };
119
120 partition@300000 {
Andrew Lunn4f5e01e2014-09-01 19:35:41 +0200121 label = "rootfs";
Andrew Lunne2eaa332014-02-15 13:59:53 +0100122 reg = <0x0300000 0x500000>;
123 };
124};
125
126&mdio {
127 status = "okay";
Andrew Lunne2eaa332014-02-15 13:59:53 +0100128};
129
130&eth0 {
131 status = "okay";
132 ethernet0-port@0 {
Andrew Lunn4f5e01e2014-09-01 19:35:41 +0200133 speed = <1000>;
134 duplex = <1>;
Andrew Lunne2eaa332014-02-15 13:59:53 +0100135 };
136};