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Alex Deucherd38ceaf2015-04-20 16:55:21 -04001/*
2 * Copyright © 2007 David Airlie
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * David Airlie
25 */
26#include <linux/module.h>
27#include <linux/slab.h>
Alex Deucher7c1fa1d2016-08-27 12:37:22 -040028#include <linux/pm_runtime.h>
Alex Deucherd38ceaf2015-04-20 16:55:21 -040029
30#include <drm/drmP.h>
31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/amdgpu_drm.h>
34#include "amdgpu.h"
Marek Olšákfbd76d52015-05-14 23:48:26 +020035#include "cikd.h"
Alex Deucherd38ceaf2015-04-20 16:55:21 -040036
37#include <drm/drm_fb_helper.h>
38
39#include <linux/vga_switcheroo.h>
40
41/* object hierarchy -
42 this contains a helper + a amdgpu fb
43 the helper contains a pointer to amdgpu framebuffer baseclass.
44*/
45struct amdgpu_fbdev {
46 struct drm_fb_helper helper;
47 struct amdgpu_framebuffer rfb;
Alex Deucherd38ceaf2015-04-20 16:55:21 -040048 struct amdgpu_device *adev;
49};
50
Alex Deucher7c1fa1d2016-08-27 12:37:22 -040051static int
52amdgpufb_open(struct fb_info *info, int user)
53{
54 struct amdgpu_fbdev *rfbdev = info->par;
55 struct amdgpu_device *adev = rfbdev->adev;
56 int ret = pm_runtime_get_sync(adev->ddev->dev);
57 if (ret < 0 && ret != -EACCES) {
58 pm_runtime_mark_last_busy(adev->ddev->dev);
59 pm_runtime_put_autosuspend(adev->ddev->dev);
60 return ret;
61 }
62 return 0;
63}
64
65static int
66amdgpufb_release(struct fb_info *info, int user)
67{
68 struct amdgpu_fbdev *rfbdev = info->par;
69 struct amdgpu_device *adev = rfbdev->adev;
70
71 pm_runtime_mark_last_busy(adev->ddev->dev);
72 pm_runtime_put_autosuspend(adev->ddev->dev);
73 return 0;
74}
75
Alex Deucherd38ceaf2015-04-20 16:55:21 -040076static struct fb_ops amdgpufb_ops = {
77 .owner = THIS_MODULE,
Stefan Christea4ffff2016-11-14 00:03:13 +010078 DRM_FB_HELPER_DEFAULT_OPS,
Alex Deucher7c1fa1d2016-08-27 12:37:22 -040079 .fb_open = amdgpufb_open,
80 .fb_release = amdgpufb_release,
Archit Taneja2dbaf3922015-07-31 16:22:00 +053081 .fb_fillrect = drm_fb_helper_cfb_fillrect,
82 .fb_copyarea = drm_fb_helper_cfb_copyarea,
83 .fb_imageblit = drm_fb_helper_cfb_imageblit,
Alex Deucherd38ceaf2015-04-20 16:55:21 -040084};
85
86
Laurent Pinchart8e911ab2016-10-18 01:41:17 +030087int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
Alex Deucherd38ceaf2015-04-20 16:55:21 -040088{
89 int aligned = width;
90 int pitch_mask = 0;
91
Laurent Pinchart8e911ab2016-10-18 01:41:17 +030092 switch (cpp) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -040093 case 1:
94 pitch_mask = 255;
95 break;
96 case 2:
97 pitch_mask = 127;
98 break;
99 case 3:
100 case 4:
101 pitch_mask = 63;
102 break;
103 }
104
105 aligned += pitch_mask;
106 aligned &= ~pitch_mask;
Laurent Pinchart8e911ab2016-10-18 01:41:17 +0300107 return aligned * cpp;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400108}
109
110static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
111{
Christian König765e7fb2016-09-15 15:06:50 +0200112 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400113 int ret;
114
Michel Dänzerc81a1a72017-04-28 17:28:14 +0900115 ret = amdgpu_bo_reserve(abo, true);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400116 if (likely(ret == 0)) {
Christian König765e7fb2016-09-15 15:06:50 +0200117 amdgpu_bo_kunmap(abo);
118 amdgpu_bo_unpin(abo);
119 amdgpu_bo_unreserve(abo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400120 }
Cihangir Akturkf62facc2017-08-03 14:58:16 +0300121 drm_gem_object_put_unlocked(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400122}
123
124static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
125 struct drm_mode_fb_cmd2 *mode_cmd,
126 struct drm_gem_object **gobj_p)
127{
128 struct amdgpu_device *adev = rfbdev->adev;
129 struct drm_gem_object *gobj = NULL;
Christian König765e7fb2016-09-15 15:06:50 +0200130 struct amdgpu_bo *abo = NULL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400131 bool fb_tiled = false; /* useful for testing */
132 u32 tiling_flags = 0;
133 int ret;
134 int aligned_size, size;
135 int height = mode_cmd->height;
Laurent Pinchart8e911ab2016-10-18 01:41:17 +0300136 u32 cpp;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400137
Laurent Pinchart8e911ab2016-10-18 01:41:17 +0300138 cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400139
140 /* need to align pitch with crtc limits */
Laurent Pinchart8e911ab2016-10-18 01:41:17 +0300141 mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
142 fb_tiled);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400143
144 height = ALIGN(mode_cmd->height, 8);
145 size = mode_cmd->pitches[0] * height;
146 aligned_size = ALIGN(size, PAGE_SIZE);
147 ret = amdgpu_gem_object_create(adev, aligned_size, 0,
148 AMDGPU_GEM_DOMAIN_VRAM,
Christian König03f48dd2016-08-15 17:00:22 +0200149 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
Pixel Dingcbabc8b2017-01-24 11:39:48 +0800150 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
151 AMDGPU_GEM_CREATE_VRAM_CLEARED,
Alex Deucher857d9132015-08-27 00:14:16 -0400152 true, &gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400153 if (ret) {
Joe Perches7ca85292017-02-28 04:55:52 -0800154 pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400155 return -ENOMEM;
156 }
Christian König765e7fb2016-09-15 15:06:50 +0200157 abo = gem_to_amdgpu_bo(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400158
159 if (fb_tiled)
Marek Olšákfbd76d52015-05-14 23:48:26 +0200160 tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400161
Christian König765e7fb2016-09-15 15:06:50 +0200162 ret = amdgpu_bo_reserve(abo, false);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400163 if (unlikely(ret != 0))
164 goto out_unref;
165
166 if (tiling_flags) {
Christian König765e7fb2016-09-15 15:06:50 +0200167 ret = amdgpu_bo_set_tiling_flags(abo,
Marek Olšák63ab1c22015-05-14 23:03:57 +0200168 tiling_flags);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400169 if (ret)
170 dev_err(adev->dev, "FB failed to set tiling flags\n");
171 }
172
173
Alex Deucher7fe28572016-12-07 16:14:38 -0500174 ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400175 if (ret) {
Christian König765e7fb2016-09-15 15:06:50 +0200176 amdgpu_bo_unreserve(abo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400177 goto out_unref;
178 }
Christian König765e7fb2016-09-15 15:06:50 +0200179 ret = amdgpu_bo_kmap(abo, NULL);
180 amdgpu_bo_unreserve(abo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400181 if (ret) {
182 goto out_unref;
183 }
184
185 *gobj_p = gobj;
186 return 0;
187out_unref:
188 amdgpufb_destroy_pinned_object(gobj);
189 *gobj_p = NULL;
190 return ret;
191}
192
193static int amdgpufb_create(struct drm_fb_helper *helper,
194 struct drm_fb_helper_surface_size *sizes)
195{
196 struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
197 struct amdgpu_device *adev = rfbdev->adev;
198 struct fb_info *info;
199 struct drm_framebuffer *fb = NULL;
200 struct drm_mode_fb_cmd2 mode_cmd;
201 struct drm_gem_object *gobj = NULL;
Christian König765e7fb2016-09-15 15:06:50 +0200202 struct amdgpu_bo *abo = NULL;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400203 int ret;
204 unsigned long tmp;
205
206 mode_cmd.width = sizes->surface_width;
207 mode_cmd.height = sizes->surface_height;
208
209 if (sizes->surface_bpp == 24)
210 sizes->surface_bpp = 32;
211
212 mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
213 sizes->surface_depth);
214
215 ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
216 if (ret) {
217 DRM_ERROR("failed to create fbcon object %d\n", ret);
218 return ret;
219 }
220
Christian König765e7fb2016-09-15 15:06:50 +0200221 abo = gem_to_amdgpu_bo(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400222
223 /* okay we have an object now allocate the framebuffer */
Archit Taneja2dbaf3922015-07-31 16:22:00 +0530224 info = drm_fb_helper_alloc_fbi(helper);
225 if (IS_ERR(info)) {
226 ret = PTR_ERR(info);
Daniel Vetterda7bdda2017-02-07 17:16:03 +0100227 goto out;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400228 }
229
230 info->par = rfbdev;
Alex Deucherdf7989f2015-11-02 10:52:32 -0500231 info->skip_vt_switch = true;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400232
233 ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
234 if (ret) {
235 DRM_ERROR("failed to initialize framebuffer %d\n", ret);
Daniel Vetterda7bdda2017-02-07 17:16:03 +0100236 goto out;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400237 }
238
239 fb = &rfbdev->rfb.base;
240
241 /* setup helper */
242 rfbdev->helper.fb = fb;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400243
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400244 strcpy(info->fix.id, "amdgpudrmfb");
245
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200246 drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400247
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400248 info->fbops = &amdgpufb_ops;
249
Christian König765e7fb2016-09-15 15:06:50 +0200250 tmp = amdgpu_bo_gpu_offset(abo) - adev->mc.vram_start;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400251 info->fix.smem_start = adev->mc.aper_base + tmp;
Christian König765e7fb2016-09-15 15:06:50 +0200252 info->fix.smem_len = amdgpu_bo_size(abo);
Christian Königf5e1c742017-07-20 23:45:18 +0200253 info->screen_base = amdgpu_bo_kptr(abo);
Christian König765e7fb2016-09-15 15:06:50 +0200254 info->screen_size = amdgpu_bo_size(abo);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400255
256 drm_fb_helper_fill_var(info, &rfbdev->helper, sizes->fb_width, sizes->fb_height);
257
258 /* setup aperture base/size for vesafb takeover */
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400259 info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
260 info->apertures->ranges[0].size = adev->mc.aper_size;
261
262 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
263
264 if (info->screen_base == NULL) {
265 ret = -ENOSPC;
Daniel Vetterda7bdda2017-02-07 17:16:03 +0100266 goto out;
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400267 }
268
269 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
270 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->mc.aper_base);
Christian König765e7fb2016-09-15 15:06:50 +0200271 DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
Ville Syrjäläb00c6002016-12-14 23:31:35 +0200272 DRM_INFO("fb depth is %d\n", fb->format->depth);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400273 DRM_INFO(" pitch is %d\n", fb->pitches[0]);
274
275 vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
276 return 0;
277
Daniel Vetterda7bdda2017-02-07 17:16:03 +0100278out:
Christian König765e7fb2016-09-15 15:06:50 +0200279 if (abo) {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400280
281 }
282 if (fb && ret) {
Cihangir Akturkf62facc2017-08-03 14:58:16 +0300283 drm_gem_object_put_unlocked(gobj);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400284 drm_framebuffer_unregister_private(fb);
285 drm_framebuffer_cleanup(fb);
286 kfree(fb);
287 }
288 return ret;
289}
290
291void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev)
292{
293 if (adev->mode_info.rfbdev)
294 drm_fb_helper_hotplug_event(&adev->mode_info.rfbdev->helper);
295}
296
297static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
298{
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400299 struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
300
Archit Taneja2dbaf3922015-07-31 16:22:00 +0530301 drm_fb_helper_unregister_fbi(&rfbdev->helper);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400302
303 if (rfb->obj) {
304 amdgpufb_destroy_pinned_object(rfb->obj);
305 rfb->obj = NULL;
306 }
307 drm_fb_helper_fini(&rfbdev->helper);
308 drm_framebuffer_unregister_private(&rfb->base);
309 drm_framebuffer_cleanup(&rfb->base);
310
311 return 0;
312}
313
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400314static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400315 .fb_probe = amdgpufb_create,
316};
317
318int amdgpu_fbdev_init(struct amdgpu_device *adev)
319{
320 struct amdgpu_fbdev *rfbdev;
321 int bpp_sel = 32;
322 int ret;
323
324 /* don't init fbdev on hw without DCE */
325 if (!adev->mode_info.mode_config_initialized)
326 return 0;
327
Alex Deucherf49d45c2016-01-26 00:30:33 -0500328 /* don't init fbdev if there are no connectors */
329 if (list_empty(&adev->ddev->mode_config.connector_list))
330 return 0;
331
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400332 /* select 8 bpp console on low vram cards */
333 if (adev->mc.real_vram_size <= (32*1024*1024))
334 bpp_sel = 8;
335
336 rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
337 if (!rfbdev)
338 return -ENOMEM;
339
340 rfbdev->adev = adev;
341 adev->mode_info.rfbdev = rfbdev;
342
343 drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
344 &amdgpu_fb_helper_funcs);
345
346 ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper,
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400347 AMDGPUFB_CONN_LIMIT);
348 if (ret) {
349 kfree(rfbdev);
350 return ret;
351 }
352
353 drm_fb_helper_single_add_all_connectors(&rfbdev->helper);
354
355 /* disable all the possible outputs/crtcs before entering KMS mode */
356 drm_helper_disable_unused_functions(adev->ddev);
357
358 drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
359 return 0;
360}
361
362void amdgpu_fbdev_fini(struct amdgpu_device *adev)
363{
364 if (!adev->mode_info.rfbdev)
365 return;
366
367 amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
368 kfree(adev->mode_info.rfbdev);
369 adev->mode_info.rfbdev = NULL;
370}
371
372void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
373{
374 if (adev->mode_info.rfbdev)
Archit Taneja2dbaf3922015-07-31 16:22:00 +0530375 drm_fb_helper_set_suspend(&adev->mode_info.rfbdev->helper,
376 state);
Alex Deucherd38ceaf2015-04-20 16:55:21 -0400377}
378
379int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
380{
381 struct amdgpu_bo *robj;
382 int size = 0;
383
384 if (!adev->mode_info.rfbdev)
385 return 0;
386
387 robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj);
388 size += amdgpu_bo_size(robj);
389 return size;
390}
391
392bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
393{
394 if (!adev->mode_info.rfbdev)
395 return false;
396 if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.obj))
397 return true;
398 return false;
399}
Alex Deucher8b7530b2015-10-02 16:59:34 -0400400
401void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev)
402{
Rex Zhub62ce3972017-05-22 13:11:41 +0800403 struct amdgpu_fbdev *afbdev;
Alex Deucher8b7530b2015-10-02 16:59:34 -0400404 struct drm_fb_helper *fb_helper;
405 int ret;
406
Rex Zhub62ce3972017-05-22 13:11:41 +0800407 if (!adev)
408 return;
409
410 afbdev = adev->mode_info.rfbdev;
411
Alex Deucher8b7530b2015-10-02 16:59:34 -0400412 if (!afbdev)
413 return;
414
415 fb_helper = &afbdev->helper;
416
417 ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper);
418 if (ret)
419 DRM_DEBUG("failed to restore crtc mode\n");
420}