blob: 0857ca981fae38485d15203f69576d0e6dd13887 [file] [log] [blame]
Ben Hutchings94e61082008-03-05 16:52:39 +00001#include <linux/delay.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07002#include <linux/pci.h>
3#include <linux/module.h>
Al Virof6a57032006-10-18 01:47:25 -04004#include <linux/sched.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +09005#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07006#include <linux/ioport.h>
Matthew Wilcox7ea7e982006-10-19 09:41:28 -06007#include <linux/wait.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07008
Adrian Bunk48b19142005-11-06 01:45:08 +01009#include "pci.h"
10
Linus Torvalds1da177e2005-04-16 15:20:36 -070011/*
12 * This interrupt-safe spinlock protects all accesses to PCI
13 * configuration space.
14 */
15
Jan Kiszkaa2e27782011-11-04 09:46:00 +010016DEFINE_RAW_SPINLOCK(pci_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -070017
18/*
19 * Wrappers for all PCI configuration access functions. They just check
20 * alignment, do locking and call the low-level functions pointed to
21 * by pci_dev->ops.
22 */
23
24#define PCI_byte_BAD 0
25#define PCI_word_BAD (pos & 1)
26#define PCI_dword_BAD (pos & 3)
27
28#define PCI_OP_READ(size,type,len) \
29int pci_bus_read_config_##size \
30 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
31{ \
32 int res; \
33 unsigned long flags; \
34 u32 data = 0; \
35 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
Thomas Gleixner511dd982010-02-17 14:35:19 +000036 raw_spin_lock_irqsave(&pci_lock, flags); \
Linus Torvalds1da177e2005-04-16 15:20:36 -070037 res = bus->ops->read(bus, devfn, pos, len, &data); \
38 *value = (type)data; \
Thomas Gleixner511dd982010-02-17 14:35:19 +000039 raw_spin_unlock_irqrestore(&pci_lock, flags); \
Linus Torvalds1da177e2005-04-16 15:20:36 -070040 return res; \
41}
42
43#define PCI_OP_WRITE(size,type,len) \
44int pci_bus_write_config_##size \
45 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
46{ \
47 int res; \
48 unsigned long flags; \
49 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
Thomas Gleixner511dd982010-02-17 14:35:19 +000050 raw_spin_lock_irqsave(&pci_lock, flags); \
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 res = bus->ops->write(bus, devfn, pos, len, value); \
Thomas Gleixner511dd982010-02-17 14:35:19 +000052 raw_spin_unlock_irqrestore(&pci_lock, flags); \
Linus Torvalds1da177e2005-04-16 15:20:36 -070053 return res; \
54}
55
56PCI_OP_READ(byte, u8, 1)
57PCI_OP_READ(word, u16, 2)
58PCI_OP_READ(dword, u32, 4)
59PCI_OP_WRITE(byte, u8, 1)
60PCI_OP_WRITE(word, u16, 2)
61PCI_OP_WRITE(dword, u32, 4)
62
63EXPORT_SYMBOL(pci_bus_read_config_byte);
64EXPORT_SYMBOL(pci_bus_read_config_word);
65EXPORT_SYMBOL(pci_bus_read_config_dword);
66EXPORT_SYMBOL(pci_bus_write_config_byte);
67EXPORT_SYMBOL(pci_bus_write_config_word);
68EXPORT_SYMBOL(pci_bus_write_config_dword);
Brian Kinge04b0ea2005-09-27 01:21:55 -070069
Huang Yinga72b46c2009-04-24 10:45:17 +080070/**
71 * pci_bus_set_ops - Set raw operations of pci bus
72 * @bus: pci bus struct
73 * @ops: new raw operations
74 *
75 * Return previous raw operations
76 */
77struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
78{
79 struct pci_ops *old_ops;
80 unsigned long flags;
81
Thomas Gleixner511dd982010-02-17 14:35:19 +000082 raw_spin_lock_irqsave(&pci_lock, flags);
Huang Yinga72b46c2009-04-24 10:45:17 +080083 old_ops = bus->ops;
84 bus->ops = ops;
Thomas Gleixner511dd982010-02-17 14:35:19 +000085 raw_spin_unlock_irqrestore(&pci_lock, flags);
Huang Yinga72b46c2009-04-24 10:45:17 +080086 return old_ops;
87}
88EXPORT_SYMBOL(pci_bus_set_ops);
Stephen Hemminger287d19c2008-12-18 09:17:16 -080089
90/**
91 * pci_read_vpd - Read one entry from Vital Product Data
92 * @dev: pci device struct
93 * @pos: offset in vpd space
94 * @count: number of bytes to read
95 * @buf: pointer to where to store result
96 *
97 */
98ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
99{
100 if (!dev->vpd || !dev->vpd->ops)
101 return -ENODEV;
102 return dev->vpd->ops->read(dev, pos, count, buf);
103}
104EXPORT_SYMBOL(pci_read_vpd);
105
106/**
107 * pci_write_vpd - Write entry to Vital Product Data
108 * @dev: pci device struct
109 * @pos: offset in vpd space
Randy Dunlapcffb2fa2009-04-10 15:17:50 -0700110 * @count: number of bytes to write
111 * @buf: buffer containing write data
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800112 *
113 */
114ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
115{
116 if (!dev->vpd || !dev->vpd->ops)
117 return -ENODEV;
118 return dev->vpd->ops->write(dev, pos, count, buf);
119}
120EXPORT_SYMBOL(pci_write_vpd);
121
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600122/*
123 * The following routines are to prevent the user from accessing PCI config
124 * space when it's unsafe to do so. Some devices require this during BIST and
125 * we're required to prevent it during D-state transitions.
126 *
127 * We have a bit per device to indicate it's blocked and a global wait queue
128 * for callers to sleep on until devices are unblocked.
129 */
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100130static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700131
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100132static noinline void pci_wait_cfg(struct pci_dev *dev)
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600133{
134 DECLARE_WAITQUEUE(wait, current);
135
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100136 __add_wait_queue(&pci_cfg_wait, &wait);
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600137 do {
138 set_current_state(TASK_UNINTERRUPTIBLE);
Thomas Gleixner511dd982010-02-17 14:35:19 +0000139 raw_spin_unlock_irq(&pci_lock);
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600140 schedule();
Thomas Gleixner511dd982010-02-17 14:35:19 +0000141 raw_spin_lock_irq(&pci_lock);
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100142 } while (dev->block_cfg_access);
143 __remove_wait_queue(&pci_cfg_wait, &wait);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700144}
145
Greg Thelen34e32072011-04-17 08:20:32 -0700146/* Returns 0 on success, negative values indicate error. */
Brian Kinge04b0ea2005-09-27 01:21:55 -0700147#define PCI_USER_READ_CONFIG(size,type) \
148int pci_user_read_config_##size \
149 (struct pci_dev *dev, int pos, type *val) \
150{ \
Brian Kinge04b0ea2005-09-27 01:21:55 -0700151 int ret = 0; \
152 u32 data = -1; \
Greg Thelen34e32072011-04-17 08:20:32 -0700153 if (PCI_##size##_BAD) \
154 return -EINVAL; \
Thomas Gleixner511dd982010-02-17 14:35:19 +0000155 raw_spin_lock_irq(&pci_lock); \
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100156 if (unlikely(dev->block_cfg_access)) \
157 pci_wait_cfg(dev); \
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600158 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
Brian Kinge04b0ea2005-09-27 01:21:55 -0700159 pos, sizeof(type), &data); \
Thomas Gleixner511dd982010-02-17 14:35:19 +0000160 raw_spin_unlock_irq(&pci_lock); \
Brian Kinge04b0ea2005-09-27 01:21:55 -0700161 *val = (type)data; \
Greg Thelen34e32072011-04-17 08:20:32 -0700162 if (ret > 0) \
163 ret = -EINVAL; \
Brian Kinge04b0ea2005-09-27 01:21:55 -0700164 return ret; \
Alex Williamsonc63587d2012-06-11 05:27:19 +0000165} \
166EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700167
Greg Thelen34e32072011-04-17 08:20:32 -0700168/* Returns 0 on success, negative values indicate error. */
Brian Kinge04b0ea2005-09-27 01:21:55 -0700169#define PCI_USER_WRITE_CONFIG(size,type) \
170int pci_user_write_config_##size \
171 (struct pci_dev *dev, int pos, type val) \
172{ \
Brian Kinge04b0ea2005-09-27 01:21:55 -0700173 int ret = -EIO; \
Greg Thelen34e32072011-04-17 08:20:32 -0700174 if (PCI_##size##_BAD) \
175 return -EINVAL; \
Thomas Gleixner511dd982010-02-17 14:35:19 +0000176 raw_spin_lock_irq(&pci_lock); \
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100177 if (unlikely(dev->block_cfg_access)) \
178 pci_wait_cfg(dev); \
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600179 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
Brian Kinge04b0ea2005-09-27 01:21:55 -0700180 pos, sizeof(type), val); \
Thomas Gleixner511dd982010-02-17 14:35:19 +0000181 raw_spin_unlock_irq(&pci_lock); \
Greg Thelen34e32072011-04-17 08:20:32 -0700182 if (ret > 0) \
183 ret = -EINVAL; \
Brian Kinge04b0ea2005-09-27 01:21:55 -0700184 return ret; \
Alex Williamsonc63587d2012-06-11 05:27:19 +0000185} \
186EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700187
188PCI_USER_READ_CONFIG(byte, u8)
189PCI_USER_READ_CONFIG(word, u16)
190PCI_USER_READ_CONFIG(dword, u32)
191PCI_USER_WRITE_CONFIG(byte, u8)
192PCI_USER_WRITE_CONFIG(word, u16)
193PCI_USER_WRITE_CONFIG(dword, u32)
194
Ben Hutchings94e61082008-03-05 16:52:39 +0000195/* VPD access through PCI 2.2+ VPD capability */
196
197#define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
198
199struct pci_vpd_pci22 {
200 struct pci_vpd base;
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800201 struct mutex lock;
202 u16 flag;
Ben Hutchings94e61082008-03-05 16:52:39 +0000203 bool busy;
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800204 u8 cap;
Ben Hutchings94e61082008-03-05 16:52:39 +0000205};
206
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800207/*
208 * Wait for last operation to complete.
209 * This code has to spin since there is no other notification from the PCI
210 * hardware. Since the VPD is often implemented by serial attachment to an
211 * EEPROM, it may take many milliseconds to complete.
Greg Thelen34e32072011-04-17 08:20:32 -0700212 *
213 * Returns 0 on success, negative values indicate error.
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800214 */
Ben Hutchings94e61082008-03-05 16:52:39 +0000215static int pci_vpd_pci22_wait(struct pci_dev *dev)
216{
217 struct pci_vpd_pci22 *vpd =
218 container_of(dev->vpd, struct pci_vpd_pci22, base);
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800219 unsigned long timeout = jiffies + HZ/20 + 2;
220 u16 status;
Ben Hutchings94e61082008-03-05 16:52:39 +0000221 int ret;
222
223 if (!vpd->busy)
224 return 0;
225
Ben Hutchings94e61082008-03-05 16:52:39 +0000226 for (;;) {
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800227 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
Ben Hutchings94e61082008-03-05 16:52:39 +0000228 &status);
Greg Thelen34e32072011-04-17 08:20:32 -0700229 if (ret < 0)
Ben Hutchings94e61082008-03-05 16:52:39 +0000230 return ret;
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800231
232 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
Ben Hutchings94e61082008-03-05 16:52:39 +0000233 vpd->busy = false;
234 return 0;
235 }
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800236
Prarit Bhargava50307182010-05-17 14:25:14 -0400237 if (time_after(jiffies, timeout)) {
238 dev_printk(KERN_DEBUG, &dev->dev,
239 "vpd r/w failed. This is likely a firmware "
240 "bug on this device. Contact the card "
241 "vendor for a firmware update.");
Ben Hutchings94e61082008-03-05 16:52:39 +0000242 return -ETIMEDOUT;
Prarit Bhargava50307182010-05-17 14:25:14 -0400243 }
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800244 if (fatal_signal_pending(current))
245 return -EINTR;
246 if (!cond_resched())
247 udelay(10);
Ben Hutchings94e61082008-03-05 16:52:39 +0000248 }
249}
250
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800251static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
252 void *arg)
Ben Hutchings94e61082008-03-05 16:52:39 +0000253{
254 struct pci_vpd_pci22 *vpd =
255 container_of(dev->vpd, struct pci_vpd_pci22, base);
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800256 int ret;
257 loff_t end = pos + count;
258 u8 *buf = arg;
Ben Hutchings94e61082008-03-05 16:52:39 +0000259
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800260 if (pos < 0 || pos > vpd->base.len || end > vpd->base.len)
Ben Hutchings94e61082008-03-05 16:52:39 +0000261 return -EINVAL;
Ben Hutchings94e61082008-03-05 16:52:39 +0000262
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800263 if (mutex_lock_killable(&vpd->lock))
264 return -EINTR;
265
Ben Hutchings94e61082008-03-05 16:52:39 +0000266 ret = pci_vpd_pci22_wait(dev);
267 if (ret < 0)
268 goto out;
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800269
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800270 while (pos < end) {
271 u32 val;
272 unsigned int i, skip;
273
274 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
275 pos & ~3);
276 if (ret < 0)
277 break;
278 vpd->busy = true;
279 vpd->flag = PCI_VPD_ADDR_F;
280 ret = pci_vpd_pci22_wait(dev);
281 if (ret < 0)
282 break;
283
284 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
285 if (ret < 0)
286 break;
287
288 skip = pos & 3;
289 for (i = 0; i < sizeof(u32); i++) {
290 if (i >= skip) {
291 *buf++ = val;
292 if (++pos == end)
293 break;
294 }
295 val >>= 8;
296 }
297 }
Ben Hutchings94e61082008-03-05 16:52:39 +0000298out:
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800299 mutex_unlock(&vpd->lock);
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800300 return ret ? ret : count;
Ben Hutchings94e61082008-03-05 16:52:39 +0000301}
302
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800303static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
304 const void *arg)
Ben Hutchings94e61082008-03-05 16:52:39 +0000305{
306 struct pci_vpd_pci22 *vpd =
307 container_of(dev->vpd, struct pci_vpd_pci22, base);
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800308 const u8 *buf = arg;
309 loff_t end = pos + count;
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800310 int ret = 0;
Ben Hutchings94e61082008-03-05 16:52:39 +0000311
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800312 if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len)
Ben Hutchings94e61082008-03-05 16:52:39 +0000313 return -EINVAL;
314
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800315 if (mutex_lock_killable(&vpd->lock))
316 return -EINTR;
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800317
Ben Hutchings94e61082008-03-05 16:52:39 +0000318 ret = pci_vpd_pci22_wait(dev);
319 if (ret < 0)
320 goto out;
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800321
322 while (pos < end) {
323 u32 val;
324
325 val = *buf++;
326 val |= *buf++ << 8;
327 val |= *buf++ << 16;
328 val |= *buf++ << 24;
329
330 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
331 if (ret < 0)
332 break;
333 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
334 pos | PCI_VPD_ADDR_F);
335 if (ret < 0)
336 break;
337
338 vpd->busy = true;
339 vpd->flag = 0;
340 ret = pci_vpd_pci22_wait(dev);
Greg Thelend97ecd82011-04-17 08:22:21 -0700341 if (ret < 0)
342 break;
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800343
344 pos += sizeof(u32);
345 }
Ben Hutchings94e61082008-03-05 16:52:39 +0000346out:
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800347 mutex_unlock(&vpd->lock);
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800348 return ret ? ret : count;
Ben Hutchings94e61082008-03-05 16:52:39 +0000349}
350
Ben Hutchings94e61082008-03-05 16:52:39 +0000351static void pci_vpd_pci22_release(struct pci_dev *dev)
352{
353 kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
354}
355
Stephen Hemminger287d19c2008-12-18 09:17:16 -0800356static const struct pci_vpd_ops pci_vpd_pci22_ops = {
Ben Hutchings94e61082008-03-05 16:52:39 +0000357 .read = pci_vpd_pci22_read,
358 .write = pci_vpd_pci22_write,
Ben Hutchings94e61082008-03-05 16:52:39 +0000359 .release = pci_vpd_pci22_release,
360};
361
362int pci_vpd_pci22_init(struct pci_dev *dev)
363{
364 struct pci_vpd_pci22 *vpd;
365 u8 cap;
366
367 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
368 if (!cap)
369 return -ENODEV;
370 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
371 if (!vpd)
372 return -ENOMEM;
373
Benjamin Li99cb233d2008-07-02 10:59:04 -0700374 vpd->base.len = PCI_VPD_PCI22_SIZE;
Ben Hutchings94e61082008-03-05 16:52:39 +0000375 vpd->base.ops = &pci_vpd_pci22_ops;
Stephen Hemminger1120f8b2008-12-18 09:17:16 -0800376 mutex_init(&vpd->lock);
Ben Hutchings94e61082008-03-05 16:52:39 +0000377 vpd->cap = cap;
378 vpd->busy = false;
379 dev->vpd = &vpd->base;
380 return 0;
381}
382
Brian Kinge04b0ea2005-09-27 01:21:55 -0700383/**
Stephen Hemmingerdb567942008-12-18 09:17:16 -0800384 * pci_vpd_truncate - Set available Vital Product Data size
385 * @dev: pci device struct
386 * @size: available memory in bytes
387 *
388 * Adjust size of available VPD area.
389 */
390int pci_vpd_truncate(struct pci_dev *dev, size_t size)
391{
392 if (!dev->vpd)
393 return -EINVAL;
394
395 /* limited by the access method */
396 if (size > dev->vpd->len)
397 return -EINVAL;
398
399 dev->vpd->len = size;
Anton Vorontsovd407e322009-04-01 02:23:41 +0400400 if (dev->vpd->attr)
401 dev->vpd->attr->size = size;
Stephen Hemmingerdb567942008-12-18 09:17:16 -0800402
403 return 0;
404}
405EXPORT_SYMBOL(pci_vpd_truncate);
406
407/**
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100408 * pci_cfg_access_lock - Lock PCI config reads/writes
Brian Kinge04b0ea2005-09-27 01:21:55 -0700409 * @dev: pci device struct
410 *
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100411 * When access is locked, any userspace reads or writes to config
412 * space and concurrent lock requests will sleep until access is
413 * allowed via pci_cfg_access_unlocked again.
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600414 */
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100415void pci_cfg_access_lock(struct pci_dev *dev)
Brian Kinge04b0ea2005-09-27 01:21:55 -0700416{
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100417 might_sleep();
Brian Kinge04b0ea2005-09-27 01:21:55 -0700418
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100419 raw_spin_lock_irq(&pci_lock);
420 if (dev->block_cfg_access)
421 pci_wait_cfg(dev);
422 dev->block_cfg_access = 1;
423 raw_spin_unlock_irq(&pci_lock);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700424}
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100425EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700426
427/**
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100428 * pci_cfg_access_trylock - try to lock PCI config reads/writes
Brian Kinge04b0ea2005-09-27 01:21:55 -0700429 * @dev: pci device struct
430 *
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100431 * Same as pci_cfg_access_lock, but will return 0 if access is
432 * already locked, 1 otherwise. This function can be used from
433 * atomic contexts.
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600434 */
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100435bool pci_cfg_access_trylock(struct pci_dev *dev)
436{
437 unsigned long flags;
438 bool locked = true;
439
440 raw_spin_lock_irqsave(&pci_lock, flags);
441 if (dev->block_cfg_access)
442 locked = false;
443 else
444 dev->block_cfg_access = 1;
445 raw_spin_unlock_irqrestore(&pci_lock, flags);
446
447 return locked;
448}
449EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
450
451/**
452 * pci_cfg_access_unlock - Unlock PCI config reads/writes
453 * @dev: pci device struct
454 *
455 * This function allows PCI config accesses to resume.
456 */
457void pci_cfg_access_unlock(struct pci_dev *dev)
Brian Kinge04b0ea2005-09-27 01:21:55 -0700458{
459 unsigned long flags;
460
Thomas Gleixner511dd982010-02-17 14:35:19 +0000461 raw_spin_lock_irqsave(&pci_lock, flags);
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600462
463 /* This indicates a problem in the caller, but we don't need
464 * to kill them, unlike a double-block above. */
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100465 WARN_ON(!dev->block_cfg_access);
Matthew Wilcox7ea7e982006-10-19 09:41:28 -0600466
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100467 dev->block_cfg_access = 0;
468 wake_up_all(&pci_cfg_wait);
Thomas Gleixner511dd982010-02-17 14:35:19 +0000469 raw_spin_unlock_irqrestore(&pci_lock, flags);
Brian Kinge04b0ea2005-09-27 01:21:55 -0700470}
Jan Kiszkafb51ccb2011-11-04 09:45:59 +0100471EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800472
473static inline int pcie_cap_version(const struct pci_dev *dev)
474{
Myron Stowe1c531d82013-01-25 17:55:45 -0700475 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800476}
477
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800478static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
479{
480 int type = pci_pcie_type(dev);
481
Bjorn Helgaasc8b303d2013-08-28 11:33:53 -0600482 return type == PCI_EXP_TYPE_ENDPOINT ||
Bjorn Helgaasd3694d42013-08-27 09:54:40 -0600483 type == PCI_EXP_TYPE_LEG_END ||
484 type == PCI_EXP_TYPE_ROOT_PORT ||
485 type == PCI_EXP_TYPE_UPSTREAM ||
486 type == PCI_EXP_TYPE_DOWNSTREAM ||
487 type == PCI_EXP_TYPE_PCI_BRIDGE ||
488 type == PCI_EXP_TYPE_PCIE_BRIDGE;
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800489}
490
491static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
492{
493 int type = pci_pcie_type(dev);
494
Bjorn Helgaas6d3a1742013-08-28 12:01:03 -0600495 return (type == PCI_EXP_TYPE_ROOT_PORT ||
496 type == PCI_EXP_TYPE_DOWNSTREAM) &&
497 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800498}
499
500static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
501{
502 int type = pci_pcie_type(dev);
503
Bjorn Helgaasc8b303d2013-08-28 11:33:53 -0600504 return type == PCI_EXP_TYPE_ROOT_PORT ||
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800505 type == PCI_EXP_TYPE_RC_EC;
506}
507
508static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
509{
510 if (!pci_is_pcie(dev))
511 return false;
512
513 switch (pos) {
Alex Williamson969daa32013-02-14 11:35:42 -0700514 case PCI_EXP_FLAGS:
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800515 return true;
516 case PCI_EXP_DEVCAP:
517 case PCI_EXP_DEVCTL:
518 case PCI_EXP_DEVSTA:
Bjorn Helgaasfed24512013-08-28 12:03:42 -0600519 return true;
Jiang Liu8c0d3a02012-07-24 17:20:05 +0800520 case PCI_EXP_LNKCAP:
521 case PCI_EXP_LNKCTL:
522 case PCI_EXP_LNKSTA:
523 return pcie_cap_has_lnkctl(dev);
524 case PCI_EXP_SLTCAP:
525 case PCI_EXP_SLTCTL:
526 case PCI_EXP_SLTSTA:
527 return pcie_cap_has_sltctl(dev);
528 case PCI_EXP_RTCTL:
529 case PCI_EXP_RTCAP:
530 case PCI_EXP_RTSTA:
531 return pcie_cap_has_rtctl(dev);
532 case PCI_EXP_DEVCAP2:
533 case PCI_EXP_DEVCTL2:
534 case PCI_EXP_LNKCAP2:
535 case PCI_EXP_LNKCTL2:
536 case PCI_EXP_LNKSTA2:
537 return pcie_cap_version(dev) > 1;
538 default:
539 return false;
540 }
541}
542
543/*
544 * Note that these accessor functions are only for the "PCI Express
545 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
546 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
547 */
548int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
549{
550 int ret;
551
552 *val = 0;
553 if (pos & 1)
554 return -EINVAL;
555
556 if (pcie_capability_reg_implemented(dev, pos)) {
557 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
558 /*
559 * Reset *val to 0 if pci_read_config_word() fails, it may
560 * have been written as 0xFFFF if hardware error happens
561 * during pci_read_config_word().
562 */
563 if (ret)
564 *val = 0;
565 return ret;
566 }
567
568 /*
569 * For Functions that do not implement the Slot Capabilities,
570 * Slot Status, and Slot Control registers, these spaces must
571 * be hardwired to 0b, with the exception of the Presence Detect
572 * State bit in the Slot Status register of Downstream Ports,
573 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
574 */
575 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
576 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
577 *val = PCI_EXP_SLTSTA_PDS;
578 }
579
580 return 0;
581}
582EXPORT_SYMBOL(pcie_capability_read_word);
583
584int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
585{
586 int ret;
587
588 *val = 0;
589 if (pos & 3)
590 return -EINVAL;
591
592 if (pcie_capability_reg_implemented(dev, pos)) {
593 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
594 /*
595 * Reset *val to 0 if pci_read_config_dword() fails, it may
596 * have been written as 0xFFFFFFFF if hardware error happens
597 * during pci_read_config_dword().
598 */
599 if (ret)
600 *val = 0;
601 return ret;
602 }
603
604 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
605 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
606 *val = PCI_EXP_SLTSTA_PDS;
607 }
608
609 return 0;
610}
611EXPORT_SYMBOL(pcie_capability_read_dword);
612
613int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
614{
615 if (pos & 1)
616 return -EINVAL;
617
618 if (!pcie_capability_reg_implemented(dev, pos))
619 return 0;
620
621 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
622}
623EXPORT_SYMBOL(pcie_capability_write_word);
624
625int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
626{
627 if (pos & 3)
628 return -EINVAL;
629
630 if (!pcie_capability_reg_implemented(dev, pos))
631 return 0;
632
633 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
634}
635EXPORT_SYMBOL(pcie_capability_write_dword);
636
637int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
638 u16 clear, u16 set)
639{
640 int ret;
641 u16 val;
642
643 ret = pcie_capability_read_word(dev, pos, &val);
644 if (!ret) {
645 val &= ~clear;
646 val |= set;
647 ret = pcie_capability_write_word(dev, pos, val);
648 }
649
650 return ret;
651}
652EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
653
654int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
655 u32 clear, u32 set)
656{
657 int ret;
658 u32 val;
659
660 ret = pcie_capability_read_dword(dev, pos, &val);
661 if (!ret) {
662 val &= ~clear;
663 val |= set;
664 ret = pcie_capability_write_dword(dev, pos, val);
665 }
666
667 return ret;
668}
669EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);