Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2007-2008 Intel Corporation |
| 3 | * Jesse Barnes <jesse.barnes@intel.com> |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | #ifndef __DRM_EDID_H__ |
| 24 | #define __DRM_EDID_H__ |
| 25 | |
| 26 | #include <linux/types.h> |
Ville Syrjälä | 0014793 | 2017-01-11 14:57:21 +0200 | [diff] [blame] | 27 | #include <linux/hdmi.h> |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 28 | |
Daniel Vetter | cdc3d09 | 2016-08-31 18:09:06 +0200 | [diff] [blame] | 29 | struct drm_device; |
| 30 | struct i2c_adapter; |
| 31 | |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 32 | #define EDID_LENGTH 128 |
| 33 | #define DDC_ADDR 0x50 |
Dave Airlie | b49b55b | 2014-10-20 16:13:19 +1000 | [diff] [blame] | 34 | #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 35 | |
Adam Jackson | 4d76a22 | 2010-08-03 14:38:17 -0400 | [diff] [blame] | 36 | #define CEA_EXT 0x02 |
| 37 | #define VTB_EXT 0x10 |
| 38 | #define DI_EXT 0x40 |
| 39 | #define LS_EXT 0x50 |
| 40 | #define MI_EXT 0x60 |
Dave Airlie | b49b55b | 2014-10-20 16:13:19 +1000 | [diff] [blame] | 41 | #define DISPLAYID_EXT 0x70 |
Adam Jackson | 4d76a22 | 2010-08-03 14:38:17 -0400 | [diff] [blame] | 42 | |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 43 | struct est_timings { |
| 44 | u8 t1; |
| 45 | u8 t2; |
| 46 | u8 mfg_rsvd; |
| 47 | } __attribute__((packed)); |
| 48 | |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 49 | /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ |
Michel Dänzer | e14cbee | 2009-06-23 12:36:32 +0200 | [diff] [blame] | 50 | #define EDID_TIMING_ASPECT_SHIFT 6 |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 51 | #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) |
| 52 | |
| 53 | /* need to add 60 */ |
Michel Dänzer | e14cbee | 2009-06-23 12:36:32 +0200 | [diff] [blame] | 54 | #define EDID_TIMING_VFREQ_SHIFT 0 |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 55 | #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) |
| 56 | |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 57 | struct std_timing { |
| 58 | u8 hsize; /* need to multiply by 8 then add 248 */ |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 59 | u8 vfreq_aspect; |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 60 | } __attribute__((packed)); |
| 61 | |
Michel Dänzer | e14cbee | 2009-06-23 12:36:32 +0200 | [diff] [blame] | 62 | #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) |
| 63 | #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 64 | #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) |
Michel Dänzer | e14cbee | 2009-06-23 12:36:32 +0200 | [diff] [blame] | 65 | #define DRM_EDID_PT_STEREO (1 << 5) |
| 66 | #define DRM_EDID_PT_INTERLACED (1 << 7) |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 67 | |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 68 | /* If detailed data is pixel timing */ |
| 69 | struct detailed_pixel_timing { |
| 70 | u8 hactive_lo; |
| 71 | u8 hblank_lo; |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 72 | u8 hactive_hblank_hi; |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 73 | u8 vactive_lo; |
| 74 | u8 vblank_lo; |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 75 | u8 vactive_vblank_hi; |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 76 | u8 hsync_offset_lo; |
| 77 | u8 hsync_pulse_width_lo; |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 78 | u8 vsync_offset_pulse_width_lo; |
| 79 | u8 hsync_vsync_offset_pulse_width_hi; |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 80 | u8 width_mm_lo; |
| 81 | u8 height_mm_lo; |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 82 | u8 width_height_mm_hi; |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 83 | u8 hborder; |
| 84 | u8 vborder; |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 85 | u8 misc; |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 86 | } __attribute__((packed)); |
| 87 | |
| 88 | /* If it's not pixel timing, it'll be one of the below */ |
| 89 | struct detailed_data_string { |
| 90 | u8 str[13]; |
| 91 | } __attribute__((packed)); |
| 92 | |
| 93 | struct detailed_data_monitor_range { |
| 94 | u8 min_vfreq; |
| 95 | u8 max_vfreq; |
| 96 | u8 min_hfreq_khz; |
| 97 | u8 max_hfreq_khz; |
| 98 | u8 pixel_clock_mhz; /* need to multiply by 10 */ |
Adam Jackson | eeefa4b | 2012-04-13 16:33:37 -0400 | [diff] [blame] | 99 | u8 flags; |
| 100 | union { |
| 101 | struct { |
| 102 | u8 reserved; |
| 103 | u8 hfreq_start_khz; /* need to multiply by 2 */ |
| 104 | u8 c; /* need to divide by 2 */ |
| 105 | __le16 m; |
| 106 | u8 k; |
| 107 | u8 j; /* need to divide by 2 */ |
Takashi Iwai | 8353e6c | 2012-04-23 17:40:49 +0100 | [diff] [blame] | 108 | } __attribute__((packed)) gtf2; |
Adam Jackson | eeefa4b | 2012-04-13 16:33:37 -0400 | [diff] [blame] | 109 | struct { |
| 110 | u8 version; |
| 111 | u8 data1; /* high 6 bits: extra clock resolution */ |
| 112 | u8 data2; /* plus low 2 of above: max hactive */ |
| 113 | u8 supported_aspects; |
| 114 | u8 flags; /* preferred aspect and blanking support */ |
| 115 | u8 supported_scalings; |
| 116 | u8 preferred_refresh; |
Takashi Iwai | 8353e6c | 2012-04-23 17:40:49 +0100 | [diff] [blame] | 117 | } __attribute__((packed)) cvt; |
Adam Jackson | eeefa4b | 2012-04-13 16:33:37 -0400 | [diff] [blame] | 118 | } formula; |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 119 | } __attribute__((packed)); |
| 120 | |
| 121 | struct detailed_data_wpindex { |
Michel Dänzer | e14cbee | 2009-06-23 12:36:32 +0200 | [diff] [blame] | 122 | u8 white_yx_lo; /* Lower 2 bits each */ |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 123 | u8 white_x_hi; |
| 124 | u8 white_y_hi; |
| 125 | u8 gamma; /* need to divide by 100 then add 1 */ |
| 126 | } __attribute__((packed)); |
| 127 | |
| 128 | struct detailed_data_color_point { |
| 129 | u8 windex1; |
| 130 | u8 wpindex1[3]; |
| 131 | u8 windex2; |
| 132 | u8 wpindex2[3]; |
| 133 | } __attribute__((packed)); |
| 134 | |
Adam Jackson | 9340d8c | 2009-12-03 17:44:40 -0500 | [diff] [blame] | 135 | struct cvt_timing { |
| 136 | u8 code[3]; |
| 137 | } __attribute__((packed)); |
| 138 | |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 139 | struct detailed_non_pixel { |
| 140 | u8 pad1; |
| 141 | u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name |
| 142 | fb=color point data, fa=standard timing data, |
| 143 | f9=undefined, f8=mfg. reserved */ |
| 144 | u8 pad2; |
| 145 | union { |
| 146 | struct detailed_data_string str; |
| 147 | struct detailed_data_monitor_range range; |
| 148 | struct detailed_data_wpindex color; |
Dan Carpenter | 96525a2 | 2010-05-14 13:06:19 +0200 | [diff] [blame] | 149 | struct std_timing timings[6]; |
Adam Jackson | 9340d8c | 2009-12-03 17:44:40 -0500 | [diff] [blame] | 150 | struct cvt_timing cvt[4]; |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 151 | } data; |
| 152 | } __attribute__((packed)); |
| 153 | |
Adam Jackson | 2dbdc52 | 2009-12-03 17:44:39 -0500 | [diff] [blame] | 154 | #define EDID_DETAIL_EST_TIMINGS 0xf7 |
| 155 | #define EDID_DETAIL_CVT_3BYTE 0xf8 |
| 156 | #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 157 | #define EDID_DETAIL_STD_MODES 0xfa |
| 158 | #define EDID_DETAIL_MONITOR_CPDATA 0xfb |
| 159 | #define EDID_DETAIL_MONITOR_NAME 0xfc |
| 160 | #define EDID_DETAIL_MONITOR_RANGE 0xfd |
| 161 | #define EDID_DETAIL_MONITOR_STRING 0xfe |
| 162 | #define EDID_DETAIL_MONITOR_SERIAL 0xff |
| 163 | |
| 164 | struct detailed_timing { |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 165 | __le16 pixel_clock; /* need to multiply by 10 KHz */ |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 166 | union { |
| 167 | struct detailed_pixel_timing pixel_data; |
| 168 | struct detailed_non_pixel other_data; |
| 169 | } data; |
| 170 | } __attribute__((packed)); |
| 171 | |
Michel Dänzer | e14cbee | 2009-06-23 12:36:32 +0200 | [diff] [blame] | 172 | #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) |
| 173 | #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) |
| 174 | #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 175 | #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) |
Michel Dänzer | e14cbee | 2009-06-23 12:36:32 +0200 | [diff] [blame] | 176 | #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) |
| 177 | #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) |
Jesse Barnes | 3b11228 | 2011-04-15 12:49:23 -0700 | [diff] [blame] | 178 | #define DRM_EDID_INPUT_DIGITAL (1 << 7) |
| 179 | #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) |
| 180 | #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) |
| 181 | #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) |
| 182 | #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) |
| 183 | #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) |
| 184 | #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) |
| 185 | #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) |
| 186 | #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) |
| 187 | #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) |
| 188 | #define DRM_EDID_DIGITAL_TYPE_UNDEF (0) |
| 189 | #define DRM_EDID_DIGITAL_TYPE_DVI (1) |
| 190 | #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2) |
| 191 | #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3) |
| 192 | #define DRM_EDID_DIGITAL_TYPE_MDDI (4) |
| 193 | #define DRM_EDID_DIGITAL_TYPE_DP (5) |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 194 | |
Michel Dänzer | e14cbee | 2009-06-23 12:36:32 +0200 | [diff] [blame] | 195 | #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) |
| 196 | #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) |
| 197 | #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) |
Jesse Barnes | da05a5a7 | 2011-04-15 13:48:57 -0700 | [diff] [blame] | 198 | /* If analog */ |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 199 | #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ |
Jesse Barnes | da05a5a7 | 2011-04-15 13:48:57 -0700 | [diff] [blame] | 200 | /* If digital */ |
| 201 | #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) |
| 202 | #define DRM_EDID_FEATURE_RGB (0 << 3) |
| 203 | #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) |
| 204 | #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) |
| 205 | #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ |
| 206 | |
Michel Dänzer | e14cbee | 2009-06-23 12:36:32 +0200 | [diff] [blame] | 207 | #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) |
| 208 | #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) |
| 209 | #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 210 | |
Mario Kleiner | d0c9469 | 2014-03-27 19:59:39 +0100 | [diff] [blame] | 211 | #define DRM_EDID_HDMI_DC_48 (1 << 6) |
| 212 | #define DRM_EDID_HDMI_DC_36 (1 << 5) |
| 213 | #define DRM_EDID_HDMI_DC_30 (1 << 4) |
| 214 | #define DRM_EDID_HDMI_DC_Y444 (1 << 3) |
| 215 | |
Jani Nikula | babc949 | 2014-10-28 16:20:47 +0200 | [diff] [blame] | 216 | /* ELD Header Block */ |
| 217 | #define DRM_ELD_HEADER_BLOCK_SIZE 4 |
| 218 | |
| 219 | #define DRM_ELD_VER 0 |
| 220 | # define DRM_ELD_VER_SHIFT 3 |
| 221 | # define DRM_ELD_VER_MASK (0x1f << 3) |
Jani Nikula | 1b54bdb | 2015-04-13 10:57:14 +0300 | [diff] [blame] | 222 | # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */ |
| 223 | # define DRM_ELD_VER_CANNED (0x1f << 3) |
Jani Nikula | babc949 | 2014-10-28 16:20:47 +0200 | [diff] [blame] | 224 | |
| 225 | #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */ |
| 226 | |
| 227 | /* ELD Baseline Block for ELD_Ver == 2 */ |
| 228 | #define DRM_ELD_CEA_EDID_VER_MNL 4 |
| 229 | # define DRM_ELD_CEA_EDID_VER_SHIFT 5 |
| 230 | # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5) |
| 231 | # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5) |
| 232 | # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5) |
| 233 | # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5) |
| 234 | # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5) |
| 235 | # define DRM_ELD_MNL_SHIFT 0 |
| 236 | # define DRM_ELD_MNL_MASK (0x1f << 0) |
| 237 | |
| 238 | #define DRM_ELD_SAD_COUNT_CONN_TYPE 5 |
| 239 | # define DRM_ELD_SAD_COUNT_SHIFT 4 |
| 240 | # define DRM_ELD_SAD_COUNT_MASK (0xf << 4) |
| 241 | # define DRM_ELD_CONN_TYPE_SHIFT 2 |
| 242 | # define DRM_ELD_CONN_TYPE_MASK (3 << 2) |
| 243 | # define DRM_ELD_CONN_TYPE_HDMI (0 << 2) |
| 244 | # define DRM_ELD_CONN_TYPE_DP (1 << 2) |
| 245 | # define DRM_ELD_SUPPORTS_AI (1 << 1) |
| 246 | # define DRM_ELD_SUPPORTS_HDCP (1 << 0) |
| 247 | |
| 248 | #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */ |
| 249 | # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */ |
| 250 | |
| 251 | #define DRM_ELD_SPEAKER 7 |
| 252 | # define DRM_ELD_SPEAKER_RLRC (1 << 6) |
| 253 | # define DRM_ELD_SPEAKER_FLRC (1 << 5) |
| 254 | # define DRM_ELD_SPEAKER_RC (1 << 4) |
| 255 | # define DRM_ELD_SPEAKER_RLR (1 << 3) |
| 256 | # define DRM_ELD_SPEAKER_FC (1 << 2) |
| 257 | # define DRM_ELD_SPEAKER_LFE (1 << 1) |
| 258 | # define DRM_ELD_SPEAKER_FLR (1 << 0) |
| 259 | |
| 260 | #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */ |
| 261 | # define DRM_ELD_PORT_ID_LEN 8 |
| 262 | |
| 263 | #define DRM_ELD_MANUFACTURER_NAME0 16 |
| 264 | #define DRM_ELD_MANUFACTURER_NAME1 17 |
| 265 | |
| 266 | #define DRM_ELD_PRODUCT_CODE0 18 |
| 267 | #define DRM_ELD_PRODUCT_CODE1 19 |
| 268 | |
| 269 | #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */ |
| 270 | |
| 271 | #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) |
| 272 | |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 273 | struct edid { |
| 274 | u8 header[8]; |
| 275 | /* Vendor & product info */ |
| 276 | u8 mfg_id[2]; |
| 277 | u8 prod_code[2]; |
| 278 | u32 serial; /* FIXME: byte order */ |
| 279 | u8 mfg_week; |
| 280 | u8 mfg_year; |
| 281 | /* EDID version */ |
| 282 | u8 version; |
| 283 | u8 revision; |
| 284 | /* Display info: */ |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 285 | u8 input; |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 286 | u8 width_cm; |
| 287 | u8 height_cm; |
| 288 | u8 gamma; |
Michel Dänzer | 0454bea | 2009-06-15 16:56:07 +0200 | [diff] [blame] | 289 | u8 features; |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 290 | /* Color characteristics */ |
| 291 | u8 red_green_lo; |
| 292 | u8 black_white_lo; |
| 293 | u8 red_x; |
| 294 | u8 red_y; |
| 295 | u8 green_x; |
| 296 | u8 green_y; |
| 297 | u8 blue_x; |
| 298 | u8 blue_y; |
| 299 | u8 white_x; |
| 300 | u8 white_y; |
| 301 | /* Est. timings and mfg rsvd timings*/ |
| 302 | struct est_timings established_timings; |
| 303 | /* Standard timings 1-8*/ |
| 304 | struct std_timing standard_timings[8]; |
| 305 | /* Detailing timings 1-4 */ |
| 306 | struct detailed_timing detailed_timings[4]; |
| 307 | /* Number of 128 byte ext. blocks */ |
| 308 | u8 extensions; |
| 309 | /* Checksum */ |
| 310 | u8 checksum; |
| 311 | } __attribute__((packed)); |
| 312 | |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 313 | #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) |
| 314 | |
Rafał Miłecki | fe21416 | 2013-04-19 19:01:25 +0200 | [diff] [blame] | 315 | /* Short Audio Descriptor */ |
| 316 | struct cea_sad { |
| 317 | u8 format; |
| 318 | u8 channels; /* max number of channels - 1 */ |
| 319 | u8 freq; |
| 320 | u8 byte2; /* meaning depends on format */ |
| 321 | }; |
| 322 | |
Wu Fengguang | 76adaa34 | 2011-09-05 14:23:20 +0800 | [diff] [blame] | 323 | struct drm_encoder; |
| 324 | struct drm_connector; |
| 325 | struct drm_display_mode; |
Thierry Reding | 10a8512 | 2012-11-21 15:31:35 +0100 | [diff] [blame] | 326 | |
Wu Fengguang | 76adaa34 | 2011-09-05 14:23:20 +0800 | [diff] [blame] | 327 | void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid); |
Rafał Miłecki | fe21416 | 2013-04-19 19:01:25 +0200 | [diff] [blame] | 328 | int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); |
Alex Deucher | d105f47 | 2013-07-25 15:55:32 -0400 | [diff] [blame] | 329 | int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); |
Wu Fengguang | 76adaa34 | 2011-09-05 14:23:20 +0800 | [diff] [blame] | 330 | int drm_av_sync_delay(struct drm_connector *connector, |
Ville Syrjälä | 3a818d3 | 2015-09-07 18:22:58 +0300 | [diff] [blame] | 331 | const struct drm_display_mode *mode); |
Ezequiel Garcia | ba34d58 | 2016-04-19 14:40:37 -0300 | [diff] [blame] | 332 | |
| 333 | #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE |
Carsten Emde | da0df92 | 2012-03-18 22:37:33 +0100 | [diff] [blame] | 334 | int drm_load_edid_firmware(struct drm_connector *connector); |
Ezequiel Garcia | ba34d58 | 2016-04-19 14:40:37 -0300 | [diff] [blame] | 335 | #else |
| 336 | static inline int drm_load_edid_firmware(struct drm_connector *connector) |
| 337 | { |
| 338 | return 0; |
| 339 | } |
| 340 | #endif |
Wu Fengguang | 76adaa34 | 2011-09-05 14:23:20 +0800 | [diff] [blame] | 341 | |
Thierry Reding | 10a8512 | 2012-11-21 15:31:35 +0100 | [diff] [blame] | 342 | int |
| 343 | drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, |
| 344 | const struct drm_display_mode *mode); |
Lespiau, Damien | 83dd000 | 2013-08-19 16:59:03 +0100 | [diff] [blame] | 345 | int |
| 346 | drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, |
| 347 | const struct drm_display_mode *mode); |
Ville Syrjälä | a2ce26f | 2017-01-11 14:57:23 +0200 | [diff] [blame^] | 348 | void |
| 349 | drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, |
| 350 | enum hdmi_quantization_range rgb_quant_range, |
| 351 | bool rgb_quant_range_selectable); |
Thierry Reding | 10a8512 | 2012-11-21 15:31:35 +0100 | [diff] [blame] | 352 | |
Jani Nikula | babc949 | 2014-10-28 16:20:47 +0200 | [diff] [blame] | 353 | /** |
| 354 | * drm_eld_mnl - Get ELD monitor name length in bytes. |
| 355 | * @eld: pointer to an eld memory structure with mnl set |
| 356 | */ |
| 357 | static inline int drm_eld_mnl(const uint8_t *eld) |
| 358 | { |
| 359 | return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; |
| 360 | } |
| 361 | |
| 362 | /** |
Russell King | 1c73d3b | 2015-03-28 18:13:52 +0000 | [diff] [blame] | 363 | * drm_eld_sad - Get ELD SAD structures. |
| 364 | * @eld: pointer to an eld memory structure with sad_count set |
| 365 | */ |
| 366 | static inline const uint8_t *drm_eld_sad(const uint8_t *eld) |
| 367 | { |
| 368 | unsigned int ver, mnl; |
| 369 | |
| 370 | ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT; |
| 371 | if (ver != 2 && ver != 31) |
| 372 | return NULL; |
| 373 | |
| 374 | mnl = drm_eld_mnl(eld); |
| 375 | if (mnl > 16) |
| 376 | return NULL; |
| 377 | |
| 378 | return eld + DRM_ELD_CEA_SAD(mnl, 0); |
| 379 | } |
| 380 | |
| 381 | /** |
Jani Nikula | babc949 | 2014-10-28 16:20:47 +0200 | [diff] [blame] | 382 | * drm_eld_sad_count - Get ELD SAD count. |
| 383 | * @eld: pointer to an eld memory structure with sad_count set |
| 384 | */ |
| 385 | static inline int drm_eld_sad_count(const uint8_t *eld) |
| 386 | { |
| 387 | return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >> |
| 388 | DRM_ELD_SAD_COUNT_SHIFT; |
| 389 | } |
| 390 | |
| 391 | /** |
| 392 | * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes |
| 393 | * @eld: pointer to an eld memory structure with mnl and sad_count set |
| 394 | * |
| 395 | * This is a helper for determining the payload size of the baseline block, in |
| 396 | * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block. |
| 397 | */ |
| 398 | static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld) |
| 399 | { |
| 400 | return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE + |
| 401 | drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3; |
| 402 | } |
| 403 | |
| 404 | /** |
| 405 | * drm_eld_size - Get ELD size in bytes |
| 406 | * @eld: pointer to a complete eld memory structure |
| 407 | * |
| 408 | * The returned value does not include the vendor block. It's vendor specific, |
| 409 | * and comprises of the remaining bytes in the ELD memory buffer after |
| 410 | * drm_eld_size() bytes of header and baseline block. |
| 411 | * |
| 412 | * The returned value is guaranteed to be a multiple of 4. |
| 413 | */ |
| 414 | static inline int drm_eld_size(const uint8_t *eld) |
| 415 | { |
| 416 | return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4; |
| 417 | } |
| 418 | |
Subhransu S. Prusty | 1aa8ec2 | 2016-02-12 07:46:08 +0530 | [diff] [blame] | 419 | /** |
| 420 | * drm_eld_get_conn_type - Get device type hdmi/dp connected |
| 421 | * @eld: pointer to an ELD memory structure |
| 422 | * |
| 423 | * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to |
| 424 | * identify the display type connected. |
| 425 | */ |
| 426 | static inline u8 drm_eld_get_conn_type(const uint8_t *eld) |
| 427 | { |
| 428 | return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK; |
| 429 | } |
| 430 | |
Daniel Vetter | cdc3d09 | 2016-08-31 18:09:06 +0200 | [diff] [blame] | 431 | bool drm_probe_ddc(struct i2c_adapter *adapter); |
Lars-Peter Clausen | 18df89f | 2012-04-27 11:11:58 +0200 | [diff] [blame] | 432 | struct edid *drm_do_get_edid(struct drm_connector *connector, |
| 433 | int (*get_edid_block)(void *data, u8 *buf, unsigned int block, |
| 434 | size_t len), |
| 435 | void *data); |
Daniel Vetter | cdc3d09 | 2016-08-31 18:09:06 +0200 | [diff] [blame] | 436 | struct edid *drm_get_edid(struct drm_connector *connector, |
| 437 | struct i2c_adapter *adapter); |
| 438 | struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, |
| 439 | struct i2c_adapter *adapter); |
| 440 | struct edid *drm_edid_duplicate(const struct edid *edid); |
| 441 | int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); |
| 442 | |
| 443 | u8 drm_match_cea_mode(const struct drm_display_mode *to_match); |
| 444 | enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code); |
| 445 | bool drm_detect_hdmi_monitor(struct edid *edid); |
| 446 | bool drm_detect_monitor_audio(struct edid *edid); |
| 447 | bool drm_rgb_quant_range_selectable(struct edid *edid); |
Ville Syrjälä | c8127cf0 | 2017-01-11 16:18:35 +0200 | [diff] [blame] | 448 | enum hdmi_quantization_range |
| 449 | drm_default_rgb_quant_range(const struct drm_display_mode *mode); |
Daniel Vetter | cdc3d09 | 2016-08-31 18:09:06 +0200 | [diff] [blame] | 450 | int drm_add_modes_noedid(struct drm_connector *connector, |
| 451 | int hdisplay, int vdisplay); |
| 452 | void drm_set_preferred_mode(struct drm_connector *connector, |
| 453 | int hpref, int vpref); |
| 454 | |
| 455 | int drm_edid_header_is_valid(const u8 *raw_edid); |
| 456 | bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, |
| 457 | bool *edid_corrupt); |
| 458 | bool drm_edid_is_valid(struct edid *edid); |
| 459 | void drm_edid_get_monitor_name(struct edid *edid, char *name, |
| 460 | int buflen); |
| 461 | struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, |
| 462 | int hsize, int vsize, int fresh, |
| 463 | bool rb); |
Lars-Peter Clausen | 18df89f | 2012-04-27 11:11:58 +0200 | [diff] [blame] | 464 | |
Dave Airlie | f453ba0 | 2008-11-07 14:05:41 -0800 | [diff] [blame] | 465 | #endif /* __DRM_EDID_H__ */ |