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Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001/*
Jamie Ilesf75ba502011-11-08 10:12:32 +00002 * Cadence MACB/GEM Ethernet Controller driver
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01003 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
Jamie Ilesc220f8c2011-03-08 20:27:08 +000011#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
Haavard Skinnemoen89e57852006-11-09 14:51:17 +010012#include <linux/clk.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
Nicolas Ferre909a8582012-11-19 06:00:21 +000017#include <linux/circ_buf.h>
Haavard Skinnemoen89e57852006-11-09 14:51:17 +010018#include <linux/slab.h>
19#include <linux/init.h>
Soren Brinkmann60fe7162013-12-10 16:07:21 -080020#include <linux/io.h>
Joachim Eastwood2dbfdbb2012-11-11 13:56:27 +000021#include <linux/gpio.h>
Alexey Dobriyana6b7a402011-06-06 10:43:46 +000022#include <linux/interrupt.h>
Haavard Skinnemoen89e57852006-11-09 14:51:17 +010023#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
Haavard Skinnemoen89e57852006-11-09 14:51:17 +010025#include <linux/dma-mapping.h>
Jamie Iles84e0cdb2011-03-08 20:17:06 +000026#include <linux/platform_data/macb.h>
Haavard Skinnemoen89e57852006-11-09 14:51:17 +010027#include <linux/platform_device.h>
frederic RODO6c36a702007-07-12 19:07:24 +020028#include <linux/phy.h>
Olof Johanssonb17471f2011-12-20 13:13:07 -080029#include <linux/of.h>
Jean-Christophe PLAGNIOL-VILLARDfb97a842011-11-18 15:29:25 +010030#include <linux/of_device.h>
Boris BREZILLON148cbb52013-08-22 17:57:28 +020031#include <linux/of_mdio.h>
Jean-Christophe PLAGNIOL-VILLARDfb97a842011-11-18 15:29:25 +010032#include <linux/of_net.h>
Haavard Skinnemoen89e57852006-11-09 14:51:17 +010033
Haavard Skinnemoen89e57852006-11-09 14:51:17 +010034#include "macb.h"
35
Nicolas Ferre1b447912013-06-04 21:57:11 +000036#define MACB_RX_BUFFER_SIZE 128
Nicolas Ferre1b447912013-06-04 21:57:11 +000037#define RX_BUFFER_MULTIPLE 64 /* bytes */
Havard Skinnemoen55054a12012-10-31 06:04:55 +000038#define RX_RING_SIZE 512 /* must be power of 2 */
39#define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +010040
Havard Skinnemoen55054a12012-10-31 06:04:55 +000041#define TX_RING_SIZE 128 /* must be power of 2 */
42#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +010043
Nicolas Ferre909a8582012-11-19 06:00:21 +000044/* level of occupied TX descriptors under which we wake up TX process */
45#define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +010046
47#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
48 | MACB_BIT(ISR_ROVR))
Nicolas Ferree86cd532012-10-31 06:04:57 +000049#define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
50 | MACB_BIT(ISR_RLE) \
51 | MACB_BIT(TXERR))
52#define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
53
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +020054#define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
55#define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
56
Harini Katakama5898ea2015-05-06 22:27:18 +053057#define GEM_MTU_MIN_SIZE 68
58
Nicolas Ferree86cd532012-10-31 06:04:57 +000059/*
60 * Graceful stop timeouts in us. We should allow up to
61 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
62 */
63#define MACB_HALT_TIMEOUT 1230
Haavard Skinnemoen89e57852006-11-09 14:51:17 +010064
Havard Skinnemoen55054a12012-10-31 06:04:55 +000065/* Ring buffer accessors */
66static unsigned int macb_tx_ring_wrap(unsigned int index)
67{
68 return index & (TX_RING_SIZE - 1);
69}
70
Cyrille Pitchen02c958d2014-12-12 13:26:44 +010071static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
72 unsigned int index)
Havard Skinnemoen55054a12012-10-31 06:04:55 +000073{
Cyrille Pitchen02c958d2014-12-12 13:26:44 +010074 return &queue->tx_ring[macb_tx_ring_wrap(index)];
Havard Skinnemoen55054a12012-10-31 06:04:55 +000075}
76
Cyrille Pitchen02c958d2014-12-12 13:26:44 +010077static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
78 unsigned int index)
Havard Skinnemoen55054a12012-10-31 06:04:55 +000079{
Cyrille Pitchen02c958d2014-12-12 13:26:44 +010080 return &queue->tx_skb[macb_tx_ring_wrap(index)];
Havard Skinnemoen55054a12012-10-31 06:04:55 +000081}
82
Cyrille Pitchen02c958d2014-12-12 13:26:44 +010083static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
Havard Skinnemoen55054a12012-10-31 06:04:55 +000084{
85 dma_addr_t offset;
86
87 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
88
Cyrille Pitchen02c958d2014-12-12 13:26:44 +010089 return queue->tx_ring_dma + offset;
Havard Skinnemoen55054a12012-10-31 06:04:55 +000090}
91
92static unsigned int macb_rx_ring_wrap(unsigned int index)
93{
94 return index & (RX_RING_SIZE - 1);
95}
96
97static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
98{
99 return &bp->rx_ring[macb_rx_ring_wrap(index)];
100}
101
102static void *macb_rx_buffer(struct macb *bp, unsigned int index)
103{
Nicolas Ferre1b447912013-06-04 21:57:11 +0000104 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000105}
106
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +0300107/* I/O accessors */
108static u32 hw_readl_native(struct macb *bp, int offset)
109{
110 return __raw_readl(bp->regs + offset);
111}
112
113static void hw_writel_native(struct macb *bp, int offset, u32 value)
114{
115 __raw_writel(value, bp->regs + offset);
116}
117
118static u32 hw_readl(struct macb *bp, int offset)
119{
120 return readl_relaxed(bp->regs + offset);
121}
122
123static void hw_writel(struct macb *bp, int offset, u32 value)
124{
125 writel_relaxed(value, bp->regs + offset);
126}
127
128/*
129 * Find the CPU endianness by using the loopback bit of NCR register. When the
130 * CPU is in big endian we need to program swaped mode for management
131 * descriptor access.
132 */
133static bool hw_is_native_io(void __iomem *addr)
134{
135 u32 value = MACB_BIT(LLB);
136
137 __raw_writel(value, addr + MACB_NCR);
138 value = __raw_readl(addr + MACB_NCR);
139
140 /* Write 0 back to disable everything */
141 __raw_writel(0, addr + MACB_NCR);
142
143 return value == MACB_BIT(LLB);
144}
145
146static bool hw_is_gem(void __iomem *addr, bool native_io)
147{
148 u32 id;
149
150 if (native_io)
151 id = __raw_readl(addr + MACB_MID);
152 else
153 id = readl_relaxed(addr + MACB_MID);
154
155 return MACB_BFEXT(IDNUM, id) >= 0x2;
156}
157
Cyrille Pitchen421d9df2015-03-07 07:23:32 +0100158static void macb_set_hwaddr(struct macb *bp)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100159{
160 u32 bottom;
161 u16 top;
162
163 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
Jamie Ilesf75ba502011-11-08 10:12:32 +0000164 macb_or_gem_writel(bp, SA1B, bottom);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100165 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
Jamie Ilesf75ba502011-11-08 10:12:32 +0000166 macb_or_gem_writel(bp, SA1T, top);
Joachim Eastwood3629a6c2012-11-11 13:56:28 +0000167
168 /* Clear unused address register sets */
169 macb_or_gem_writel(bp, SA2B, 0);
170 macb_or_gem_writel(bp, SA2T, 0);
171 macb_or_gem_writel(bp, SA3B, 0);
172 macb_or_gem_writel(bp, SA3T, 0);
173 macb_or_gem_writel(bp, SA4B, 0);
174 macb_or_gem_writel(bp, SA4T, 0);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100175}
176
Cyrille Pitchen421d9df2015-03-07 07:23:32 +0100177static void macb_get_hwaddr(struct macb *bp)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100178{
Joachim Eastwoodd25e78a2012-11-07 08:14:51 +0000179 struct macb_platform_data *pdata;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100180 u32 bottom;
181 u16 top;
182 u8 addr[6];
Joachim Eastwood17b8bb32012-11-07 08:14:50 +0000183 int i;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100184
Jingoo Hanc607a0d2013-08-30 14:12:21 +0900185 pdata = dev_get_platdata(&bp->pdev->dev);
Joachim Eastwoodd25e78a2012-11-07 08:14:51 +0000186
Joachim Eastwood17b8bb32012-11-07 08:14:50 +0000187 /* Check all 4 address register for vaild address */
188 for (i = 0; i < 4; i++) {
189 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
190 top = macb_or_gem_readl(bp, SA1T + i * 8);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100191
Joachim Eastwoodd25e78a2012-11-07 08:14:51 +0000192 if (pdata && pdata->rev_eth_addr) {
193 addr[5] = bottom & 0xff;
194 addr[4] = (bottom >> 8) & 0xff;
195 addr[3] = (bottom >> 16) & 0xff;
196 addr[2] = (bottom >> 24) & 0xff;
197 addr[1] = top & 0xff;
198 addr[0] = (top & 0xff00) >> 8;
199 } else {
200 addr[0] = bottom & 0xff;
201 addr[1] = (bottom >> 8) & 0xff;
202 addr[2] = (bottom >> 16) & 0xff;
203 addr[3] = (bottom >> 24) & 0xff;
204 addr[4] = top & 0xff;
205 addr[5] = (top >> 8) & 0xff;
206 }
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100207
Joachim Eastwood17b8bb32012-11-07 08:14:50 +0000208 if (is_valid_ether_addr(addr)) {
209 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
210 return;
211 }
Sven Schnelled1d57412008-06-09 16:33:57 -0700212 }
Joachim Eastwood17b8bb32012-11-07 08:14:50 +0000213
Andy Shevchenkoa35919e2015-07-24 21:24:01 +0300214 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
Joachim Eastwood17b8bb32012-11-07 08:14:50 +0000215 eth_hw_addr_random(bp->dev);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100216}
217
frederic RODO6c36a702007-07-12 19:07:24 +0200218static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100219{
frederic RODO6c36a702007-07-12 19:07:24 +0200220 struct macb *bp = bus->priv;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100221 int value;
222
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100223 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
224 | MACB_BF(RW, MACB_MAN_READ)
frederic RODO6c36a702007-07-12 19:07:24 +0200225 | MACB_BF(PHYA, mii_id)
226 | MACB_BF(REGA, regnum)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100227 | MACB_BF(CODE, MACB_MAN_CODE)));
228
frederic RODO6c36a702007-07-12 19:07:24 +0200229 /* wait for end of transfer */
230 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
231 cpu_relax();
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100232
233 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100234
235 return value;
236}
237
frederic RODO6c36a702007-07-12 19:07:24 +0200238static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
239 u16 value)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100240{
frederic RODO6c36a702007-07-12 19:07:24 +0200241 struct macb *bp = bus->priv;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100242
243 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
244 | MACB_BF(RW, MACB_MAN_WRITE)
frederic RODO6c36a702007-07-12 19:07:24 +0200245 | MACB_BF(PHYA, mii_id)
246 | MACB_BF(REGA, regnum)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100247 | MACB_BF(CODE, MACB_MAN_CODE)
frederic RODO6c36a702007-07-12 19:07:24 +0200248 | MACB_BF(DATA, value)));
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100249
frederic RODO6c36a702007-07-12 19:07:24 +0200250 /* wait for end of transfer */
251 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
252 cpu_relax();
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100253
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100254 return 0;
255}
256
Soren Brinkmanne1824df2013-12-10 16:07:23 -0800257/**
258 * macb_set_tx_clk() - Set a clock to a new frequency
259 * @clk Pointer to the clock to change
260 * @rate New frequency in Hz
261 * @dev Pointer to the struct net_device
262 */
263static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
264{
265 long ferr, rate, rate_rounded;
266
Cyrille Pitchen93b31f42015-03-07 07:23:31 +0100267 if (!clk)
268 return;
269
Soren Brinkmanne1824df2013-12-10 16:07:23 -0800270 switch (speed) {
271 case SPEED_10:
272 rate = 2500000;
273 break;
274 case SPEED_100:
275 rate = 25000000;
276 break;
277 case SPEED_1000:
278 rate = 125000000;
279 break;
280 default:
Soren Brinkmann9319e472013-12-10 20:57:57 -0800281 return;
Soren Brinkmanne1824df2013-12-10 16:07:23 -0800282 }
283
284 rate_rounded = clk_round_rate(clk, rate);
285 if (rate_rounded < 0)
286 return;
287
288 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
289 * is not satisfied.
290 */
291 ferr = abs(rate_rounded - rate);
292 ferr = DIV_ROUND_UP(ferr, rate / 100000);
293 if (ferr > 5)
294 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
295 rate);
296
297 if (clk_set_rate(clk, rate_rounded))
298 netdev_err(dev, "adjusting tx_clk failed.\n");
299}
300
frederic RODO6c36a702007-07-12 19:07:24 +0200301static void macb_handle_link_change(struct net_device *dev)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100302{
frederic RODO6c36a702007-07-12 19:07:24 +0200303 struct macb *bp = netdev_priv(dev);
304 struct phy_device *phydev = bp->phy_dev;
305 unsigned long flags;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100306
frederic RODO6c36a702007-07-12 19:07:24 +0200307 int status_change = 0;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100308
frederic RODO6c36a702007-07-12 19:07:24 +0200309 spin_lock_irqsave(&bp->lock, flags);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100310
frederic RODO6c36a702007-07-12 19:07:24 +0200311 if (phydev->link) {
312 if ((bp->speed != phydev->speed) ||
313 (bp->duplex != phydev->duplex)) {
314 u32 reg;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100315
frederic RODO6c36a702007-07-12 19:07:24 +0200316 reg = macb_readl(bp, NCFGR);
317 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
Patrice Vilchez140b7552012-10-31 06:04:50 +0000318 if (macb_is_gem(bp))
319 reg &= ~GEM_BIT(GBE);
frederic RODO6c36a702007-07-12 19:07:24 +0200320
321 if (phydev->duplex)
322 reg |= MACB_BIT(FD);
Atsushi Nemoto179956f2008-02-21 22:50:54 +0900323 if (phydev->speed == SPEED_100)
frederic RODO6c36a702007-07-12 19:07:24 +0200324 reg |= MACB_BIT(SPD);
Nicolas Ferree1755872014-07-24 13:50:58 +0200325 if (phydev->speed == SPEED_1000 &&
326 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
Patrice Vilchez140b7552012-10-31 06:04:50 +0000327 reg |= GEM_BIT(GBE);
frederic RODO6c36a702007-07-12 19:07:24 +0200328
Patrice Vilchez140b7552012-10-31 06:04:50 +0000329 macb_or_gem_writel(bp, NCFGR, reg);
frederic RODO6c36a702007-07-12 19:07:24 +0200330
331 bp->speed = phydev->speed;
332 bp->duplex = phydev->duplex;
333 status_change = 1;
334 }
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100335 }
336
frederic RODO6c36a702007-07-12 19:07:24 +0200337 if (phydev->link != bp->link) {
Anton Vorontsovc8f15682008-07-22 15:41:24 -0700338 if (!phydev->link) {
frederic RODO6c36a702007-07-12 19:07:24 +0200339 bp->speed = 0;
340 bp->duplex = -1;
341 }
342 bp->link = phydev->link;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100343
frederic RODO6c36a702007-07-12 19:07:24 +0200344 status_change = 1;
345 }
346
347 spin_unlock_irqrestore(&bp->lock, flags);
348
349 if (status_change) {
Nicolas Ferre03fc4722012-07-03 23:14:13 +0000350 if (phydev->link) {
Jaeden Amero2c29b232015-03-12 18:07:54 -0500351 /* Update the TX clock rate if and only if the link is
352 * up and there has been a link change.
353 */
354 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
355
Nicolas Ferre03fc4722012-07-03 23:14:13 +0000356 netif_carrier_on(dev);
Jamie Ilesc220f8c2011-03-08 20:27:08 +0000357 netdev_info(dev, "link up (%d/%s)\n",
358 phydev->speed,
359 phydev->duplex == DUPLEX_FULL ?
360 "Full" : "Half");
Nicolas Ferre03fc4722012-07-03 23:14:13 +0000361 } else {
362 netif_carrier_off(dev);
Jamie Ilesc220f8c2011-03-08 20:27:08 +0000363 netdev_info(dev, "link down\n");
Nicolas Ferre03fc4722012-07-03 23:14:13 +0000364 }
frederic RODO6c36a702007-07-12 19:07:24 +0200365 }
366}
367
368/* based on au1000_eth. c*/
369static int macb_mii_probe(struct net_device *dev)
370{
371 struct macb *bp = netdev_priv(dev);
Joachim Eastwood2dbfdbb2012-11-11 13:56:27 +0000372 struct macb_platform_data *pdata;
Jiri Pirko7455a762010-02-08 05:12:08 +0000373 struct phy_device *phydev;
Joachim Eastwood2dbfdbb2012-11-11 13:56:27 +0000374 int phy_irq;
Jiri Pirko7455a762010-02-08 05:12:08 +0000375 int ret;
frederic RODO6c36a702007-07-12 19:07:24 +0200376
Jiri Pirko7455a762010-02-08 05:12:08 +0000377 phydev = phy_find_first(bp->mii_bus);
frederic RODO6c36a702007-07-12 19:07:24 +0200378 if (!phydev) {
Jamie Ilesc220f8c2011-03-08 20:27:08 +0000379 netdev_err(dev, "no PHY found\n");
Boris BREZILLON7daa78e2013-08-27 14:36:14 +0200380 return -ENXIO;
frederic RODO6c36a702007-07-12 19:07:24 +0200381 }
382
Joachim Eastwood2dbfdbb2012-11-11 13:56:27 +0000383 pdata = dev_get_platdata(&bp->pdev->dev);
384 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
385 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
386 if (!ret) {
387 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
388 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
389 }
390 }
frederic RODO6c36a702007-07-12 19:07:24 +0200391
392 /* attach the mac to the phy */
Florian Fainellif9a8f832013-01-14 00:52:52 +0000393 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
Jean-Christophe PLAGNIOL-VILLARDfb97a842011-11-18 15:29:25 +0100394 bp->phy_interface);
Jiri Pirko7455a762010-02-08 05:12:08 +0000395 if (ret) {
Jamie Ilesc220f8c2011-03-08 20:27:08 +0000396 netdev_err(dev, "Could not attach to PHY\n");
Jiri Pirko7455a762010-02-08 05:12:08 +0000397 return ret;
frederic RODO6c36a702007-07-12 19:07:24 +0200398 }
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100399
frederic RODO6c36a702007-07-12 19:07:24 +0200400 /* mask with MAC supported features */
Nicolas Ferree1755872014-07-24 13:50:58 +0200401 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
Patrice Vilchez140b7552012-10-31 06:04:50 +0000402 phydev->supported &= PHY_GBIT_FEATURES;
403 else
404 phydev->supported &= PHY_BASIC_FEATURES;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100405
Nathan Sullivan222ca8e2015-05-22 09:22:10 -0500406 if (bp->caps & MACB_CAPS_NO_GIGABIT_HALF)
407 phydev->supported &= ~SUPPORTED_1000baseT_Half;
408
frederic RODO6c36a702007-07-12 19:07:24 +0200409 phydev->advertising = phydev->supported;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100410
frederic RODO6c36a702007-07-12 19:07:24 +0200411 bp->link = 0;
412 bp->speed = 0;
413 bp->duplex = -1;
414 bp->phy_dev = phydev;
415
416 return 0;
417}
418
Cyrille Pitchen421d9df2015-03-07 07:23:32 +0100419static int macb_mii_init(struct macb *bp)
frederic RODO6c36a702007-07-12 19:07:24 +0200420{
Jamie Iles84e0cdb2011-03-08 20:17:06 +0000421 struct macb_platform_data *pdata;
Boris BREZILLON148cbb52013-08-22 17:57:28 +0200422 struct device_node *np;
frederic RODO6c36a702007-07-12 19:07:24 +0200423 int err = -ENXIO, i;
424
Uwe Kleine-Koenig3dbda772009-07-23 08:31:31 +0200425 /* Enable management port */
frederic RODO6c36a702007-07-12 19:07:24 +0200426 macb_writel(bp, NCR, MACB_BIT(MPE));
427
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -0700428 bp->mii_bus = mdiobus_alloc();
429 if (bp->mii_bus == NULL) {
frederic RODO6c36a702007-07-12 19:07:24 +0200430 err = -ENOMEM;
431 goto err_out;
432 }
433
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -0700434 bp->mii_bus->name = "MACB_mii_bus";
435 bp->mii_bus->read = &macb_mdio_read;
436 bp->mii_bus->write = &macb_mdio_write;
Florian Fainelli98d5e572012-01-09 23:59:11 +0000437 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
438 bp->pdev->name, bp->pdev->id);
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -0700439 bp->mii_bus->priv = bp;
440 bp->mii_bus->parent = &bp->dev->dev;
Jingoo Hanc607a0d2013-08-30 14:12:21 +0900441 pdata = dev_get_platdata(&bp->pdev->dev);
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -0700442
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -0700443 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
444 if (!bp->mii_bus->irq) {
445 err = -ENOMEM;
446 goto err_out_free_mdiobus;
447 }
448
Jamie Iles91523942011-02-28 04:05:25 +0000449 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
frederic RODO6c36a702007-07-12 19:07:24 +0200450
Boris BREZILLON148cbb52013-08-22 17:57:28 +0200451 np = bp->pdev->dev.of_node;
452 if (np) {
453 /* try dt phy registration */
454 err = of_mdiobus_register(bp->mii_bus, np);
455
456 /* fallback to standard phy registration if no phy were
457 found during dt phy registration */
458 if (!err && !phy_find_first(bp->mii_bus)) {
459 for (i = 0; i < PHY_MAX_ADDR; i++) {
460 struct phy_device *phydev;
461
462 phydev = mdiobus_scan(bp->mii_bus, i);
463 if (IS_ERR(phydev)) {
464 err = PTR_ERR(phydev);
465 break;
466 }
467 }
468
469 if (err)
470 goto err_out_unregister_bus;
471 }
472 } else {
473 for (i = 0; i < PHY_MAX_ADDR; i++)
474 bp->mii_bus->irq[i] = PHY_POLL;
475
476 if (pdata)
477 bp->mii_bus->phy_mask = pdata->phy_mask;
478
479 err = mdiobus_register(bp->mii_bus);
480 }
481
482 if (err)
frederic RODO6c36a702007-07-12 19:07:24 +0200483 goto err_out_free_mdio_irq;
484
Boris BREZILLON7daa78e2013-08-27 14:36:14 +0200485 err = macb_mii_probe(bp->dev);
486 if (err)
frederic RODO6c36a702007-07-12 19:07:24 +0200487 goto err_out_unregister_bus;
frederic RODO6c36a702007-07-12 19:07:24 +0200488
489 return 0;
490
491err_out_unregister_bus:
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -0700492 mdiobus_unregister(bp->mii_bus);
frederic RODO6c36a702007-07-12 19:07:24 +0200493err_out_free_mdio_irq:
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -0700494 kfree(bp->mii_bus->irq);
495err_out_free_mdiobus:
496 mdiobus_free(bp->mii_bus);
frederic RODO6c36a702007-07-12 19:07:24 +0200497err_out:
498 return err;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100499}
500
501static void macb_update_stats(struct macb *bp)
502{
Jamie Ilesa494ed82011-03-09 16:26:35 +0000503 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
504 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +0300505 int offset = MACB_PFR;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100506
507 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
508
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +0300509 for(; p < end; p++, offset += 4)
510 *p += bp->readl(bp, offset);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100511}
512
Nicolas Ferree86cd532012-10-31 06:04:57 +0000513static int macb_halt_tx(struct macb *bp)
514{
515 unsigned long halt_time, timeout;
516 u32 status;
517
518 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
519
520 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
521 do {
522 halt_time = jiffies;
523 status = macb_readl(bp, TSR);
524 if (!(status & MACB_BIT(TGO)))
525 return 0;
526
527 usleep_range(10, 250);
528 } while (time_before(halt_time, timeout));
529
530 return -ETIMEDOUT;
531}
532
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +0200533static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
534{
535 if (tx_skb->mapping) {
536 if (tx_skb->mapped_as_page)
537 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
538 tx_skb->size, DMA_TO_DEVICE);
539 else
540 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
541 tx_skb->size, DMA_TO_DEVICE);
542 tx_skb->mapping = 0;
543 }
544
545 if (tx_skb->skb) {
546 dev_kfree_skb_any(tx_skb->skb);
547 tx_skb->skb = NULL;
548 }
549}
550
Nicolas Ferree86cd532012-10-31 06:04:57 +0000551static void macb_tx_error_task(struct work_struct *work)
552{
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100553 struct macb_queue *queue = container_of(work, struct macb_queue,
554 tx_error_task);
555 struct macb *bp = queue->bp;
Nicolas Ferree86cd532012-10-31 06:04:57 +0000556 struct macb_tx_skb *tx_skb;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100557 struct macb_dma_desc *desc;
Nicolas Ferree86cd532012-10-31 06:04:57 +0000558 struct sk_buff *skb;
559 unsigned int tail;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100560 unsigned long flags;
Nicolas Ferree86cd532012-10-31 06:04:57 +0000561
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100562 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
563 (unsigned int)(queue - bp->queues),
564 queue->tx_tail, queue->tx_head);
565
566 /* Prevent the queue IRQ handlers from running: each of them may call
567 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
568 * As explained below, we have to halt the transmission before updating
569 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
570 * network engine about the macb/gem being halted.
571 */
572 spin_lock_irqsave(&bp->lock, flags);
Nicolas Ferree86cd532012-10-31 06:04:57 +0000573
574 /* Make sure nobody is trying to queue up new packets */
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100575 netif_tx_stop_all_queues(bp->dev);
Nicolas Ferree86cd532012-10-31 06:04:57 +0000576
577 /*
578 * Stop transmission now
579 * (in case we have just queued new packets)
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100580 * macb/gem must be halted to write TBQP register
Nicolas Ferree86cd532012-10-31 06:04:57 +0000581 */
582 if (macb_halt_tx(bp))
583 /* Just complain for now, reinitializing TX path can be good */
584 netdev_err(bp->dev, "BUG: halt tx timed out\n");
585
Nicolas Ferree86cd532012-10-31 06:04:57 +0000586 /*
587 * Treat frames in TX queue including the ones that caused the error.
588 * Free transmit buffers in upper layer.
589 */
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100590 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
591 u32 ctrl;
Nicolas Ferree86cd532012-10-31 06:04:57 +0000592
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100593 desc = macb_tx_desc(queue, tail);
Nicolas Ferree86cd532012-10-31 06:04:57 +0000594 ctrl = desc->ctrl;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100595 tx_skb = macb_tx_skb(queue, tail);
Nicolas Ferree86cd532012-10-31 06:04:57 +0000596 skb = tx_skb->skb;
597
598 if (ctrl & MACB_BIT(TX_USED)) {
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +0200599 /* skb is set for the last buffer of the frame */
600 while (!skb) {
601 macb_tx_unmap(bp, tx_skb);
602 tail++;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100603 tx_skb = macb_tx_skb(queue, tail);
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +0200604 skb = tx_skb->skb;
605 }
606
607 /* ctrl still refers to the first buffer descriptor
608 * since it's the only one written back by the hardware
609 */
610 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
611 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
612 macb_tx_ring_wrap(tail), skb->data);
613 bp->stats.tx_packets++;
614 bp->stats.tx_bytes += skb->len;
615 }
Nicolas Ferree86cd532012-10-31 06:04:57 +0000616 } else {
617 /*
618 * "Buffers exhausted mid-frame" errors may only happen
619 * if the driver is buggy, so complain loudly about those.
620 * Statistics are updated by hardware.
621 */
622 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
623 netdev_err(bp->dev,
624 "BUG: TX buffers exhausted mid-frame\n");
625
626 desc->ctrl = ctrl | MACB_BIT(TX_USED);
627 }
628
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +0200629 macb_tx_unmap(bp, tx_skb);
Nicolas Ferree86cd532012-10-31 06:04:57 +0000630 }
631
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100632 /* Set end of TX queue */
633 desc = macb_tx_desc(queue, 0);
634 desc->addr = 0;
635 desc->ctrl = MACB_BIT(TX_USED);
636
Nicolas Ferree86cd532012-10-31 06:04:57 +0000637 /* Make descriptor updates visible to hardware */
638 wmb();
639
640 /* Reinitialize the TX desc queue */
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100641 queue_writel(queue, TBQP, queue->tx_ring_dma);
Nicolas Ferree86cd532012-10-31 06:04:57 +0000642 /* Make TX ring reflect state of hardware */
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100643 queue->tx_head = 0;
644 queue->tx_tail = 0;
Nicolas Ferree86cd532012-10-31 06:04:57 +0000645
646 /* Housework before enabling TX IRQ */
647 macb_writel(bp, TSR, macb_readl(bp, TSR));
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100648 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
649
650 /* Now we are ready to start transmission again */
651 netif_tx_start_all_queues(bp->dev);
652 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
653
654 spin_unlock_irqrestore(&bp->lock, flags);
Nicolas Ferree86cd532012-10-31 06:04:57 +0000655}
656
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100657static void macb_tx_interrupt(struct macb_queue *queue)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100658{
659 unsigned int tail;
660 unsigned int head;
661 u32 status;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100662 struct macb *bp = queue->bp;
663 u16 queue_index = queue - bp->queues;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100664
665 status = macb_readl(bp, TSR);
666 macb_writel(bp, TSR, status);
667
Nicolas Ferre581df9e2013-05-14 03:00:16 +0000668 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100669 queue_writel(queue, ISR, MACB_BIT(TCOMP));
Steffen Trumtrar749a2b62013-03-27 23:07:05 +0000670
Nicolas Ferree86cd532012-10-31 06:04:57 +0000671 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
672 (unsigned long)status);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100673
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100674 head = queue->tx_head;
675 for (tail = queue->tx_tail; tail != head; tail++) {
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000676 struct macb_tx_skb *tx_skb;
677 struct sk_buff *skb;
678 struct macb_dma_desc *desc;
679 u32 ctrl;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100680
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100681 desc = macb_tx_desc(queue, tail);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100682
Havard Skinnemoen03dbe052012-10-31 06:04:51 +0000683 /* Make hw descriptor updates visible to CPU */
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100684 rmb();
Havard Skinnemoen03dbe052012-10-31 06:04:51 +0000685
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000686 ctrl = desc->ctrl;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100687
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +0200688 /* TX_USED bit is only set by hardware on the very first buffer
689 * descriptor of the transmitted frame.
690 */
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000691 if (!(ctrl & MACB_BIT(TX_USED)))
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100692 break;
693
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +0200694 /* Process all buffers of the current transmitted frame */
695 for (;; tail++) {
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100696 tx_skb = macb_tx_skb(queue, tail);
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +0200697 skb = tx_skb->skb;
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000698
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +0200699 /* First, update TX stats if needed */
700 if (skb) {
701 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
702 macb_tx_ring_wrap(tail), skb->data);
703 bp->stats.tx_packets++;
704 bp->stats.tx_bytes += skb->len;
705 }
706
707 /* Now we can safely release resources */
708 macb_tx_unmap(bp, tx_skb);
709
710 /* skb is set only for the last buffer of the frame.
711 * WARNING: at this point skb has been freed by
712 * macb_tx_unmap().
713 */
714 if (skb)
715 break;
716 }
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100717 }
718
Cyrille Pitchen02c958d2014-12-12 13:26:44 +0100719 queue->tx_tail = tail;
720 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
721 CIRC_CNT(queue->tx_head, queue->tx_tail,
722 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
723 netif_wake_subqueue(bp->dev, queue_index);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100724}
725
Nicolas Ferre4df95132013-06-04 21:57:12 +0000726static void gem_rx_refill(struct macb *bp)
727{
728 unsigned int entry;
729 struct sk_buff *skb;
Nicolas Ferre4df95132013-06-04 21:57:12 +0000730 dma_addr_t paddr;
731
732 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
Nicolas Ferre4df95132013-06-04 21:57:12 +0000733 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
Nicolas Ferre4df95132013-06-04 21:57:12 +0000734
735 /* Make hw descriptor updates visible to CPU */
736 rmb();
737
Nicolas Ferre4df95132013-06-04 21:57:12 +0000738 bp->rx_prepared_head++;
739
Nicolas Ferre4df95132013-06-04 21:57:12 +0000740 if (bp->rx_skbuff[entry] == NULL) {
741 /* allocate sk_buff for this free entry in ring */
742 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
743 if (unlikely(skb == NULL)) {
744 netdev_err(bp->dev,
745 "Unable to allocate sk_buff\n");
746 break;
747 }
Nicolas Ferre4df95132013-06-04 21:57:12 +0000748
749 /* now fill corresponding descriptor entry */
750 paddr = dma_map_single(&bp->pdev->dev, skb->data,
751 bp->rx_buffer_size, DMA_FROM_DEVICE);
Soren Brinkmann92030902014-03-04 08:46:39 -0800752 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
753 dev_kfree_skb(skb);
754 break;
755 }
756
757 bp->rx_skbuff[entry] = skb;
Nicolas Ferre4df95132013-06-04 21:57:12 +0000758
759 if (entry == RX_RING_SIZE - 1)
760 paddr |= MACB_BIT(RX_WRAP);
761 bp->rx_ring[entry].addr = paddr;
762 bp->rx_ring[entry].ctrl = 0;
763
764 /* properly align Ethernet header */
765 skb_reserve(skb, NET_IP_ALIGN);
Punnaiah Choudary Kallurid4c216c2015-04-29 08:34:46 +0530766 } else {
767 bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
768 bp->rx_ring[entry].ctrl = 0;
Nicolas Ferre4df95132013-06-04 21:57:12 +0000769 }
770 }
771
772 /* Make descriptor updates visible to hardware */
773 wmb();
774
775 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
776 bp->rx_prepared_head, bp->rx_tail);
777}
778
779/* Mark DMA descriptors from begin up to and not including end as unused */
780static void discard_partial_frame(struct macb *bp, unsigned int begin,
781 unsigned int end)
782{
783 unsigned int frag;
784
785 for (frag = begin; frag != end; frag++) {
786 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
787 desc->addr &= ~MACB_BIT(RX_USED);
788 }
789
790 /* Make descriptor updates visible to hardware */
791 wmb();
792
793 /*
794 * When this happens, the hardware stats registers for
795 * whatever caused this is updated, so we don't have to record
796 * anything.
797 */
798}
799
800static int gem_rx(struct macb *bp, int budget)
801{
802 unsigned int len;
803 unsigned int entry;
804 struct sk_buff *skb;
805 struct macb_dma_desc *desc;
806 int count = 0;
807
808 while (count < budget) {
809 u32 addr, ctrl;
810
811 entry = macb_rx_ring_wrap(bp->rx_tail);
812 desc = &bp->rx_ring[entry];
813
814 /* Make hw descriptor updates visible to CPU */
815 rmb();
816
817 addr = desc->addr;
818 ctrl = desc->ctrl;
819
820 if (!(addr & MACB_BIT(RX_USED)))
821 break;
822
Nicolas Ferre4df95132013-06-04 21:57:12 +0000823 bp->rx_tail++;
824 count++;
825
826 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
827 netdev_err(bp->dev,
828 "not whole frame pointed by descriptor\n");
829 bp->stats.rx_dropped++;
830 break;
831 }
832 skb = bp->rx_skbuff[entry];
833 if (unlikely(!skb)) {
834 netdev_err(bp->dev,
835 "inconsistent Rx descriptor chain\n");
836 bp->stats.rx_dropped++;
837 break;
838 }
839 /* now everything is ready for receiving packet */
840 bp->rx_skbuff[entry] = NULL;
Harini Katakam98b5a0f42015-05-06 22:27:17 +0530841 len = ctrl & bp->rx_frm_len_mask;
Nicolas Ferre4df95132013-06-04 21:57:12 +0000842
843 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
844
845 skb_put(skb, len);
846 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
847 dma_unmap_single(&bp->pdev->dev, addr,
Soren Brinkmann48330e082014-03-04 08:46:40 -0800848 bp->rx_buffer_size, DMA_FROM_DEVICE);
Nicolas Ferre4df95132013-06-04 21:57:12 +0000849
850 skb->protocol = eth_type_trans(skb, bp->dev);
851 skb_checksum_none_assert(skb);
Cyrille Pitchen924ec532014-07-24 13:51:01 +0200852 if (bp->dev->features & NETIF_F_RXCSUM &&
853 !(bp->dev->flags & IFF_PROMISC) &&
854 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
855 skb->ip_summed = CHECKSUM_UNNECESSARY;
Nicolas Ferre4df95132013-06-04 21:57:12 +0000856
857 bp->stats.rx_packets++;
858 bp->stats.rx_bytes += skb->len;
859
860#if defined(DEBUG) && defined(VERBOSE_DEBUG)
861 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
862 skb->len, skb->csum);
863 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
Cyrille Pitchen51f83012014-12-11 11:15:54 +0100864 skb_mac_header(skb), 16, true);
Nicolas Ferre4df95132013-06-04 21:57:12 +0000865 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
866 skb->data, 32, true);
867#endif
868
869 netif_receive_skb(skb);
870 }
871
872 gem_rx_refill(bp);
873
874 return count;
875}
876
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100877static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
878 unsigned int last_frag)
879{
880 unsigned int len;
881 unsigned int frag;
Havard Skinnemoen29bc2e12012-10-31 06:04:58 +0000882 unsigned int offset;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100883 struct sk_buff *skb;
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000884 struct macb_dma_desc *desc;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100885
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000886 desc = macb_rx_desc(bp, last_frag);
Harini Katakam98b5a0f42015-05-06 22:27:17 +0530887 len = desc->ctrl & bp->rx_frm_len_mask;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100888
Havard Skinnemoena268adb2012-10-31 06:04:52 +0000889 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000890 macb_rx_ring_wrap(first_frag),
891 macb_rx_ring_wrap(last_frag), len);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100892
Havard Skinnemoen29bc2e12012-10-31 06:04:58 +0000893 /*
894 * The ethernet header starts NET_IP_ALIGN bytes into the
895 * first buffer. Since the header is 14 bytes, this makes the
896 * payload word-aligned.
897 *
898 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
899 * the two padding bytes into the skb so that we avoid hitting
900 * the slowpath in memcpy(), and pull them off afterwards.
901 */
902 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100903 if (!skb) {
904 bp->stats.rx_dropped++;
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000905 for (frag = first_frag; ; frag++) {
906 desc = macb_rx_desc(bp, frag);
907 desc->addr &= ~MACB_BIT(RX_USED);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100908 if (frag == last_frag)
909 break;
910 }
Havard Skinnemoen03dbe052012-10-31 06:04:51 +0000911
912 /* Make descriptor updates visible to hardware */
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100913 wmb();
Havard Skinnemoen03dbe052012-10-31 06:04:51 +0000914
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100915 return 1;
916 }
917
Havard Skinnemoen29bc2e12012-10-31 06:04:58 +0000918 offset = 0;
919 len += NET_IP_ALIGN;
Eric Dumazetbc8acf22010-09-02 13:07:41 -0700920 skb_checksum_none_assert(skb);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100921 skb_put(skb, len);
922
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000923 for (frag = first_frag; ; frag++) {
Nicolas Ferre1b447912013-06-04 21:57:11 +0000924 unsigned int frag_len = bp->rx_buffer_size;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100925
926 if (offset + frag_len > len) {
927 BUG_ON(frag != last_frag);
928 frag_len = len - offset;
929 }
Arnaldo Carvalho de Melo27d7ff42007-03-31 11:55:19 -0300930 skb_copy_to_linear_data_offset(skb, offset,
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000931 macb_rx_buffer(bp, frag), frag_len);
Nicolas Ferre1b447912013-06-04 21:57:11 +0000932 offset += bp->rx_buffer_size;
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000933 desc = macb_rx_desc(bp, frag);
934 desc->addr &= ~MACB_BIT(RX_USED);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100935
936 if (frag == last_frag)
937 break;
938 }
939
Havard Skinnemoen03dbe052012-10-31 06:04:51 +0000940 /* Make descriptor updates visible to hardware */
941 wmb();
942
Havard Skinnemoen29bc2e12012-10-31 06:04:58 +0000943 __skb_pull(skb, NET_IP_ALIGN);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100944 skb->protocol = eth_type_trans(skb, bp->dev);
945
946 bp->stats.rx_packets++;
Havard Skinnemoen29bc2e12012-10-31 06:04:58 +0000947 bp->stats.rx_bytes += skb->len;
Havard Skinnemoena268adb2012-10-31 06:04:52 +0000948 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
Jamie Ilesc220f8c2011-03-08 20:27:08 +0000949 skb->len, skb->csum);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100950 netif_receive_skb(skb);
951
952 return 0;
953}
954
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100955static int macb_rx(struct macb *bp, int budget)
956{
957 int received = 0;
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000958 unsigned int tail;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100959 int first_frag = -1;
960
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000961 for (tail = bp->rx_tail; budget > 0; tail++) {
962 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100963 u32 addr, ctrl;
964
Havard Skinnemoen03dbe052012-10-31 06:04:51 +0000965 /* Make hw descriptor updates visible to CPU */
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100966 rmb();
Havard Skinnemoen03dbe052012-10-31 06:04:51 +0000967
Havard Skinnemoen55054a12012-10-31 06:04:55 +0000968 addr = desc->addr;
969 ctrl = desc->ctrl;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +0100970
971 if (!(addr & MACB_BIT(RX_USED)))
972 break;
973
974 if (ctrl & MACB_BIT(RX_SOF)) {
975 if (first_frag != -1)
976 discard_partial_frame(bp, first_frag, tail);
977 first_frag = tail;
978 }
979
980 if (ctrl & MACB_BIT(RX_EOF)) {
981 int dropped;
982 BUG_ON(first_frag == -1);
983
984 dropped = macb_rx_frame(bp, first_frag, tail);
985 first_frag = -1;
986 if (!dropped) {
987 received++;
988 budget--;
989 }
990 }
991 }
992
993 if (first_frag != -1)
994 bp->rx_tail = first_frag;
995 else
996 bp->rx_tail = tail;
997
998 return received;
999}
1000
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001001static int macb_poll(struct napi_struct *napi, int budget)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001002{
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001003 struct macb *bp = container_of(napi, struct macb, napi);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001004 int work_done;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001005 u32 status;
1006
1007 status = macb_readl(bp, RSR);
1008 macb_writel(bp, RSR, status);
1009
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001010 work_done = 0;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001011
Havard Skinnemoena268adb2012-10-31 06:04:52 +00001012 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
Jamie Ilesc220f8c2011-03-08 20:27:08 +00001013 (unsigned long)status, budget);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001014
Nicolas Ferre4df95132013-06-04 21:57:12 +00001015 work_done = bp->macbgem_ops.mog_rx(bp, budget);
Joshua Hokeb3363692010-10-25 01:44:22 +00001016 if (work_done < budget) {
Ben Hutchings288379f2009-01-19 16:43:59 -08001017 napi_complete(napi);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001018
Nicolas Ferre8770e912013-02-12 11:08:48 +01001019 /* Packets received while interrupts were disabled */
1020 status = macb_readl(bp, RSR);
Soren Brinkmann504ad982014-05-04 15:43:01 -07001021 if (status) {
Soren Brinkmann02f7a342014-05-04 15:43:00 -07001022 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1023 macb_writel(bp, ISR, MACB_BIT(RCOMP));
Nicolas Ferre8770e912013-02-12 11:08:48 +01001024 napi_reschedule(napi);
Soren Brinkmann02f7a342014-05-04 15:43:00 -07001025 } else {
1026 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
1027 }
Joshua Hokeb3363692010-10-25 01:44:22 +00001028 }
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001029
1030 /* TODO: Handle errors */
1031
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001032 return work_done;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001033}
1034
1035static irqreturn_t macb_interrupt(int irq, void *dev_id)
1036{
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001037 struct macb_queue *queue = dev_id;
1038 struct macb *bp = queue->bp;
1039 struct net_device *dev = bp->dev;
Nathan Sullivanbfbb92c2015-05-05 15:00:25 -05001040 u32 status, ctrl;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001041
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001042 status = queue_readl(queue, ISR);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001043
1044 if (unlikely(!status))
1045 return IRQ_NONE;
1046
1047 spin_lock(&bp->lock);
1048
1049 while (status) {
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001050 /* close possible race with dev_close */
1051 if (unlikely(!netif_running(dev))) {
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001052 queue_writel(queue, IDR, -1);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001053 break;
1054 }
1055
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001056 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1057 (unsigned int)(queue - bp->queues),
1058 (unsigned long)status);
Havard Skinnemoena268adb2012-10-31 06:04:52 +00001059
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001060 if (status & MACB_RX_INT_FLAGS) {
Joshua Hokeb3363692010-10-25 01:44:22 +00001061 /*
1062 * There's no point taking any more interrupts
1063 * until we have processed the buffers. The
1064 * scheduling call may fail if the poll routine
1065 * is already scheduled, so disable interrupts
1066 * now.
1067 */
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001068 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
Nicolas Ferre581df9e2013-05-14 03:00:16 +00001069 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001070 queue_writel(queue, ISR, MACB_BIT(RCOMP));
Joshua Hokeb3363692010-10-25 01:44:22 +00001071
Ben Hutchings288379f2009-01-19 16:43:59 -08001072 if (napi_schedule_prep(&bp->napi)) {
Havard Skinnemoena268adb2012-10-31 06:04:52 +00001073 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
Ben Hutchings288379f2009-01-19 16:43:59 -08001074 __napi_schedule(&bp->napi);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001075 }
1076 }
1077
Nicolas Ferree86cd532012-10-31 06:04:57 +00001078 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001079 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1080 schedule_work(&queue->tx_error_task);
Soren Brinkmann6a027b72014-05-04 15:42:59 -07001081
1082 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001083 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
Soren Brinkmann6a027b72014-05-04 15:42:59 -07001084
Nicolas Ferree86cd532012-10-31 06:04:57 +00001085 break;
1086 }
1087
1088 if (status & MACB_BIT(TCOMP))
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001089 macb_tx_interrupt(queue);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001090
1091 /*
1092 * Link change detection isn't possible with RMII, so we'll
1093 * add that if/when we get our hands on a full-blown MII PHY.
1094 */
1095
Nathan Sullivan86b5e7d2015-05-13 17:01:36 -05001096 /* There is a hardware issue under heavy load where DMA can
1097 * stop, this causes endless "used buffer descriptor read"
1098 * interrupts but it can be cleared by re-enabling RX. See
1099 * the at91 manual, section 41.3.1 or the Zynq manual
1100 * section 16.7.4 for details.
1101 */
Nathan Sullivanbfbb92c2015-05-05 15:00:25 -05001102 if (status & MACB_BIT(RXUBR)) {
1103 ctrl = macb_readl(bp, NCR);
1104 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1105 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1106
1107 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1108 macb_writel(bp, ISR, MACB_BIT(RXUBR));
1109 }
1110
Alexander Steinb19f7f72011-04-13 05:03:24 +00001111 if (status & MACB_BIT(ISR_ROVR)) {
1112 /* We missed at least one packet */
Jamie Ilesf75ba502011-11-08 10:12:32 +00001113 if (macb_is_gem(bp))
1114 bp->hw_stats.gem.rx_overruns++;
1115 else
1116 bp->hw_stats.macb.rx_overruns++;
Soren Brinkmann6a027b72014-05-04 15:42:59 -07001117
1118 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001119 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
Alexander Steinb19f7f72011-04-13 05:03:24 +00001120 }
1121
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001122 if (status & MACB_BIT(HRESP)) {
1123 /*
Jamie Ilesc220f8c2011-03-08 20:27:08 +00001124 * TODO: Reset the hardware, and maybe move the
1125 * netdev_err to a lower-priority context as well
1126 * (work queue?)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001127 */
Jamie Ilesc220f8c2011-03-08 20:27:08 +00001128 netdev_err(dev, "DMA bus error: HRESP not OK\n");
Soren Brinkmann6a027b72014-05-04 15:42:59 -07001129
1130 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001131 queue_writel(queue, ISR, MACB_BIT(HRESP));
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001132 }
1133
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001134 status = queue_readl(queue, ISR);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001135 }
1136
1137 spin_unlock(&bp->lock);
1138
1139 return IRQ_HANDLED;
1140}
1141
Thomas Petazzoni6e8cf5c2009-05-04 11:08:41 -07001142#ifdef CONFIG_NET_POLL_CONTROLLER
1143/*
1144 * Polling receive - used by netconsole and other diagnostic tools
1145 * to allow network i/o with interrupts disabled.
1146 */
1147static void macb_poll_controller(struct net_device *dev)
1148{
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001149 struct macb *bp = netdev_priv(dev);
1150 struct macb_queue *queue;
Thomas Petazzoni6e8cf5c2009-05-04 11:08:41 -07001151 unsigned long flags;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001152 unsigned int q;
Thomas Petazzoni6e8cf5c2009-05-04 11:08:41 -07001153
1154 local_irq_save(flags);
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001155 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1156 macb_interrupt(dev->irq, queue);
Thomas Petazzoni6e8cf5c2009-05-04 11:08:41 -07001157 local_irq_restore(flags);
1158}
1159#endif
1160
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001161static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
1162 unsigned int len)
1163{
1164 return (len + bp->max_tx_length - 1) / bp->max_tx_length;
1165}
1166
1167static unsigned int macb_tx_map(struct macb *bp,
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001168 struct macb_queue *queue,
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001169 struct sk_buff *skb)
1170{
1171 dma_addr_t mapping;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001172 unsigned int len, entry, i, tx_head = queue->tx_head;
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001173 struct macb_tx_skb *tx_skb = NULL;
1174 struct macb_dma_desc *desc;
1175 unsigned int offset, size, count = 0;
1176 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1177 unsigned int eof = 1;
1178 u32 ctrl;
1179
1180 /* First, map non-paged data */
1181 len = skb_headlen(skb);
1182 offset = 0;
1183 while (len) {
1184 size = min(len, bp->max_tx_length);
1185 entry = macb_tx_ring_wrap(tx_head);
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001186 tx_skb = &queue->tx_skb[entry];
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001187
1188 mapping = dma_map_single(&bp->pdev->dev,
1189 skb->data + offset,
1190 size, DMA_TO_DEVICE);
1191 if (dma_mapping_error(&bp->pdev->dev, mapping))
1192 goto dma_error;
1193
1194 /* Save info to properly release resources */
1195 tx_skb->skb = NULL;
1196 tx_skb->mapping = mapping;
1197 tx_skb->size = size;
1198 tx_skb->mapped_as_page = false;
1199
1200 len -= size;
1201 offset += size;
1202 count++;
1203 tx_head++;
1204 }
1205
1206 /* Then, map paged data from fragments */
1207 for (f = 0; f < nr_frags; f++) {
1208 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1209
1210 len = skb_frag_size(frag);
1211 offset = 0;
1212 while (len) {
1213 size = min(len, bp->max_tx_length);
1214 entry = macb_tx_ring_wrap(tx_head);
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001215 tx_skb = &queue->tx_skb[entry];
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001216
1217 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1218 offset, size, DMA_TO_DEVICE);
1219 if (dma_mapping_error(&bp->pdev->dev, mapping))
1220 goto dma_error;
1221
1222 /* Save info to properly release resources */
1223 tx_skb->skb = NULL;
1224 tx_skb->mapping = mapping;
1225 tx_skb->size = size;
1226 tx_skb->mapped_as_page = true;
1227
1228 len -= size;
1229 offset += size;
1230 count++;
1231 tx_head++;
1232 }
1233 }
1234
1235 /* Should never happen */
1236 if (unlikely(tx_skb == NULL)) {
1237 netdev_err(bp->dev, "BUG! empty skb!\n");
1238 return 0;
1239 }
1240
1241 /* This is the last buffer of the frame: save socket buffer */
1242 tx_skb->skb = skb;
1243
1244 /* Update TX ring: update buffer descriptors in reverse order
1245 * to avoid race condition
1246 */
1247
1248 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1249 * to set the end of TX queue
1250 */
1251 i = tx_head;
1252 entry = macb_tx_ring_wrap(i);
1253 ctrl = MACB_BIT(TX_USED);
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001254 desc = &queue->tx_ring[entry];
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001255 desc->ctrl = ctrl;
1256
1257 do {
1258 i--;
1259 entry = macb_tx_ring_wrap(i);
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001260 tx_skb = &queue->tx_skb[entry];
1261 desc = &queue->tx_ring[entry];
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001262
1263 ctrl = (u32)tx_skb->size;
1264 if (eof) {
1265 ctrl |= MACB_BIT(TX_LAST);
1266 eof = 0;
1267 }
1268 if (unlikely(entry == (TX_RING_SIZE - 1)))
1269 ctrl |= MACB_BIT(TX_WRAP);
1270
1271 /* Set TX buffer descriptor */
1272 desc->addr = tx_skb->mapping;
1273 /* desc->addr must be visible to hardware before clearing
1274 * 'TX_USED' bit in desc->ctrl.
1275 */
1276 wmb();
1277 desc->ctrl = ctrl;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001278 } while (i != queue->tx_head);
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001279
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001280 queue->tx_head = tx_head;
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001281
1282 return count;
1283
1284dma_error:
1285 netdev_err(bp->dev, "TX DMA map failed\n");
1286
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001287 for (i = queue->tx_head; i != tx_head; i++) {
1288 tx_skb = macb_tx_skb(queue, i);
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001289
1290 macb_tx_unmap(bp, tx_skb);
1291 }
1292
1293 return 0;
1294}
1295
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001296static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1297{
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001298 u16 queue_index = skb_get_queue_mapping(skb);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001299 struct macb *bp = netdev_priv(dev);
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001300 struct macb_queue *queue = &bp->queues[queue_index];
Dongdong Deng48719532009-08-23 19:49:07 -07001301 unsigned long flags;
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001302 unsigned int count, nr_frags, frag_size, f;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001303
Havard Skinnemoena268adb2012-10-31 06:04:52 +00001304#if defined(DEBUG) && defined(VERBOSE_DEBUG)
1305 netdev_vdbg(bp->dev,
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001306 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1307 queue_index, skb->len, skb->head, skb->data,
Jamie Ilesc220f8c2011-03-08 20:27:08 +00001308 skb_tail_pointer(skb), skb_end_pointer(skb));
1309 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1310 skb->data, 16, true);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001311#endif
1312
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001313 /* Count how many TX buffer descriptors are needed to send this
1314 * socket buffer: skb fragments of jumbo frames may need to be
1315 * splitted into many buffer descriptors.
1316 */
1317 count = macb_count_tx_descriptors(bp, skb_headlen(skb));
1318 nr_frags = skb_shinfo(skb)->nr_frags;
1319 for (f = 0; f < nr_frags; f++) {
1320 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1321 count += macb_count_tx_descriptors(bp, frag_size);
1322 }
1323
Dongdong Deng48719532009-08-23 19:49:07 -07001324 spin_lock_irqsave(&bp->lock, flags);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001325
1326 /* This is a hard error, log it. */
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001327 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) {
1328 netif_stop_subqueue(dev, queue_index);
Dongdong Deng48719532009-08-23 19:49:07 -07001329 spin_unlock_irqrestore(&bp->lock, flags);
Jamie Ilesc220f8c2011-03-08 20:27:08 +00001330 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001331 queue->tx_head, queue->tx_tail);
Patrick McHardy5b548142009-06-12 06:22:29 +00001332 return NETDEV_TX_BUSY;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001333 }
1334
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02001335 /* Map socket buffer for DMA transfer */
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001336 if (!macb_tx_map(bp, queue, skb)) {
Eric W. Biedermanc88b5b62014-03-15 16:08:27 -07001337 dev_kfree_skb_any(skb);
Soren Brinkmann92030902014-03-04 08:46:39 -08001338 goto unlock;
1339 }
Havard Skinnemoen55054a12012-10-31 06:04:55 +00001340
Havard Skinnemoen03dbe052012-10-31 06:04:51 +00001341 /* Make newly initialized descriptor visible to hardware */
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001342 wmb();
1343
Richard Cochrane0720922011-06-19 21:51:28 +00001344 skb_tx_timestamp(skb);
1345
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001346 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1347
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001348 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1)
1349 netif_stop_subqueue(dev, queue_index);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001350
Soren Brinkmann92030902014-03-04 08:46:39 -08001351unlock:
Dongdong Deng48719532009-08-23 19:49:07 -07001352 spin_unlock_irqrestore(&bp->lock, flags);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001353
Patrick McHardy6ed10652009-06-23 06:03:08 +00001354 return NETDEV_TX_OK;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001355}
1356
Nicolas Ferre4df95132013-06-04 21:57:12 +00001357static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
Nicolas Ferre1b447912013-06-04 21:57:11 +00001358{
1359 if (!macb_is_gem(bp)) {
1360 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1361 } else {
Nicolas Ferre4df95132013-06-04 21:57:12 +00001362 bp->rx_buffer_size = size;
Nicolas Ferre1b447912013-06-04 21:57:11 +00001363
Nicolas Ferre1b447912013-06-04 21:57:11 +00001364 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
Nicolas Ferre4df95132013-06-04 21:57:12 +00001365 netdev_dbg(bp->dev,
1366 "RX buffer must be multiple of %d bytes, expanding\n",
Nicolas Ferre1b447912013-06-04 21:57:11 +00001367 RX_BUFFER_MULTIPLE);
1368 bp->rx_buffer_size =
Nicolas Ferre4df95132013-06-04 21:57:12 +00001369 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
Nicolas Ferre1b447912013-06-04 21:57:11 +00001370 }
Nicolas Ferre1b447912013-06-04 21:57:11 +00001371 }
Nicolas Ferre4df95132013-06-04 21:57:12 +00001372
1373 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1374 bp->dev->mtu, bp->rx_buffer_size);
Nicolas Ferre1b447912013-06-04 21:57:11 +00001375}
1376
Nicolas Ferre4df95132013-06-04 21:57:12 +00001377static void gem_free_rx_buffers(struct macb *bp)
1378{
1379 struct sk_buff *skb;
1380 struct macb_dma_desc *desc;
1381 dma_addr_t addr;
1382 int i;
1383
1384 if (!bp->rx_skbuff)
1385 return;
1386
1387 for (i = 0; i < RX_RING_SIZE; i++) {
1388 skb = bp->rx_skbuff[i];
1389
1390 if (skb == NULL)
1391 continue;
1392
1393 desc = &bp->rx_ring[i];
1394 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
Soren Brinkmannccd6d0a2014-05-04 15:42:58 -07001395 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
Nicolas Ferre4df95132013-06-04 21:57:12 +00001396 DMA_FROM_DEVICE);
1397 dev_kfree_skb_any(skb);
1398 skb = NULL;
1399 }
1400
1401 kfree(bp->rx_skbuff);
1402 bp->rx_skbuff = NULL;
1403}
1404
1405static void macb_free_rx_buffers(struct macb *bp)
1406{
1407 if (bp->rx_buffers) {
1408 dma_free_coherent(&bp->pdev->dev,
1409 RX_RING_SIZE * bp->rx_buffer_size,
1410 bp->rx_buffers, bp->rx_buffers_dma);
1411 bp->rx_buffers = NULL;
1412 }
1413}
Nicolas Ferre1b447912013-06-04 21:57:11 +00001414
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001415static void macb_free_consistent(struct macb *bp)
1416{
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001417 struct macb_queue *queue;
1418 unsigned int q;
1419
Nicolas Ferre4df95132013-06-04 21:57:12 +00001420 bp->macbgem_ops.mog_free_rx_buffers(bp);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001421 if (bp->rx_ring) {
1422 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1423 bp->rx_ring, bp->rx_ring_dma);
1424 bp->rx_ring = NULL;
1425 }
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001426
1427 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1428 kfree(queue->tx_skb);
1429 queue->tx_skb = NULL;
1430 if (queue->tx_ring) {
1431 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1432 queue->tx_ring, queue->tx_ring_dma);
1433 queue->tx_ring = NULL;
1434 }
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001435 }
Nicolas Ferre4df95132013-06-04 21:57:12 +00001436}
1437
1438static int gem_alloc_rx_buffers(struct macb *bp)
1439{
1440 int size;
1441
1442 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1443 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1444 if (!bp->rx_skbuff)
1445 return -ENOMEM;
1446 else
1447 netdev_dbg(bp->dev,
1448 "Allocated %d RX struct sk_buff entries at %p\n",
1449 RX_RING_SIZE, bp->rx_skbuff);
1450 return 0;
1451}
1452
1453static int macb_alloc_rx_buffers(struct macb *bp)
1454{
1455 int size;
1456
1457 size = RX_RING_SIZE * bp->rx_buffer_size;
1458 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1459 &bp->rx_buffers_dma, GFP_KERNEL);
1460 if (!bp->rx_buffers)
1461 return -ENOMEM;
1462 else
1463 netdev_dbg(bp->dev,
1464 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1465 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1466 return 0;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001467}
1468
1469static int macb_alloc_consistent(struct macb *bp)
1470{
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001471 struct macb_queue *queue;
1472 unsigned int q;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001473 int size;
1474
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001475 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1476 size = TX_RING_BYTES;
1477 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1478 &queue->tx_ring_dma,
1479 GFP_KERNEL);
1480 if (!queue->tx_ring)
1481 goto out_err;
1482 netdev_dbg(bp->dev,
1483 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1484 q, size, (unsigned long)queue->tx_ring_dma,
1485 queue->tx_ring);
1486
1487 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1488 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1489 if (!queue->tx_skb)
1490 goto out_err;
1491 }
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001492
1493 size = RX_RING_BYTES;
1494 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1495 &bp->rx_ring_dma, GFP_KERNEL);
1496 if (!bp->rx_ring)
1497 goto out_err;
Jamie Ilesc220f8c2011-03-08 20:27:08 +00001498 netdev_dbg(bp->dev,
1499 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1500 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001501
Nicolas Ferre4df95132013-06-04 21:57:12 +00001502 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001503 goto out_err;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001504
1505 return 0;
1506
1507out_err:
1508 macb_free_consistent(bp);
1509 return -ENOMEM;
1510}
1511
Nicolas Ferre4df95132013-06-04 21:57:12 +00001512static void gem_init_rings(struct macb *bp)
1513{
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001514 struct macb_queue *queue;
1515 unsigned int q;
Nicolas Ferre4df95132013-06-04 21:57:12 +00001516 int i;
1517
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001518 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1519 for (i = 0; i < TX_RING_SIZE; i++) {
1520 queue->tx_ring[i].addr = 0;
1521 queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1522 }
1523 queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1524 queue->tx_head = 0;
1525 queue->tx_tail = 0;
Nicolas Ferre4df95132013-06-04 21:57:12 +00001526 }
Nicolas Ferre4df95132013-06-04 21:57:12 +00001527
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001528 bp->rx_tail = 0;
1529 bp->rx_prepared_head = 0;
Nicolas Ferre4df95132013-06-04 21:57:12 +00001530
1531 gem_rx_refill(bp);
1532}
1533
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001534static void macb_init_rings(struct macb *bp)
1535{
1536 int i;
1537 dma_addr_t addr;
1538
1539 addr = bp->rx_buffers_dma;
1540 for (i = 0; i < RX_RING_SIZE; i++) {
1541 bp->rx_ring[i].addr = addr;
1542 bp->rx_ring[i].ctrl = 0;
Nicolas Ferre1b447912013-06-04 21:57:11 +00001543 addr += bp->rx_buffer_size;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001544 }
1545 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1546
1547 for (i = 0; i < TX_RING_SIZE; i++) {
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001548 bp->queues[0].tx_ring[i].addr = 0;
1549 bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001550 }
Ben Shelton21d35152015-04-22 17:28:54 -05001551 bp->queues[0].tx_head = 0;
1552 bp->queues[0].tx_tail = 0;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001553 bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001554
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001555 bp->rx_tail = 0;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001556}
1557
1558static void macb_reset_hw(struct macb *bp)
1559{
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001560 struct macb_queue *queue;
1561 unsigned int q;
1562
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001563 /*
1564 * Disable RX and TX (XXX: Should we halt the transmission
1565 * more gracefully?)
1566 */
1567 macb_writel(bp, NCR, 0);
1568
1569 /* Clear the stats registers (XXX: Update stats first?) */
1570 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1571
1572 /* Clear all status flags */
Joachim Eastwood95ebcea2012-10-22 08:45:31 +00001573 macb_writel(bp, TSR, -1);
1574 macb_writel(bp, RSR, -1);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001575
1576 /* Disable all interrupts */
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001577 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1578 queue_writel(queue, IDR, -1);
1579 queue_readl(queue, ISR);
1580 }
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001581}
1582
Jamie Iles70c9f3d2011-03-09 16:22:54 +00001583static u32 gem_mdc_clk_div(struct macb *bp)
1584{
1585 u32 config;
1586 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1587
1588 if (pclk_hz <= 20000000)
1589 config = GEM_BF(CLK, GEM_CLK_DIV8);
1590 else if (pclk_hz <= 40000000)
1591 config = GEM_BF(CLK, GEM_CLK_DIV16);
1592 else if (pclk_hz <= 80000000)
1593 config = GEM_BF(CLK, GEM_CLK_DIV32);
1594 else if (pclk_hz <= 120000000)
1595 config = GEM_BF(CLK, GEM_CLK_DIV48);
1596 else if (pclk_hz <= 160000000)
1597 config = GEM_BF(CLK, GEM_CLK_DIV64);
1598 else
1599 config = GEM_BF(CLK, GEM_CLK_DIV96);
1600
1601 return config;
1602}
1603
1604static u32 macb_mdc_clk_div(struct macb *bp)
1605{
1606 u32 config;
1607 unsigned long pclk_hz;
1608
1609 if (macb_is_gem(bp))
1610 return gem_mdc_clk_div(bp);
1611
1612 pclk_hz = clk_get_rate(bp->pclk);
1613 if (pclk_hz <= 20000000)
1614 config = MACB_BF(CLK, MACB_CLK_DIV8);
1615 else if (pclk_hz <= 40000000)
1616 config = MACB_BF(CLK, MACB_CLK_DIV16);
1617 else if (pclk_hz <= 80000000)
1618 config = MACB_BF(CLK, MACB_CLK_DIV32);
1619 else
1620 config = MACB_BF(CLK, MACB_CLK_DIV64);
1621
1622 return config;
1623}
1624
Jamie Iles757a03c2011-03-09 16:29:59 +00001625/*
1626 * Get the DMA bus width field of the network configuration register that we
1627 * should program. We find the width from decoding the design configuration
1628 * register to find the maximum supported data bus width.
1629 */
1630static u32 macb_dbw(struct macb *bp)
1631{
1632 if (!macb_is_gem(bp))
1633 return 0;
1634
1635 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1636 case 4:
1637 return GEM_BF(DBW, GEM_DBW128);
1638 case 2:
1639 return GEM_BF(DBW, GEM_DBW64);
1640 case 1:
1641 default:
1642 return GEM_BF(DBW, GEM_DBW32);
1643 }
1644}
1645
Jamie Iles0116da42011-03-14 17:38:30 +00001646/*
Nicolas Ferreb3e3bd712012-11-23 03:49:01 +00001647 * Configure the receive DMA engine
1648 * - use the correct receive buffer size
Nicolas Ferree1755872014-07-24 13:50:58 +02001649 * - set best burst length for DMA operations
Nicolas Ferreb3e3bd712012-11-23 03:49:01 +00001650 * (if not supported by FIFO, it will fallback to default)
1651 * - set both rx/tx packet buffers to full memory size
1652 * These are configurable parameters for GEM.
Jamie Iles0116da42011-03-14 17:38:30 +00001653 */
1654static void macb_configure_dma(struct macb *bp)
1655{
1656 u32 dmacfg;
1657
1658 if (macb_is_gem(bp)) {
1659 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
Nicolas Ferre1b447912013-06-04 21:57:11 +00001660 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
Nicolas Ferree1755872014-07-24 13:50:58 +02001661 if (bp->dma_burst_length)
1662 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
Nicolas Ferreb3e3bd712012-11-23 03:49:01 +00001663 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
Arun Chandrana50dad32015-02-18 16:59:35 +05301664 dmacfg &= ~GEM_BIT(ENDIA_PKT);
Arun Chandran62f69242015-03-01 11:38:02 +05301665
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +03001666 if (bp->native_io)
Arun Chandran62f69242015-03-01 11:38:02 +05301667 dmacfg &= ~GEM_BIT(ENDIA_DESC);
1668 else
1669 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1670
Cyrille Pitchen85ff3d82014-07-24 13:51:00 +02001671 if (bp->dev->features & NETIF_F_HW_CSUM)
1672 dmacfg |= GEM_BIT(TXCOEN);
1673 else
1674 dmacfg &= ~GEM_BIT(TXCOEN);
Nicolas Ferree1755872014-07-24 13:50:58 +02001675 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1676 dmacfg);
Jamie Iles0116da42011-03-14 17:38:30 +00001677 gem_writel(bp, DMACFG, dmacfg);
1678 }
1679}
1680
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001681static void macb_init_hw(struct macb *bp)
1682{
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001683 struct macb_queue *queue;
1684 unsigned int q;
1685
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001686 u32 config;
1687
1688 macb_reset_hw(bp);
Joachim Eastwood314bccc2012-11-07 08:14:52 +00001689 macb_set_hwaddr(bp);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001690
Jamie Iles70c9f3d2011-03-09 16:22:54 +00001691 config = macb_mdc_clk_div(bp);
Havard Skinnemoen29bc2e12012-10-31 06:04:58 +00001692 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001693 config |= MACB_BIT(PAE); /* PAuse Enable */
1694 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
Dan Carpentera104a6b2015-05-12 21:15:24 +03001695 if (bp->caps & MACB_CAPS_JUMBO)
Harini Katakam98b5a0f42015-05-06 22:27:17 +05301696 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
1697 else
1698 config |= MACB_BIT(BIG); /* Receive oversized frames */
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001699 if (bp->dev->flags & IFF_PROMISC)
1700 config |= MACB_BIT(CAF); /* Copy All Frames */
Cyrille Pitchen924ec532014-07-24 13:51:01 +02001701 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1702 config |= GEM_BIT(RXCOEN);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001703 if (!(bp->dev->flags & IFF_BROADCAST))
1704 config |= MACB_BIT(NBC); /* No BroadCast */
Jamie Iles757a03c2011-03-09 16:29:59 +00001705 config |= macb_dbw(bp);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001706 macb_writel(bp, NCFGR, config);
Dan Carpentera104a6b2015-05-12 21:15:24 +03001707 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
Harini Katakam98b5a0f42015-05-06 22:27:17 +05301708 gem_writel(bp, JML, bp->jumbo_max_len);
Vitalii Demianets26cdfb42012-11-02 07:09:24 +00001709 bp->speed = SPEED_10;
1710 bp->duplex = DUPLEX_HALF;
Harini Katakam98b5a0f42015-05-06 22:27:17 +05301711 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
Dan Carpentera104a6b2015-05-12 21:15:24 +03001712 if (bp->caps & MACB_CAPS_JUMBO)
Harini Katakam98b5a0f42015-05-06 22:27:17 +05301713 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001714
Jamie Iles0116da42011-03-14 17:38:30 +00001715 macb_configure_dma(bp);
1716
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001717 /* Initialize TX and RX buffers */
1718 macb_writel(bp, RBQP, bp->rx_ring_dma);
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001719 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1720 queue_writel(queue, TBQP, queue->tx_ring_dma);
1721
1722 /* Enable interrupts */
1723 queue_writel(queue, IER,
1724 MACB_RX_INT_FLAGS |
1725 MACB_TX_INT_FLAGS |
1726 MACB_BIT(HRESP));
1727 }
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001728
1729 /* Enable TX and RX */
frederic RODO6c36a702007-07-12 19:07:24 +02001730 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001731}
1732
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001733/*
1734 * The hash address register is 64 bits long and takes up two
1735 * locations in the memory map. The least significant bits are stored
1736 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1737 *
1738 * The unicast hash enable and the multicast hash enable bits in the
1739 * network configuration register enable the reception of hash matched
1740 * frames. The destination address is reduced to a 6 bit index into
1741 * the 64 bit hash register using the following hash function. The
1742 * hash function is an exclusive or of every sixth bit of the
1743 * destination address.
1744 *
1745 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1746 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1747 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1748 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1749 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1750 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1751 *
1752 * da[0] represents the least significant bit of the first byte
1753 * received, that is, the multicast/unicast indicator, and da[47]
1754 * represents the most significant bit of the last byte received. If
1755 * the hash index, hi[n], points to a bit that is set in the hash
1756 * register then the frame will be matched according to whether the
1757 * frame is multicast or unicast. A multicast match will be signalled
1758 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1759 * index points to a bit set in the hash register. A unicast match
1760 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1761 * and the hash index points to a bit set in the hash register. To
1762 * receive all multicast frames, the hash register should be set with
1763 * all ones and the multicast hash enable bit should be set in the
1764 * network configuration register.
1765 */
1766
1767static inline int hash_bit_value(int bitnr, __u8 *addr)
1768{
1769 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1770 return 1;
1771 return 0;
1772}
1773
1774/*
1775 * Return the hash index value for the specified address.
1776 */
1777static int hash_get_index(__u8 *addr)
1778{
1779 int i, j, bitval;
1780 int hash_index = 0;
1781
1782 for (j = 0; j < 6; j++) {
1783 for (i = 0, bitval = 0; i < 8; i++)
Xander Huff2fa45e22015-01-15 15:55:19 -06001784 bitval ^= hash_bit_value(i * 6 + j, addr);
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001785
1786 hash_index |= (bitval << j);
1787 }
1788
1789 return hash_index;
1790}
1791
1792/*
1793 * Add multicast addresses to the internal multicast-hash table.
1794 */
1795static void macb_sethashtable(struct net_device *dev)
1796{
Jiri Pirko22bedad32010-04-01 21:22:57 +00001797 struct netdev_hw_addr *ha;
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001798 unsigned long mc_filter[2];
Jiri Pirkof9dcbcc2010-02-23 09:19:49 +00001799 unsigned int bitnr;
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001800 struct macb *bp = netdev_priv(dev);
1801
1802 mc_filter[0] = mc_filter[1] = 0;
1803
Jiri Pirko22bedad32010-04-01 21:22:57 +00001804 netdev_for_each_mc_addr(ha, dev) {
1805 bitnr = hash_get_index(ha->addr);
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001806 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1807 }
1808
Jamie Ilesf75ba502011-11-08 10:12:32 +00001809 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1810 macb_or_gem_writel(bp, HRT, mc_filter[1]);
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001811}
1812
1813/*
1814 * Enable/Disable promiscuous and multicast modes.
1815 */
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01001816static void macb_set_rx_mode(struct net_device *dev)
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001817{
1818 unsigned long cfg;
1819 struct macb *bp = netdev_priv(dev);
1820
1821 cfg = macb_readl(bp, NCFGR);
1822
Cyrille Pitchen924ec532014-07-24 13:51:01 +02001823 if (dev->flags & IFF_PROMISC) {
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001824 /* Enable promiscuous mode */
1825 cfg |= MACB_BIT(CAF);
Cyrille Pitchen924ec532014-07-24 13:51:01 +02001826
1827 /* Disable RX checksum offload */
1828 if (macb_is_gem(bp))
1829 cfg &= ~GEM_BIT(RXCOEN);
1830 } else {
1831 /* Disable promiscuous mode */
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001832 cfg &= ~MACB_BIT(CAF);
1833
Cyrille Pitchen924ec532014-07-24 13:51:01 +02001834 /* Enable RX checksum offload only if requested */
1835 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1836 cfg |= GEM_BIT(RXCOEN);
1837 }
1838
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001839 if (dev->flags & IFF_ALLMULTI) {
1840 /* Enable all multicast mode */
Jamie Ilesf75ba502011-11-08 10:12:32 +00001841 macb_or_gem_writel(bp, HRB, -1);
1842 macb_or_gem_writel(bp, HRT, -1);
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001843 cfg |= MACB_BIT(NCFGR_MTI);
Jiri Pirko4cd24ea2010-02-08 04:30:35 +00001844 } else if (!netdev_mc_empty(dev)) {
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001845 /* Enable specific multicasts */
1846 macb_sethashtable(dev);
1847 cfg |= MACB_BIT(NCFGR_MTI);
1848 } else if (dev->flags & (~IFF_ALLMULTI)) {
1849 /* Disable all multicast mode */
Jamie Ilesf75ba502011-11-08 10:12:32 +00001850 macb_or_gem_writel(bp, HRB, 0);
1851 macb_or_gem_writel(bp, HRT, 0);
Patrice Vilchez446ebd02007-07-12 19:07:25 +02001852 cfg &= ~MACB_BIT(NCFGR_MTI);
1853 }
1854
1855 macb_writel(bp, NCFGR, cfg);
1856}
1857
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001858static int macb_open(struct net_device *dev)
1859{
1860 struct macb *bp = netdev_priv(dev);
Nicolas Ferre4df95132013-06-04 21:57:12 +00001861 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001862 int err;
1863
Jamie Ilesc220f8c2011-03-08 20:27:08 +00001864 netdev_dbg(bp->dev, "open\n");
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001865
Nicolas Ferre03fc4722012-07-03 23:14:13 +00001866 /* carrier starts down */
1867 netif_carrier_off(dev);
1868
frederic RODO6c36a702007-07-12 19:07:24 +02001869 /* if the phy is not yet register, retry later*/
1870 if (!bp->phy_dev)
1871 return -EAGAIN;
1872
Nicolas Ferre1b447912013-06-04 21:57:11 +00001873 /* RX buffers initialization */
Nicolas Ferre4df95132013-06-04 21:57:12 +00001874 macb_init_rx_buffer_size(bp, bufsz);
Nicolas Ferre1b447912013-06-04 21:57:11 +00001875
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001876 err = macb_alloc_consistent(bp);
1877 if (err) {
Jamie Ilesc220f8c2011-03-08 20:27:08 +00001878 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1879 err);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001880 return err;
1881 }
1882
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001883 napi_enable(&bp->napi);
1884
Nicolas Ferre4df95132013-06-04 21:57:12 +00001885 bp->macbgem_ops.mog_init_rings(bp);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001886 macb_init_hw(bp);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001887
frederic RODO6c36a702007-07-12 19:07:24 +02001888 /* schedule a link state check */
1889 phy_start(bp->phy_dev);
1890
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001891 netif_tx_start_all_queues(dev);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001892
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001893 return 0;
1894}
1895
1896static int macb_close(struct net_device *dev)
1897{
1898 struct macb *bp = netdev_priv(dev);
1899 unsigned long flags;
1900
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01001901 netif_tx_stop_all_queues(dev);
Stephen Hemmingerbea33482007-10-03 16:41:36 -07001902 napi_disable(&bp->napi);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001903
frederic RODO6c36a702007-07-12 19:07:24 +02001904 if (bp->phy_dev)
1905 phy_stop(bp->phy_dev);
1906
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01001907 spin_lock_irqsave(&bp->lock, flags);
1908 macb_reset_hw(bp);
1909 netif_carrier_off(dev);
1910 spin_unlock_irqrestore(&bp->lock, flags);
1911
1912 macb_free_consistent(bp);
1913
1914 return 0;
1915}
1916
Harini Katakama5898ea2015-05-06 22:27:18 +05301917static int macb_change_mtu(struct net_device *dev, int new_mtu)
1918{
1919 struct macb *bp = netdev_priv(dev);
1920 u32 max_mtu;
1921
1922 if (netif_running(dev))
1923 return -EBUSY;
1924
1925 max_mtu = ETH_DATA_LEN;
Dan Carpentera104a6b2015-05-12 21:15:24 +03001926 if (bp->caps & MACB_CAPS_JUMBO)
Harini Katakama5898ea2015-05-06 22:27:18 +05301927 max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
1928
1929 if ((new_mtu > max_mtu) || (new_mtu < GEM_MTU_MIN_SIZE))
1930 return -EINVAL;
1931
1932 dev->mtu = new_mtu;
1933
1934 return 0;
1935}
1936
Jamie Ilesa494ed82011-03-09 16:26:35 +00001937static void gem_update_stats(struct macb *bp)
1938{
Xander Huff3ff13f12015-01-13 16:15:51 -06001939 int i;
Jamie Ilesa494ed82011-03-09 16:26:35 +00001940 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
Jamie Ilesa494ed82011-03-09 16:26:35 +00001941
Xander Huff3ff13f12015-01-13 16:15:51 -06001942 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
1943 u32 offset = gem_statistics[i].offset;
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +03001944 u64 val = bp->readl(bp, offset);
Xander Huff3ff13f12015-01-13 16:15:51 -06001945
1946 bp->ethtool_stats[i] += val;
1947 *p += val;
1948
1949 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
1950 /* Add GEM_OCTTXH, GEM_OCTRXH */
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +03001951 val = bp->readl(bp, offset + 4);
Xander Huff2fa45e22015-01-15 15:55:19 -06001952 bp->ethtool_stats[i] += ((u64)val) << 32;
Xander Huff3ff13f12015-01-13 16:15:51 -06001953 *(++p) += val;
1954 }
1955 }
Jamie Ilesa494ed82011-03-09 16:26:35 +00001956}
1957
1958static struct net_device_stats *gem_get_stats(struct macb *bp)
1959{
1960 struct gem_stats *hwstat = &bp->hw_stats.gem;
1961 struct net_device_stats *nstat = &bp->stats;
1962
1963 gem_update_stats(bp);
1964
1965 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1966 hwstat->rx_alignment_errors +
1967 hwstat->rx_resource_errors +
1968 hwstat->rx_overruns +
1969 hwstat->rx_oversize_frames +
1970 hwstat->rx_jabbers +
1971 hwstat->rx_undersized_frames +
1972 hwstat->rx_length_field_frame_errors);
1973 nstat->tx_errors = (hwstat->tx_late_collisions +
1974 hwstat->tx_excessive_collisions +
1975 hwstat->tx_underrun +
1976 hwstat->tx_carrier_sense_errors);
1977 nstat->multicast = hwstat->rx_multicast_frames;
1978 nstat->collisions = (hwstat->tx_single_collision_frames +
1979 hwstat->tx_multiple_collision_frames +
1980 hwstat->tx_excessive_collisions);
1981 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1982 hwstat->rx_jabbers +
1983 hwstat->rx_undersized_frames +
1984 hwstat->rx_length_field_frame_errors);
1985 nstat->rx_over_errors = hwstat->rx_resource_errors;
1986 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1987 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1988 nstat->rx_fifo_errors = hwstat->rx_overruns;
1989 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1990 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1991 nstat->tx_fifo_errors = hwstat->tx_underrun;
1992
1993 return nstat;
1994}
1995
Xander Huff3ff13f12015-01-13 16:15:51 -06001996static void gem_get_ethtool_stats(struct net_device *dev,
1997 struct ethtool_stats *stats, u64 *data)
1998{
1999 struct macb *bp;
2000
2001 bp = netdev_priv(dev);
2002 gem_update_stats(bp);
Xander Huff2fa45e22015-01-15 15:55:19 -06002003 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
Xander Huff3ff13f12015-01-13 16:15:51 -06002004}
2005
2006static int gem_get_sset_count(struct net_device *dev, int sset)
2007{
2008 switch (sset) {
2009 case ETH_SS_STATS:
2010 return GEM_STATS_LEN;
2011 default:
2012 return -EOPNOTSUPP;
2013 }
2014}
2015
2016static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2017{
2018 int i;
2019
2020 switch (sset) {
2021 case ETH_SS_STATS:
2022 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2023 memcpy(p, gem_statistics[i].stat_string,
2024 ETH_GSTRING_LEN);
2025 break;
2026 }
2027}
2028
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002029static struct net_device_stats *macb_get_stats(struct net_device *dev)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002030{
2031 struct macb *bp = netdev_priv(dev);
2032 struct net_device_stats *nstat = &bp->stats;
Jamie Ilesa494ed82011-03-09 16:26:35 +00002033 struct macb_stats *hwstat = &bp->hw_stats.macb;
2034
2035 if (macb_is_gem(bp))
2036 return gem_get_stats(bp);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002037
frederic RODO6c36a702007-07-12 19:07:24 +02002038 /* read stats from hardware */
2039 macb_update_stats(bp);
2040
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002041 /* Convert HW stats into netdevice stats */
2042 nstat->rx_errors = (hwstat->rx_fcs_errors +
2043 hwstat->rx_align_errors +
2044 hwstat->rx_resource_errors +
2045 hwstat->rx_overruns +
2046 hwstat->rx_oversize_pkts +
2047 hwstat->rx_jabbers +
2048 hwstat->rx_undersize_pkts +
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002049 hwstat->rx_length_mismatch);
2050 nstat->tx_errors = (hwstat->tx_late_cols +
2051 hwstat->tx_excessive_cols +
2052 hwstat->tx_underruns +
Wolfgang Steinwender716723c2015-04-10 11:42:56 +02002053 hwstat->tx_carrier_errors +
2054 hwstat->sqe_test_errors);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002055 nstat->collisions = (hwstat->tx_single_cols +
2056 hwstat->tx_multiple_cols +
2057 hwstat->tx_excessive_cols);
2058 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2059 hwstat->rx_jabbers +
2060 hwstat->rx_undersize_pkts +
2061 hwstat->rx_length_mismatch);
Alexander Steinb19f7f72011-04-13 05:03:24 +00002062 nstat->rx_over_errors = hwstat->rx_resource_errors +
2063 hwstat->rx_overruns;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002064 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2065 nstat->rx_frame_errors = hwstat->rx_align_errors;
2066 nstat->rx_fifo_errors = hwstat->rx_overruns;
2067 /* XXX: What does "missed" mean? */
2068 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2069 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2070 nstat->tx_fifo_errors = hwstat->tx_underruns;
2071 /* Don't know about heartbeat or window errors... */
2072
2073 return nstat;
2074}
2075
2076static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2077{
2078 struct macb *bp = netdev_priv(dev);
frederic RODO6c36a702007-07-12 19:07:24 +02002079 struct phy_device *phydev = bp->phy_dev;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002080
frederic RODO6c36a702007-07-12 19:07:24 +02002081 if (!phydev)
2082 return -ENODEV;
2083
2084 return phy_ethtool_gset(phydev, cmd);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002085}
2086
2087static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2088{
2089 struct macb *bp = netdev_priv(dev);
frederic RODO6c36a702007-07-12 19:07:24 +02002090 struct phy_device *phydev = bp->phy_dev;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002091
frederic RODO6c36a702007-07-12 19:07:24 +02002092 if (!phydev)
2093 return -ENODEV;
2094
2095 return phy_ethtool_sset(phydev, cmd);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002096}
2097
Nicolas Ferred1d1b532012-10-31 06:04:56 +00002098static int macb_get_regs_len(struct net_device *netdev)
2099{
2100 return MACB_GREGS_NBR * sizeof(u32);
2101}
2102
2103static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2104 void *p)
2105{
2106 struct macb *bp = netdev_priv(dev);
2107 unsigned int tail, head;
2108 u32 *regs_buff = p;
2109
2110 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2111 | MACB_GREGS_VERSION;
2112
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002113 tail = macb_tx_ring_wrap(bp->queues[0].tx_tail);
2114 head = macb_tx_ring_wrap(bp->queues[0].tx_head);
Nicolas Ferred1d1b532012-10-31 06:04:56 +00002115
2116 regs_buff[0] = macb_readl(bp, NCR);
2117 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2118 regs_buff[2] = macb_readl(bp, NSR);
2119 regs_buff[3] = macb_readl(bp, TSR);
2120 regs_buff[4] = macb_readl(bp, RBQP);
2121 regs_buff[5] = macb_readl(bp, TBQP);
2122 regs_buff[6] = macb_readl(bp, RSR);
2123 regs_buff[7] = macb_readl(bp, IMR);
2124
2125 regs_buff[8] = tail;
2126 regs_buff[9] = head;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002127 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2128 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
Nicolas Ferred1d1b532012-10-31 06:04:56 +00002129
Nicolas Ferre7c399942015-03-31 15:02:04 +02002130 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
Nicolas Ferred1d1b532012-10-31 06:04:56 +00002131 if (macb_is_gem(bp)) {
Nicolas Ferred1d1b532012-10-31 06:04:56 +00002132 regs_buff[13] = gem_readl(bp, DMACFG);
2133 }
2134}
2135
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002136static const struct ethtool_ops macb_ethtool_ops = {
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002137 .get_settings = macb_get_settings,
2138 .set_settings = macb_set_settings,
Nicolas Ferred1d1b532012-10-31 06:04:56 +00002139 .get_regs_len = macb_get_regs_len,
2140 .get_regs = macb_get_regs,
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002141 .get_link = ethtool_op_get_link,
Richard Cochran17f393e2012-04-03 22:59:31 +00002142 .get_ts_info = ethtool_op_get_ts_info,
Xander Huff8cd5a562015-01-15 15:55:20 -06002143};
Xander Huff8cd5a562015-01-15 15:55:20 -06002144
Lad, Prabhakar8093b1c2015-02-05 16:21:07 +00002145static const struct ethtool_ops gem_ethtool_ops = {
Xander Huff8cd5a562015-01-15 15:55:20 -06002146 .get_settings = macb_get_settings,
2147 .set_settings = macb_set_settings,
2148 .get_regs_len = macb_get_regs_len,
2149 .get_regs = macb_get_regs,
2150 .get_link = ethtool_op_get_link,
2151 .get_ts_info = ethtool_op_get_ts_info,
Xander Huff3ff13f12015-01-13 16:15:51 -06002152 .get_ethtool_stats = gem_get_ethtool_stats,
2153 .get_strings = gem_get_ethtool_strings,
2154 .get_sset_count = gem_get_sset_count,
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002155};
2156
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002157static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002158{
2159 struct macb *bp = netdev_priv(dev);
frederic RODO6c36a702007-07-12 19:07:24 +02002160 struct phy_device *phydev = bp->phy_dev;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002161
2162 if (!netif_running(dev))
2163 return -EINVAL;
2164
frederic RODO6c36a702007-07-12 19:07:24 +02002165 if (!phydev)
2166 return -ENODEV;
2167
Richard Cochran28b04112010-07-17 08:48:55 +00002168 return phy_mii_ioctl(phydev, rq, cmd);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002169}
2170
Cyrille Pitchen85ff3d82014-07-24 13:51:00 +02002171static int macb_set_features(struct net_device *netdev,
2172 netdev_features_t features)
2173{
2174 struct macb *bp = netdev_priv(netdev);
2175 netdev_features_t changed = features ^ netdev->features;
2176
2177 /* TX checksum offload */
2178 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2179 u32 dmacfg;
2180
2181 dmacfg = gem_readl(bp, DMACFG);
2182 if (features & NETIF_F_HW_CSUM)
2183 dmacfg |= GEM_BIT(TXCOEN);
2184 else
2185 dmacfg &= ~GEM_BIT(TXCOEN);
2186 gem_writel(bp, DMACFG, dmacfg);
2187 }
2188
Cyrille Pitchen924ec532014-07-24 13:51:01 +02002189 /* RX checksum offload */
2190 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2191 u32 netcfg;
2192
2193 netcfg = gem_readl(bp, NCFGR);
2194 if (features & NETIF_F_RXCSUM &&
2195 !(netdev->flags & IFF_PROMISC))
2196 netcfg |= GEM_BIT(RXCOEN);
2197 else
2198 netcfg &= ~GEM_BIT(RXCOEN);
2199 gem_writel(bp, NCFGR, netcfg);
2200 }
2201
Cyrille Pitchen85ff3d82014-07-24 13:51:00 +02002202 return 0;
2203}
2204
Alexander Beregalov5f1fa992009-04-11 07:42:26 +00002205static const struct net_device_ops macb_netdev_ops = {
2206 .ndo_open = macb_open,
2207 .ndo_stop = macb_close,
2208 .ndo_start_xmit = macb_start_xmit,
Jiri Pirkoafc4b132011-08-16 06:29:01 +00002209 .ndo_set_rx_mode = macb_set_rx_mode,
Alexander Beregalov5f1fa992009-04-11 07:42:26 +00002210 .ndo_get_stats = macb_get_stats,
2211 .ndo_do_ioctl = macb_ioctl,
2212 .ndo_validate_addr = eth_validate_addr,
Harini Katakama5898ea2015-05-06 22:27:18 +05302213 .ndo_change_mtu = macb_change_mtu,
Alexander Beregalov5f1fa992009-04-11 07:42:26 +00002214 .ndo_set_mac_address = eth_mac_addr,
Thomas Petazzoni6e8cf5c2009-05-04 11:08:41 -07002215#ifdef CONFIG_NET_POLL_CONTROLLER
2216 .ndo_poll_controller = macb_poll_controller,
2217#endif
Cyrille Pitchen85ff3d82014-07-24 13:51:00 +02002218 .ndo_set_features = macb_set_features,
Alexander Beregalov5f1fa992009-04-11 07:42:26 +00002219};
2220
Nicolas Ferree1755872014-07-24 13:50:58 +02002221/*
Nicolas Ferread783472015-03-31 15:02:02 +02002222 * Configure peripheral capabilities according to device tree
Nicolas Ferree1755872014-07-24 13:50:58 +02002223 * and integration options used
2224 */
Nicolas Ferref6970502015-03-31 15:02:01 +02002225static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_conf)
Nicolas Ferree1755872014-07-24 13:50:58 +02002226{
2227 u32 dcfg;
Nicolas Ferree1755872014-07-24 13:50:58 +02002228
Nicolas Ferref6970502015-03-31 15:02:01 +02002229 if (dt_conf)
2230 bp->caps = dt_conf->caps;
2231
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +03002232 if (hw_is_gem(bp->regs, bp->native_io)) {
Nicolas Ferree1755872014-07-24 13:50:58 +02002233 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2234
Nicolas Ferree1755872014-07-24 13:50:58 +02002235 dcfg = gem_readl(bp, DCFG1);
2236 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2237 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2238 dcfg = gem_readl(bp, DCFG2);
2239 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2240 bp->caps |= MACB_CAPS_FIFO_MODE;
2241 }
2242
Andy Shevchenkoa35919e2015-07-24 21:24:01 +03002243 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
Nicolas Ferree1755872014-07-24 13:50:58 +02002244}
2245
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002246static void macb_probe_queues(void __iomem *mem,
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +03002247 bool native_io,
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002248 unsigned int *queue_mask,
2249 unsigned int *num_queues)
2250{
2251 unsigned int hw_q;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002252
2253 *queue_mask = 0x1;
2254 *num_queues = 1;
2255
Nicolas Ferreda120112015-03-31 15:02:00 +02002256 /* is it macb or gem ?
2257 *
2258 * We need to read directly from the hardware here because
2259 * we are early in the probe process and don't have the
2260 * MACB_CAPS_MACB_IS_GEM flag positioned
2261 */
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +03002262 if (!hw_is_gem(mem, native_io))
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002263 return;
2264
2265 /* bit 0 is never set but queue 0 always exists */
Arun Chandrana50dad32015-02-18 16:59:35 +05302266 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2267
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002268 *queue_mask |= 0x1;
2269
2270 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2271 if (*queue_mask & (1 << hw_q))
2272 (*num_queues)++;
2273}
2274
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002275static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2276 struct clk **hclk, struct clk **tx_clk)
2277{
2278 int err;
2279
2280 *pclk = devm_clk_get(&pdev->dev, "pclk");
2281 if (IS_ERR(*pclk)) {
2282 err = PTR_ERR(*pclk);
2283 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
2284 return err;
2285 }
2286
2287 *hclk = devm_clk_get(&pdev->dev, "hclk");
2288 if (IS_ERR(*hclk)) {
2289 err = PTR_ERR(*hclk);
2290 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2291 return err;
2292 }
2293
2294 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2295 if (IS_ERR(*tx_clk))
2296 *tx_clk = NULL;
2297
2298 err = clk_prepare_enable(*pclk);
2299 if (err) {
2300 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2301 return err;
2302 }
2303
2304 err = clk_prepare_enable(*hclk);
2305 if (err) {
2306 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2307 goto err_disable_pclk;
2308 }
2309
2310 err = clk_prepare_enable(*tx_clk);
2311 if (err) {
2312 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2313 goto err_disable_hclk;
2314 }
2315
2316 return 0;
2317
2318err_disable_hclk:
2319 clk_disable_unprepare(*hclk);
2320
2321err_disable_pclk:
2322 clk_disable_unprepare(*pclk);
2323
2324 return err;
2325}
2326
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002327static int macb_init(struct platform_device *pdev)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002328{
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002329 struct net_device *dev = platform_get_drvdata(pdev);
Nicolas Ferrebfa09142015-03-31 15:01:59 +02002330 unsigned int hw_q, q;
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002331 struct macb *bp = netdev_priv(dev);
2332 struct macb_queue *queue;
2333 int err;
2334 u32 val;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002335
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002336 /* set the queue register mapping once for all: queue0 has a special
2337 * register mapping but we don't want to test the queue index then
2338 * compute the corresponding register offset at run time.
2339 */
Cyrille Pitchencf250de2014-12-15 15:13:32 +01002340 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
Nicolas Ferrebfa09142015-03-31 15:01:59 +02002341 if (!(bp->queue_mask & (1 << hw_q)))
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002342 continue;
Jamie Iles461845d2011-03-08 20:19:23 +00002343
Cyrille Pitchencf250de2014-12-15 15:13:32 +01002344 queue = &bp->queues[q];
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002345 queue->bp = bp;
2346 if (hw_q) {
2347 queue->ISR = GEM_ISR(hw_q - 1);
2348 queue->IER = GEM_IER(hw_q - 1);
2349 queue->IDR = GEM_IDR(hw_q - 1);
2350 queue->IMR = GEM_IMR(hw_q - 1);
2351 queue->TBQP = GEM_TBQP(hw_q - 1);
2352 } else {
2353 /* queue0 uses legacy registers */
2354 queue->ISR = MACB_ISR;
2355 queue->IER = MACB_IER;
2356 queue->IDR = MACB_IDR;
2357 queue->IMR = MACB_IMR;
2358 queue->TBQP = MACB_TBQP;
Soren Brinkmanne1824df2013-12-10 16:07:23 -08002359 }
Soren Brinkmanne1824df2013-12-10 16:07:23 -08002360
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002361 /* get irq: here we use the linux queue index, not the hardware
2362 * queue index. the queue irq definitions in the device tree
2363 * must remove the optional gaps that could exist in the
2364 * hardware queue mask.
2365 */
Cyrille Pitchencf250de2014-12-15 15:13:32 +01002366 queue->irq = platform_get_irq(pdev, q);
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002367 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
Punnaiah Choudary Kalluri20488232015-03-06 18:29:12 +01002368 IRQF_SHARED, dev->name, queue);
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002369 if (err) {
2370 dev_err(&pdev->dev,
2371 "Unable to request IRQ %d (error %d)\n",
2372 queue->irq, err);
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002373 return err;
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002374 }
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002375
Cyrille Pitchen02c958d2014-12-12 13:26:44 +01002376 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
Cyrille Pitchencf250de2014-12-15 15:13:32 +01002377 q++;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002378 }
2379
Alexander Beregalov5f1fa992009-04-11 07:42:26 +00002380 dev->netdev_ops = &macb_netdev_ops;
Stephen Hemmingerbea33482007-10-03 16:41:36 -07002381 netif_napi_add(dev, &bp->napi, macb_poll, 64);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002382
Nicolas Ferre4df95132013-06-04 21:57:12 +00002383 /* setup appropriated routines according to adapter type */
2384 if (macb_is_gem(bp)) {
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02002385 bp->max_tx_length = GEM_MAX_TX_LEN;
Nicolas Ferre4df95132013-06-04 21:57:12 +00002386 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2387 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2388 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2389 bp->macbgem_ops.mog_rx = gem_rx;
Xander Huff8cd5a562015-01-15 15:55:20 -06002390 dev->ethtool_ops = &gem_ethtool_ops;
Nicolas Ferre4df95132013-06-04 21:57:12 +00002391 } else {
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02002392 bp->max_tx_length = MACB_MAX_TX_LEN;
Nicolas Ferre4df95132013-06-04 21:57:12 +00002393 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2394 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2395 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2396 bp->macbgem_ops.mog_rx = macb_rx;
Xander Huff8cd5a562015-01-15 15:55:20 -06002397 dev->ethtool_ops = &macb_ethtool_ops;
Nicolas Ferre4df95132013-06-04 21:57:12 +00002398 }
2399
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02002400 /* Set features */
2401 dev->hw_features = NETIF_F_SG;
Cyrille Pitchen85ff3d82014-07-24 13:51:00 +02002402 /* Checksum offload is only available on gem with packet buffer */
2403 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
Cyrille Pitchen924ec532014-07-24 13:51:01 +02002404 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
Cyrille Pitchena4c35ed32014-07-24 13:50:59 +02002405 if (bp->caps & MACB_CAPS_SG_DISABLED)
2406 dev->hw_features &= ~NETIF_F_SG;
2407 dev->features = dev->hw_features;
2408
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002409 val = 0;
2410 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2411 val = GEM_BIT(RGMII);
2412 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2413 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2414 val = MACB_BIT(RMII);
2415 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2416 val = MACB_BIT(MII);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002417
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002418 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2419 val |= MACB_BIT(CLKEN);
2420
2421 macb_or_gem_writel(bp, USRIO, val);
2422
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002423 /* Set MII management clock divider */
2424 val = macb_mdc_clk_div(bp);
2425 val |= macb_dbw(bp);
2426 macb_writel(bp, NCFGR, val);
2427
2428 return 0;
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002429}
2430
2431#if defined(CONFIG_OF)
2432/* 1518 rounded up */
2433#define AT91ETHER_MAX_RBUFF_SZ 0x600
2434/* max number of receive buffers */
2435#define AT91ETHER_MAX_RX_DESCR 9
2436
2437/* Initialize and start the Receiver and Transmit subsystems */
2438static int at91ether_start(struct net_device *dev)
2439{
2440 struct macb *lp = netdev_priv(dev);
2441 dma_addr_t addr;
2442 u32 ctl;
2443 int i;
2444
2445 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2446 (AT91ETHER_MAX_RX_DESCR *
2447 sizeof(struct macb_dma_desc)),
2448 &lp->rx_ring_dma, GFP_KERNEL);
2449 if (!lp->rx_ring)
2450 return -ENOMEM;
2451
2452 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2453 AT91ETHER_MAX_RX_DESCR *
2454 AT91ETHER_MAX_RBUFF_SZ,
2455 &lp->rx_buffers_dma, GFP_KERNEL);
2456 if (!lp->rx_buffers) {
2457 dma_free_coherent(&lp->pdev->dev,
2458 AT91ETHER_MAX_RX_DESCR *
2459 sizeof(struct macb_dma_desc),
2460 lp->rx_ring, lp->rx_ring_dma);
2461 lp->rx_ring = NULL;
2462 return -ENOMEM;
2463 }
2464
2465 addr = lp->rx_buffers_dma;
2466 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
2467 lp->rx_ring[i].addr = addr;
2468 lp->rx_ring[i].ctrl = 0;
2469 addr += AT91ETHER_MAX_RBUFF_SZ;
2470 }
2471
2472 /* Set the Wrap bit on the last descriptor */
2473 lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
2474
2475 /* Reset buffer index */
2476 lp->rx_tail = 0;
2477
2478 /* Program address of descriptor list in Rx Buffer Queue register */
2479 macb_writel(lp, RBQP, lp->rx_ring_dma);
2480
2481 /* Enable Receive and Transmit */
2482 ctl = macb_readl(lp, NCR);
2483 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
2484
2485 return 0;
2486}
2487
2488/* Open the ethernet interface */
2489static int at91ether_open(struct net_device *dev)
2490{
2491 struct macb *lp = netdev_priv(dev);
2492 u32 ctl;
2493 int ret;
2494
2495 /* Clear internal statistics */
2496 ctl = macb_readl(lp, NCR);
2497 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
2498
2499 macb_set_hwaddr(lp);
2500
2501 ret = at91ether_start(dev);
2502 if (ret)
2503 return ret;
2504
2505 /* Enable MAC interrupts */
2506 macb_writel(lp, IER, MACB_BIT(RCOMP) |
2507 MACB_BIT(RXUBR) |
2508 MACB_BIT(ISR_TUND) |
2509 MACB_BIT(ISR_RLE) |
2510 MACB_BIT(TCOMP) |
2511 MACB_BIT(ISR_ROVR) |
2512 MACB_BIT(HRESP));
2513
2514 /* schedule a link state check */
2515 phy_start(lp->phy_dev);
2516
2517 netif_start_queue(dev);
2518
2519 return 0;
2520}
2521
2522/* Close the interface */
2523static int at91ether_close(struct net_device *dev)
2524{
2525 struct macb *lp = netdev_priv(dev);
2526 u32 ctl;
2527
2528 /* Disable Receiver and Transmitter */
2529 ctl = macb_readl(lp, NCR);
2530 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
2531
2532 /* Disable MAC interrupts */
2533 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
2534 MACB_BIT(RXUBR) |
2535 MACB_BIT(ISR_TUND) |
2536 MACB_BIT(ISR_RLE) |
2537 MACB_BIT(TCOMP) |
2538 MACB_BIT(ISR_ROVR) |
2539 MACB_BIT(HRESP));
2540
2541 netif_stop_queue(dev);
2542
2543 dma_free_coherent(&lp->pdev->dev,
2544 AT91ETHER_MAX_RX_DESCR *
2545 sizeof(struct macb_dma_desc),
2546 lp->rx_ring, lp->rx_ring_dma);
2547 lp->rx_ring = NULL;
2548
2549 dma_free_coherent(&lp->pdev->dev,
2550 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
2551 lp->rx_buffers, lp->rx_buffers_dma);
2552 lp->rx_buffers = NULL;
2553
2554 return 0;
2555}
2556
2557/* Transmit packet */
2558static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
2559{
2560 struct macb *lp = netdev_priv(dev);
2561
2562 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
2563 netif_stop_queue(dev);
2564
2565 /* Store packet information (to free when Tx completed) */
2566 lp->skb = skb;
2567 lp->skb_length = skb->len;
2568 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
2569 DMA_TO_DEVICE);
2570
2571 /* Set address of the data in the Transmit Address register */
2572 macb_writel(lp, TAR, lp->skb_physaddr);
2573 /* Set length of the packet in the Transmit Control register */
2574 macb_writel(lp, TCR, skb->len);
2575
2576 } else {
2577 netdev_err(dev, "%s called, but device is busy!\n", __func__);
2578 return NETDEV_TX_BUSY;
2579 }
2580
2581 return NETDEV_TX_OK;
2582}
2583
2584/* Extract received frame from buffer descriptors and sent to upper layers.
2585 * (Called from interrupt context)
2586 */
2587static void at91ether_rx(struct net_device *dev)
2588{
2589 struct macb *lp = netdev_priv(dev);
2590 unsigned char *p_recv;
2591 struct sk_buff *skb;
2592 unsigned int pktlen;
2593
2594 while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
2595 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
2596 pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
2597 skb = netdev_alloc_skb(dev, pktlen + 2);
2598 if (skb) {
2599 skb_reserve(skb, 2);
2600 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
2601
2602 skb->protocol = eth_type_trans(skb, dev);
2603 lp->stats.rx_packets++;
2604 lp->stats.rx_bytes += pktlen;
2605 netif_rx(skb);
2606 } else {
2607 lp->stats.rx_dropped++;
2608 }
2609
2610 if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
2611 lp->stats.multicast++;
2612
2613 /* reset ownership bit */
2614 lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
2615
2616 /* wrap after last buffer */
2617 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
2618 lp->rx_tail = 0;
2619 else
2620 lp->rx_tail++;
2621 }
2622}
2623
2624/* MAC interrupt handler */
2625static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
2626{
2627 struct net_device *dev = dev_id;
2628 struct macb *lp = netdev_priv(dev);
2629 u32 intstatus, ctl;
2630
2631 /* MAC Interrupt Status register indicates what interrupts are pending.
2632 * It is automatically cleared once read.
2633 */
2634 intstatus = macb_readl(lp, ISR);
2635
2636 /* Receive complete */
2637 if (intstatus & MACB_BIT(RCOMP))
2638 at91ether_rx(dev);
2639
2640 /* Transmit complete */
2641 if (intstatus & MACB_BIT(TCOMP)) {
2642 /* The TCOM bit is set even if the transmission failed */
2643 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
2644 lp->stats.tx_errors++;
2645
2646 if (lp->skb) {
2647 dev_kfree_skb_irq(lp->skb);
2648 lp->skb = NULL;
2649 dma_unmap_single(NULL, lp->skb_physaddr,
2650 lp->skb_length, DMA_TO_DEVICE);
2651 lp->stats.tx_packets++;
2652 lp->stats.tx_bytes += lp->skb_length;
2653 }
2654 netif_wake_queue(dev);
2655 }
2656
2657 /* Work-around for EMAC Errata section 41.3.1 */
2658 if (intstatus & MACB_BIT(RXUBR)) {
2659 ctl = macb_readl(lp, NCR);
2660 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
2661 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
2662 }
2663
2664 if (intstatus & MACB_BIT(ISR_ROVR))
2665 netdev_err(dev, "ROVR error\n");
2666
2667 return IRQ_HANDLED;
2668}
2669
2670#ifdef CONFIG_NET_POLL_CONTROLLER
2671static void at91ether_poll_controller(struct net_device *dev)
2672{
2673 unsigned long flags;
2674
2675 local_irq_save(flags);
2676 at91ether_interrupt(dev->irq, dev);
2677 local_irq_restore(flags);
2678}
2679#endif
2680
2681static const struct net_device_ops at91ether_netdev_ops = {
2682 .ndo_open = at91ether_open,
2683 .ndo_stop = at91ether_close,
2684 .ndo_start_xmit = at91ether_start_xmit,
2685 .ndo_get_stats = macb_get_stats,
2686 .ndo_set_rx_mode = macb_set_rx_mode,
2687 .ndo_set_mac_address = eth_mac_addr,
2688 .ndo_do_ioctl = macb_ioctl,
2689 .ndo_validate_addr = eth_validate_addr,
2690 .ndo_change_mtu = eth_change_mtu,
2691#ifdef CONFIG_NET_POLL_CONTROLLER
2692 .ndo_poll_controller = at91ether_poll_controller,
2693#endif
2694};
2695
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002696static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
2697 struct clk **hclk, struct clk **tx_clk)
2698{
2699 int err;
2700
2701 *hclk = NULL;
2702 *tx_clk = NULL;
2703
2704 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
2705 if (IS_ERR(*pclk))
2706 return PTR_ERR(*pclk);
2707
2708 err = clk_prepare_enable(*pclk);
2709 if (err) {
2710 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2711 return err;
2712 }
2713
2714 return 0;
2715}
2716
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002717static int at91ether_init(struct platform_device *pdev)
2718{
2719 struct net_device *dev = platform_get_drvdata(pdev);
2720 struct macb *bp = netdev_priv(dev);
2721 int err;
2722 u32 reg;
2723
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002724 dev->netdev_ops = &at91ether_netdev_ops;
2725 dev->ethtool_ops = &macb_ethtool_ops;
2726
2727 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
2728 0, dev->name, dev);
2729 if (err)
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002730 return err;
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002731
2732 macb_writel(bp, NCR, 0);
2733
2734 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
2735 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
2736 reg |= MACB_BIT(RM9200_RMII);
2737
2738 macb_writel(bp, NCFGR, reg);
2739
2740 return 0;
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002741}
2742
David S. Miller3cef5c52015-03-09 23:38:02 -04002743static const struct macb_config at91sam9260_config = {
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002744 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII,
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002745 .clk_init = macb_clk_init,
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002746 .init = macb_init,
2747};
2748
David S. Miller3cef5c52015-03-09 23:38:02 -04002749static const struct macb_config pc302gem_config = {
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002750 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2751 .dma_burst_length = 16,
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002752 .clk_init = macb_clk_init,
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002753 .init = macb_init,
2754};
2755
Cyrille Pitchen5c8fe712015-06-18 16:27:23 +02002756static const struct macb_config sama5d2_config = {
2757 .caps = 0,
2758 .dma_burst_length = 16,
2759 .clk_init = macb_clk_init,
2760 .init = macb_init,
2761};
2762
David S. Miller3cef5c52015-03-09 23:38:02 -04002763static const struct macb_config sama5d3_config = {
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002764 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2765 .dma_burst_length = 16,
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002766 .clk_init = macb_clk_init,
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002767 .init = macb_init,
2768};
2769
David S. Miller3cef5c52015-03-09 23:38:02 -04002770static const struct macb_config sama5d4_config = {
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002771 .caps = 0,
2772 .dma_burst_length = 4,
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002773 .clk_init = macb_clk_init,
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002774 .init = macb_init,
2775};
2776
David S. Miller3cef5c52015-03-09 23:38:02 -04002777static const struct macb_config emac_config = {
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002778 .clk_init = at91ether_clk_init,
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002779 .init = at91ether_init,
2780};
2781
David S. Miller36583eb2015-05-23 01:22:35 -04002782
Harini Katakam7b61f9c2015-05-06 22:27:16 +05302783static const struct macb_config zynqmp_config = {
Harini Katakam98b5a0f42015-05-06 22:27:17 +05302784 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
2785 MACB_CAPS_JUMBO,
Harini Katakam7b61f9c2015-05-06 22:27:16 +05302786 .dma_burst_length = 16,
2787 .clk_init = macb_clk_init,
2788 .init = macb_init,
Harini Katakam98b5a0f42015-05-06 22:27:17 +05302789 .jumbo_max_len = 10240,
Harini Katakam7b61f9c2015-05-06 22:27:16 +05302790};
2791
Nathan Sullivan222ca8e2015-05-22 09:22:10 -05002792static const struct macb_config zynq_config = {
2793 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
2794 MACB_CAPS_NO_GIGABIT_HALF,
2795 .dma_burst_length = 16,
2796 .clk_init = macb_clk_init,
2797 .init = macb_init,
2798};
2799
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002800static const struct of_device_id macb_dt_ids[] = {
2801 { .compatible = "cdns,at32ap7000-macb" },
2802 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
2803 { .compatible = "cdns,macb" },
2804 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2805 { .compatible = "cdns,gem", .data = &pc302gem_config },
Cyrille Pitchen5c8fe712015-06-18 16:27:23 +02002806 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002807 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
2808 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
2809 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
2810 { .compatible = "cdns,emac", .data = &emac_config },
Harini Katakam7b61f9c2015-05-06 22:27:16 +05302811 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
Nathan Sullivan222ca8e2015-05-22 09:22:10 -05002812 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002813 { /* sentinel */ }
2814};
2815MODULE_DEVICE_TABLE(of, macb_dt_ids);
2816#endif /* CONFIG_OF */
2817
2818static int macb_probe(struct platform_device *pdev)
2819{
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002820 int (*clk_init)(struct platform_device *, struct clk **,
2821 struct clk **, struct clk **)
2822 = macb_clk_init;
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002823 int (*init)(struct platform_device *) = macb_init;
2824 struct device_node *np = pdev->dev.of_node;
2825 const struct macb_config *macb_config = NULL;
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002826 struct clk *pclk, *hclk, *tx_clk;
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002827 unsigned int queue_mask, num_queues;
2828 struct macb_platform_data *pdata;
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +03002829 bool native_io;
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002830 struct phy_device *phydev;
2831 struct net_device *dev;
2832 struct resource *regs;
2833 void __iomem *mem;
2834 const char *mac;
2835 struct macb *bp;
2836 int err;
2837
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +03002838 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2839 mem = devm_ioremap_resource(&pdev->dev, regs);
2840 if (IS_ERR(mem))
2841 return PTR_ERR(mem);
2842
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002843 if (np) {
2844 const struct of_device_id *match;
2845
2846 match = of_match_node(macb_dt_ids, np);
2847 if (match && match->data) {
2848 macb_config = match->data;
2849 clk_init = macb_config->clk_init;
2850 init = macb_config->init;
2851 }
2852 }
2853
2854 err = clk_init(pdev, &pclk, &hclk, &tx_clk);
2855 if (err)
2856 return err;
2857
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +03002858 native_io = hw_is_native_io(mem);
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002859
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +03002860 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002861 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002862 if (!dev) {
2863 err = -ENOMEM;
2864 goto err_disable_clocks;
2865 }
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002866
2867 dev->base_addr = regs->start;
2868
2869 SET_NETDEV_DEV(dev, &pdev->dev);
2870
2871 bp = netdev_priv(dev);
2872 bp->pdev = pdev;
2873 bp->dev = dev;
2874 bp->regs = mem;
Andy Shevchenkof2ce8a92015-07-24 21:23:59 +03002875 bp->native_io = native_io;
2876 if (native_io) {
2877 bp->readl = hw_readl_native;
2878 bp->writel = hw_writel_native;
2879 } else {
2880 bp->readl = hw_readl;
2881 bp->writel = hw_writel;
2882 }
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002883 bp->num_queues = num_queues;
Nicolas Ferrebfa09142015-03-31 15:01:59 +02002884 bp->queue_mask = queue_mask;
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002885 if (macb_config)
2886 bp->dma_burst_length = macb_config->dma_burst_length;
2887 bp->pclk = pclk;
2888 bp->hclk = hclk;
2889 bp->tx_clk = tx_clk;
Andy Shevchenkof36dbe62015-07-24 21:24:00 +03002890 if (macb_config)
Harini Katakam98b5a0f42015-05-06 22:27:17 +05302891 bp->jumbo_max_len = macb_config->jumbo_max_len;
Harini Katakam98b5a0f42015-05-06 22:27:17 +05302892
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002893 spin_lock_init(&bp->lock);
2894
Nicolas Ferread783472015-03-31 15:02:02 +02002895 /* setup capabilities */
Nicolas Ferref6970502015-03-31 15:02:01 +02002896 macb_configure_caps(bp, macb_config);
2897
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002898 platform_set_drvdata(pdev, dev);
2899
2900 dev->irq = platform_get_irq(pdev, 0);
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002901 if (dev->irq < 0) {
2902 err = dev->irq;
2903 goto err_disable_clocks;
2904 }
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002905
2906 mac = of_get_mac_address(np);
Guenter Roeck50907042013-04-02 09:35:09 +00002907 if (mac)
2908 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
2909 else
Jean-Christophe PLAGNIOL-VILLARDfb97a842011-11-18 15:29:25 +01002910 macb_get_hwaddr(bp);
frederic RODO6c36a702007-07-12 19:07:24 +02002911
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002912 err = of_get_phy_mode(np);
Jean-Christophe PLAGNIOL-VILLARDfb97a842011-11-18 15:29:25 +01002913 if (err < 0) {
Jingoo Hanc607a0d2013-08-30 14:12:21 +09002914 pdata = dev_get_platdata(&pdev->dev);
Jean-Christophe PLAGNIOL-VILLARDfb97a842011-11-18 15:29:25 +01002915 if (pdata && pdata->is_rmii)
2916 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
2917 else
2918 bp->phy_interface = PHY_INTERFACE_MODE_MII;
2919 } else {
2920 bp->phy_interface = err;
2921 }
2922
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002923 /* IP specific init */
2924 err = init(pdev);
2925 if (err)
2926 goto err_out_free_netdev;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002927
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002928 err = register_netdev(dev);
2929 if (err) {
2930 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002931 goto err_out_unregister_netdev;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002932 }
2933
Nicolas Ferre72ca8202013-04-14 22:04:33 +00002934 err = macb_mii_init(bp);
2935 if (err)
frederic RODO6c36a702007-07-12 19:07:24 +02002936 goto err_out_unregister_netdev;
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002937
Nicolas Ferre03fc4722012-07-03 23:14:13 +00002938 netif_carrier_off(dev);
2939
Bo Shen58798232014-09-13 01:57:49 +02002940 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
2941 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
2942 dev->base_addr, dev->irq, dev->dev_addr);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002943
frederic RODO6c36a702007-07-12 19:07:24 +02002944 phydev = bp->phy_dev;
Jamie Ilesc220f8c2011-03-08 20:27:08 +00002945 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2946 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
frederic RODO6c36a702007-07-12 19:07:24 +02002947
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002948 return 0;
2949
frederic RODO6c36a702007-07-12 19:07:24 +02002950err_out_unregister_netdev:
2951 unregister_netdev(dev);
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002952
Cyrille Pitchencf250de2014-12-15 15:13:32 +01002953err_out_free_netdev:
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002954 free_netdev(dev);
Cyrille Pitchen421d9df2015-03-07 07:23:32 +01002955
Nicolas Ferrec69618b2015-03-31 15:02:03 +02002956err_disable_clocks:
2957 clk_disable_unprepare(tx_clk);
2958 clk_disable_unprepare(hclk);
2959 clk_disable_unprepare(pclk);
2960
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002961 return err;
2962}
2963
Nicolae Rosia9e86d762015-01-22 17:31:05 +00002964static int macb_remove(struct platform_device *pdev)
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002965{
2966 struct net_device *dev;
2967 struct macb *bp;
2968
2969 dev = platform_get_drvdata(pdev);
2970
2971 if (dev) {
2972 bp = netdev_priv(dev);
Atsushi Nemoto84b79012008-04-10 23:30:07 +09002973 if (bp->phy_dev)
2974 phy_disconnect(bp->phy_dev);
Lennert Buytenhek298cf9b2008-10-08 16:29:57 -07002975 mdiobus_unregister(bp->mii_bus);
2976 kfree(bp->mii_bus->irq);
2977 mdiobus_free(bp->mii_bus);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002978 unregister_netdev(dev);
Cyrille Pitchen93b31f42015-03-07 07:23:31 +01002979 clk_disable_unprepare(bp->tx_clk);
Steffen Trumtrarace58012013-03-27 23:07:07 +00002980 clk_disable_unprepare(bp->hclk);
Steffen Trumtrarace58012013-03-27 23:07:07 +00002981 clk_disable_unprepare(bp->pclk);
Cyrille Pitchene965be72014-12-15 15:13:31 +01002982 free_netdev(dev);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01002983 }
2984
2985 return 0;
2986}
2987
Michal Simekd23823d2015-01-23 09:36:03 +01002988static int __maybe_unused macb_suspend(struct device *dev)
Haavard Skinnemoenc1f598f2008-03-04 13:39:29 +01002989{
Soren Brinkmann0dfc3e12013-12-10 16:07:19 -08002990 struct platform_device *pdev = to_platform_device(dev);
Haavard Skinnemoenc1f598f2008-03-04 13:39:29 +01002991 struct net_device *netdev = platform_get_drvdata(pdev);
2992 struct macb *bp = netdev_priv(netdev);
2993
Nicolas Ferre03fc4722012-07-03 23:14:13 +00002994 netif_carrier_off(netdev);
Haavard Skinnemoenc1f598f2008-03-04 13:39:29 +01002995 netif_device_detach(netdev);
2996
Cyrille Pitchen93b31f42015-03-07 07:23:31 +01002997 clk_disable_unprepare(bp->tx_clk);
Steffen Trumtrarace58012013-03-27 23:07:07 +00002998 clk_disable_unprepare(bp->hclk);
2999 clk_disable_unprepare(bp->pclk);
Haavard Skinnemoenc1f598f2008-03-04 13:39:29 +01003000
3001 return 0;
3002}
3003
Michal Simekd23823d2015-01-23 09:36:03 +01003004static int __maybe_unused macb_resume(struct device *dev)
Haavard Skinnemoenc1f598f2008-03-04 13:39:29 +01003005{
Soren Brinkmann0dfc3e12013-12-10 16:07:19 -08003006 struct platform_device *pdev = to_platform_device(dev);
Haavard Skinnemoenc1f598f2008-03-04 13:39:29 +01003007 struct net_device *netdev = platform_get_drvdata(pdev);
3008 struct macb *bp = netdev_priv(netdev);
3009
Steffen Trumtrarace58012013-03-27 23:07:07 +00003010 clk_prepare_enable(bp->pclk);
3011 clk_prepare_enable(bp->hclk);
Cyrille Pitchen93b31f42015-03-07 07:23:31 +01003012 clk_prepare_enable(bp->tx_clk);
Haavard Skinnemoenc1f598f2008-03-04 13:39:29 +01003013
3014 netif_device_attach(netdev);
3015
3016 return 0;
3017}
Haavard Skinnemoenc1f598f2008-03-04 13:39:29 +01003018
Soren Brinkmann0dfc3e12013-12-10 16:07:19 -08003019static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
3020
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01003021static struct platform_driver macb_driver = {
Nicolae Rosia9e86d762015-01-22 17:31:05 +00003022 .probe = macb_probe,
3023 .remove = macb_remove,
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01003024 .driver = {
3025 .name = "macb",
Jean-Christophe PLAGNIOL-VILLARDfb97a842011-11-18 15:29:25 +01003026 .of_match_table = of_match_ptr(macb_dt_ids),
Soren Brinkmann0dfc3e12013-12-10 16:07:19 -08003027 .pm = &macb_pm_ops,
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01003028 },
3029};
3030
Nicolae Rosia9e86d762015-01-22 17:31:05 +00003031module_platform_driver(macb_driver);
Haavard Skinnemoen89e57852006-11-09 14:51:17 +01003032
3033MODULE_LICENSE("GPL");
Jamie Ilesf75ba502011-11-08 10:12:32 +00003034MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
Jean Delvaree05503e2011-05-18 16:49:24 +02003035MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
Kay Sievers72abb462008-04-18 13:50:44 -07003036MODULE_ALIAS("platform:macb");