ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Rockchip eFuse Driver |
| 3 | * |
| 4 | * Copyright (c) 2015 Rockchip Electronics Co. Ltd. |
| 5 | * Author: Caesar Wang <wxt@rock-chips.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of version 2 of the GNU General Public License as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | */ |
| 16 | |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 17 | #include <linux/clk.h> |
| 18 | #include <linux/delay.h> |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 19 | #include <linux/device.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <linux/module.h> |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 22 | #include <linux/nvmem-provider.h> |
| 23 | #include <linux/slab.h> |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 24 | #include <linux/of.h> |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 25 | #include <linux/platform_device.h> |
| 26 | #include <linux/regmap.h> |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 27 | |
| 28 | #define EFUSE_A_SHIFT 6 |
| 29 | #define EFUSE_A_MASK 0x3ff |
| 30 | #define EFUSE_PGENB BIT(3) |
| 31 | #define EFUSE_LOAD BIT(2) |
| 32 | #define EFUSE_STROBE BIT(1) |
| 33 | #define EFUSE_CSB BIT(0) |
| 34 | |
| 35 | #define REG_EFUSE_CTRL 0x0000 |
| 36 | #define REG_EFUSE_DOUT 0x0004 |
| 37 | |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 38 | struct rockchip_efuse_chip { |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 39 | struct device *dev; |
| 40 | void __iomem *base; |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 41 | struct clk *clk; |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 42 | }; |
| 43 | |
| 44 | static int rockchip_efuse_write(void *context, const void *data, size_t count) |
| 45 | { |
| 46 | /* Nothing TBD, Read-Only */ |
| 47 | return 0; |
| 48 | } |
| 49 | |
| 50 | static int rockchip_efuse_read(void *context, |
| 51 | const void *reg, size_t reg_size, |
| 52 | void *val, size_t val_size) |
| 53 | { |
| 54 | unsigned int offset = *(u32 *)reg; |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 55 | struct rockchip_efuse_chip *efuse = context; |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 56 | u8 *buf = val; |
| 57 | int ret; |
| 58 | |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 59 | ret = clk_prepare_enable(efuse->clk); |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 60 | if (ret < 0) { |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 61 | dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 62 | return ret; |
| 63 | } |
| 64 | |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 65 | writel(EFUSE_LOAD | EFUSE_PGENB, efuse->base + REG_EFUSE_CTRL); |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 66 | udelay(1); |
| 67 | while (val_size) { |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 68 | writel(readl(efuse->base + REG_EFUSE_CTRL) & |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 69 | (~(EFUSE_A_MASK << EFUSE_A_SHIFT)), |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 70 | efuse->base + REG_EFUSE_CTRL); |
| 71 | writel(readl(efuse->base + REG_EFUSE_CTRL) | |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 72 | ((offset & EFUSE_A_MASK) << EFUSE_A_SHIFT), |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 73 | efuse->base + REG_EFUSE_CTRL); |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 74 | udelay(1); |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 75 | writel(readl(efuse->base + REG_EFUSE_CTRL) | |
| 76 | EFUSE_STROBE, efuse->base + REG_EFUSE_CTRL); |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 77 | udelay(1); |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 78 | *buf++ = readb(efuse->base + REG_EFUSE_DOUT); |
| 79 | writel(readl(efuse->base + REG_EFUSE_CTRL) & |
| 80 | (~EFUSE_STROBE), efuse->base + REG_EFUSE_CTRL); |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 81 | udelay(1); |
| 82 | |
| 83 | val_size -= 1; |
| 84 | offset += 1; |
| 85 | } |
| 86 | |
| 87 | /* Switch to standby mode */ |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 88 | writel(EFUSE_PGENB | EFUSE_CSB, efuse->base + REG_EFUSE_CTRL); |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 89 | |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 90 | clk_disable_unprepare(efuse->clk); |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 91 | |
| 92 | return 0; |
| 93 | } |
| 94 | |
| 95 | static struct regmap_bus rockchip_efuse_bus = { |
| 96 | .read = rockchip_efuse_read, |
| 97 | .write = rockchip_efuse_write, |
| 98 | .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, |
| 99 | .val_format_endian_default = REGMAP_ENDIAN_NATIVE, |
| 100 | }; |
| 101 | |
kbuild test robot | 7e532f7 | 2015-09-30 21:46:06 +0800 | [diff] [blame] | 102 | static struct regmap_config rockchip_efuse_regmap_config = { |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 103 | .reg_bits = 32, |
| 104 | .reg_stride = 1, |
| 105 | .val_bits = 8, |
| 106 | }; |
| 107 | |
| 108 | static struct nvmem_config econfig = { |
| 109 | .name = "rockchip-efuse", |
| 110 | .owner = THIS_MODULE, |
| 111 | .read_only = true, |
| 112 | }; |
| 113 | |
| 114 | static const struct of_device_id rockchip_efuse_match[] = { |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 115 | { .compatible = "rockchip,rockchip-efuse", }, |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 116 | { /* sentinel */}, |
| 117 | }; |
| 118 | MODULE_DEVICE_TABLE(of, rockchip_efuse_match); |
| 119 | |
kbuild test robot | 7e532f7 | 2015-09-30 21:46:06 +0800 | [diff] [blame] | 120 | static int rockchip_efuse_probe(struct platform_device *pdev) |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 121 | { |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 122 | struct resource *res; |
| 123 | struct nvmem_device *nvmem; |
| 124 | struct regmap *regmap; |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 125 | struct rockchip_efuse_chip *efuse; |
| 126 | |
| 127 | efuse = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_efuse_chip), |
| 128 | GFP_KERNEL); |
| 129 | if (!efuse) |
| 130 | return -ENOMEM; |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 131 | |
| 132 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 133 | efuse->base = devm_ioremap_resource(&pdev->dev, res); |
| 134 | if (IS_ERR(efuse->base)) |
| 135 | return PTR_ERR(efuse->base); |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 136 | |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 137 | efuse->clk = devm_clk_get(&pdev->dev, "pclk_efuse"); |
| 138 | if (IS_ERR(efuse->clk)) |
| 139 | return PTR_ERR(efuse->clk); |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 140 | |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 141 | efuse->dev = &pdev->dev; |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 142 | |
| 143 | rockchip_efuse_regmap_config.max_register = resource_size(res) - 1; |
| 144 | |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 145 | regmap = devm_regmap_init(efuse->dev, &rockchip_efuse_bus, |
| 146 | efuse, &rockchip_efuse_regmap_config); |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 147 | if (IS_ERR(regmap)) { |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 148 | dev_err(efuse->dev, "regmap init failed\n"); |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 149 | return PTR_ERR(regmap); |
| 150 | } |
Caesar Wang | c37ff3f | 2015-12-14 09:43:39 +0000 | [diff] [blame] | 151 | |
| 152 | econfig.dev = efuse->dev; |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 153 | nvmem = nvmem_register(&econfig); |
| 154 | if (IS_ERR(nvmem)) |
| 155 | return PTR_ERR(nvmem); |
| 156 | |
| 157 | platform_set_drvdata(pdev, nvmem); |
| 158 | |
| 159 | return 0; |
| 160 | } |
| 161 | |
kbuild test robot | 7e532f7 | 2015-09-30 21:46:06 +0800 | [diff] [blame] | 162 | static int rockchip_efuse_remove(struct platform_device *pdev) |
ZhengShunQian | 03a6956 | 2015-09-30 13:56:44 +0100 | [diff] [blame] | 163 | { |
| 164 | struct nvmem_device *nvmem = platform_get_drvdata(pdev); |
| 165 | |
| 166 | return nvmem_unregister(nvmem); |
| 167 | } |
| 168 | |
| 169 | static struct platform_driver rockchip_efuse_driver = { |
| 170 | .probe = rockchip_efuse_probe, |
| 171 | .remove = rockchip_efuse_remove, |
| 172 | .driver = { |
| 173 | .name = "rockchip-efuse", |
| 174 | .of_match_table = rockchip_efuse_match, |
| 175 | }, |
| 176 | }; |
| 177 | |
| 178 | module_platform_driver(rockchip_efuse_driver); |
| 179 | MODULE_DESCRIPTION("rockchip_efuse driver"); |
| 180 | MODULE_LICENSE("GPL v2"); |