blob: 978ae4b25e82267ad448b68ed50c0c369c75dc11 [file] [log] [blame]
Alan Coxf910b412011-11-03 18:21:42 +00001/*
2 * Copyright (c) 2006 Intel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16 *
17 * Authors:
18 * Eric Anholt <eric@anholt.net>
19 *
20 */
21
Patrik Jakobsson9e8e4632013-03-14 12:36:54 +010022#ifndef _INTEL_BIOS_H_
23#define _INTEL_BIOS_H_
Alan Coxf910b412011-11-03 18:21:42 +000024
25#include <drm/drmP.h>
Zhao Yakuid112a812012-08-08 13:55:55 +000026#include <drm/drm_dp_helper.h>
Alan Coxf910b412011-11-03 18:21:42 +000027
28struct vbt_header {
29 u8 signature[20]; /**< Always starts with 'VBT$' */
30 u16 version; /**< decimal */
31 u16 header_size; /**< in bytes */
32 u16 vbt_size; /**< in bytes */
33 u8 vbt_checksum;
34 u8 reserved0;
35 u32 bdb_offset; /**< from beginning of VBT */
36 u32 aim_offset[4]; /**< from beginning of VBT */
37} __attribute__((packed));
38
39
40struct bdb_header {
41 u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
42 u16 version; /**< decimal */
43 u16 header_size; /**< in bytes */
44 u16 bdb_size; /**< in bytes */
45};
46
47/* strictly speaking, this is a "skip" block, but it has interesting info */
48struct vbios_data {
49 u8 type; /* 0 == desktop, 1 == mobile */
50 u8 relstage;
51 u8 chipset;
52 u8 lvds_present:1;
53 u8 tv_present:1;
54 u8 rsvd2:6; /* finish byte */
55 u8 rsvd3[4];
56 u8 signon[155];
57 u8 copyright[61];
58 u16 code_segment;
59 u8 dos_boot_mode;
60 u8 bandwidth_percent;
61 u8 rsvd4; /* popup memory size */
62 u8 resize_pci_bios;
63 u8 rsvd5; /* is crt already on ddc2 */
64} __attribute__((packed));
65
66/*
67 * There are several types of BIOS data blocks (BDBs), each block has
68 * an ID and size in the first 3 bytes (ID in first, size in next 2).
69 * Known types are listed below.
70 */
71#define BDB_GENERAL_FEATURES 1
72#define BDB_GENERAL_DEFINITIONS 2
73#define BDB_OLD_TOGGLE_LIST 3
74#define BDB_MODE_SUPPORT_LIST 4
75#define BDB_GENERIC_MODE_TABLE 5
76#define BDB_EXT_MMIO_REGS 6
77#define BDB_SWF_IO 7
78#define BDB_SWF_MMIO 8
79#define BDB_DOT_CLOCK_TABLE 9
80#define BDB_MODE_REMOVAL_TABLE 10
81#define BDB_CHILD_DEVICE_TABLE 11
82#define BDB_DRIVER_FEATURES 12
83#define BDB_DRIVER_PERSISTENCE 13
84#define BDB_EXT_TABLE_PTRS 14
85#define BDB_DOT_CLOCK_OVERRIDE 15
86#define BDB_DISPLAY_SELECT 16
87/* 17 rsvd */
88#define BDB_DRIVER_ROTATION 18
89#define BDB_DISPLAY_REMOVE 19
90#define BDB_OEM_CUSTOM 20
91#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */
92#define BDB_SDVO_LVDS_OPTIONS 22
93#define BDB_SDVO_PANEL_DTDS 23
94#define BDB_SDVO_LVDS_PNP_IDS 24
95#define BDB_SDVO_LVDS_POWER_SEQ 25
96#define BDB_TV_OPTIONS 26
Zhao Yakuid112a812012-08-08 13:55:55 +000097#define BDB_EDP 27
Alan Coxf910b412011-11-03 18:21:42 +000098#define BDB_LVDS_OPTIONS 40
99#define BDB_LVDS_LFP_DATA_PTRS 41
100#define BDB_LVDS_LFP_DATA 42
101#define BDB_LVDS_BACKLIGHT 43
102#define BDB_LVDS_POWER 44
103#define BDB_SKIP 254 /* VBIOS private block, ignore */
104
105struct bdb_general_features {
106 /* bits 1 */
107 u8 panel_fitting:2;
108 u8 flexaim:1;
109 u8 msg_enable:1;
110 u8 clear_screen:3;
111 u8 color_flip:1;
112
113 /* bits 2 */
114 u8 download_ext_vbt:1;
115 u8 enable_ssc:1;
116 u8 ssc_freq:1;
117 u8 enable_lfp_on_override:1;
118 u8 disable_ssc_ddt:1;
119 u8 rsvd8:3; /* finish byte */
120
121 /* bits 3 */
122 u8 disable_smooth_vision:1;
123 u8 single_dvi:1;
124 u8 rsvd9:6; /* finish byte */
125
126 /* bits 4 */
127 u8 legacy_monitor_detect;
128
129 /* bits 5 */
130 u8 int_crt_support:1;
131 u8 int_tv_support:1;
Alan Cox1fb28e92012-04-25 14:37:14 +0100132 u8 int_efp_support:1;
133 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */
134 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
135 u8 rsvd11:3; /* finish byte */
Alan Coxf910b412011-11-03 18:21:42 +0000136} __attribute__((packed));
137
Alan Cox1fb28e92012-04-25 14:37:14 +0100138/* pre-915 */
139#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */
140#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */
141#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */
142#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
143
144/* Pre 915 */
145#define DEVICE_TYPE_NONE 0x00
146#define DEVICE_TYPE_CRT 0x01
147#define DEVICE_TYPE_TV 0x09
148#define DEVICE_TYPE_EFP 0x12
149#define DEVICE_TYPE_LFP 0x22
150/* On 915+ */
151#define DEVICE_TYPE_CRT_DPMS 0x6001
152#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001
153#define DEVICE_TYPE_TV_COMPOSITE 0x0209
154#define DEVICE_TYPE_TV_MACROVISION 0x0289
155#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c
156#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609
157#define DEVICE_TYPE_TV_SCART 0x0209
158#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009
159#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012
160#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052
161#define DEVICE_TYPE_EFP_DVI_I 0x6053
162#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152
163#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2
164#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062
165#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162
166#define DEVICE_TYPE_LFP_PANELLINK 0x5012
167#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042
168#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062
169#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162
170#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2
171
172#define DEVICE_CFG_NONE 0x00
173#define DEVICE_CFG_12BIT_DVOB 0x01
174#define DEVICE_CFG_12BIT_DVOC 0x02
175#define DEVICE_CFG_24BIT_DVOBC 0x09
176#define DEVICE_CFG_24BIT_DVOCB 0x0a
177#define DEVICE_CFG_DUAL_DVOB 0x11
178#define DEVICE_CFG_DUAL_DVOC 0x12
179#define DEVICE_CFG_DUAL_DVOBC 0x13
180#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19
181#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a
182
183#define DEVICE_WIRE_NONE 0x00
184#define DEVICE_WIRE_DVOB 0x01
185#define DEVICE_WIRE_DVOC 0x02
186#define DEVICE_WIRE_DVOBC 0x03
187#define DEVICE_WIRE_DVOBB 0x05
188#define DEVICE_WIRE_DVOCC 0x06
189#define DEVICE_WIRE_DVOB_MASTER 0x0d
190#define DEVICE_WIRE_DVOC_MASTER 0x0e
191
192#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */
193#define DEVICE_PORT_DVOB 0x01
194#define DEVICE_PORT_DVOC 0x02
195
196struct child_device_config {
197 u16 handle;
198 u16 device_type;
199 u8 device_id[10]; /* ascii string */
200 u16 addin_offset;
201 u8 dvo_port; /* See Device_PORT_* above */
202 u8 i2c_pin;
203 u8 slave_addr;
204 u8 ddc_pin;
205 u16 edid_ptr;
206 u8 dvo_cfg; /* See DEVICE_CFG_* above */
207 u8 dvo2_port;
208 u8 i2c2_pin;
209 u8 slave2_addr;
210 u8 ddc2_pin;
211 u8 capabilities;
212 u8 dvo_wiring;/* See DEVICE_WIRE_* above */
213 u8 dvo2_wiring;
214 u16 extended_type;
215 u8 dvo_function;
216} __attribute__((packed));
217
218
Alan Coxf910b412011-11-03 18:21:42 +0000219struct bdb_general_definitions {
220 /* DDC GPIO */
221 u8 crt_ddc_gmbus_pin;
222
223 /* DPMS bits */
224 u8 dpms_acpi:1;
225 u8 skip_boot_crt_detect:1;
226 u8 dpms_aim:1;
227 u8 rsvd1:5; /* finish byte */
228
229 /* boot device bits */
230 u8 boot_display[2];
231 u8 child_dev_size;
232
Alan Cox1fb28e92012-04-25 14:37:14 +0100233 /*
234 * Device info:
235 * If TV is present, it'll be at devices[0].
236 * LVDS will be next, either devices[0] or [1], if present.
237 * On some platforms the number of device is 6. But could be as few as
238 * 4 if both TV and LVDS are missing.
239 * And the device num is related with the size of general definition
240 * block. It is obtained by using the following formula:
241 * number = (block_size - sizeof(bdb_general_definitions))/
242 * sizeof(child_device_config);
243 */
244 struct child_device_config devices[0];
Alan Coxf910b412011-11-03 18:21:42 +0000245};
246
247struct bdb_lvds_options {
248 u8 panel_type;
249 u8 rsvd1;
250 /* LVDS capabilities, stored in a dword */
251 u8 pfit_mode:2;
252 u8 pfit_text_mode_enhanced:1;
253 u8 pfit_gfx_mode_enhanced:1;
254 u8 pfit_ratio_auto:1;
255 u8 pixel_dither:1;
256 u8 lvds_edid:1;
257 u8 rsvd2:1;
258 u8 rsvd4;
259} __attribute__((packed));
260
261struct bdb_lvds_backlight {
262 u8 type:2;
263 u8 pol:1;
264 u8 gpio:3;
265 u8 gmbus:2;
266 u16 freq;
267 u8 minbrightness;
268 u8 i2caddr;
269 u8 brightnesscmd;
270 /*FIXME: more...*/
271} __attribute__((packed));
272
273/* LFP pointer table contains entries to the struct below */
274struct bdb_lvds_lfp_data_ptr {
275 u16 fp_timing_offset; /* offsets are from start of bdb */
276 u8 fp_table_size;
277 u16 dvo_timing_offset;
278 u8 dvo_table_size;
279 u16 panel_pnp_id_offset;
280 u8 pnp_table_size;
281} __attribute__((packed));
282
283struct bdb_lvds_lfp_data_ptrs {
284 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
285 struct bdb_lvds_lfp_data_ptr ptr[16];
286} __attribute__((packed));
287
288/* LFP data has 3 blocks per entry */
289struct lvds_fp_timing {
290 u16 x_res;
291 u16 y_res;
292 u32 lvds_reg;
293 u32 lvds_reg_val;
294 u32 pp_on_reg;
295 u32 pp_on_reg_val;
296 u32 pp_off_reg;
297 u32 pp_off_reg_val;
298 u32 pp_cycle_reg;
299 u32 pp_cycle_reg_val;
300 u32 pfit_reg;
301 u32 pfit_reg_val;
302 u16 terminator;
303} __attribute__((packed));
304
305struct lvds_dvo_timing {
306 u16 clock; /**< In 10khz */
307 u8 hactive_lo;
308 u8 hblank_lo;
309 u8 hblank_hi:4;
310 u8 hactive_hi:4;
311 u8 vactive_lo;
312 u8 vblank_lo;
313 u8 vblank_hi:4;
314 u8 vactive_hi:4;
315 u8 hsync_off_lo;
316 u8 hsync_pulse_width;
317 u8 vsync_pulse_width:4;
318 u8 vsync_off:4;
319 u8 rsvd0:6;
320 u8 hsync_off_hi:2;
321 u8 h_image;
322 u8 v_image;
323 u8 max_hv;
324 u8 h_border;
325 u8 v_border;
326 u8 rsvd1:3;
327 u8 digital:2;
328 u8 vsync_positive:1;
329 u8 hsync_positive:1;
330 u8 rsvd2:1;
331} __attribute__((packed));
332
333struct lvds_pnp_id {
334 u16 mfg_name;
335 u16 product_code;
336 u32 serial;
337 u8 mfg_week;
338 u8 mfg_year;
339} __attribute__((packed));
340
341struct bdb_lvds_lfp_data_entry {
342 struct lvds_fp_timing fp_timing;
343 struct lvds_dvo_timing dvo_timing;
344 struct lvds_pnp_id pnp_id;
345} __attribute__((packed));
346
347struct bdb_lvds_lfp_data {
348 struct bdb_lvds_lfp_data_entry data[16];
349} __attribute__((packed));
350
351struct aimdb_header {
352 char signature[16];
353 char oem_device[20];
354 u16 aimdb_version;
355 u16 aimdb_header_size;
356 u16 aimdb_size;
357} __attribute__((packed));
358
359struct aimdb_block {
360 u8 aimdb_id;
361 u16 aimdb_size;
362} __attribute__((packed));
363
364struct vch_panel_data {
365 u16 fp_timing_offset;
366 u8 fp_timing_size;
367 u16 dvo_timing_offset;
368 u8 dvo_timing_size;
369 u16 text_fitting_offset;
370 u8 text_fitting_size;
371 u16 graphics_fitting_offset;
372 u8 graphics_fitting_size;
373} __attribute__((packed));
374
375struct vch_bdb_22 {
376 struct aimdb_block aimdb_block;
377 struct vch_panel_data panels[16];
378} __attribute__((packed));
379
380struct bdb_sdvo_lvds_options {
381 u8 panel_backlight;
382 u8 h40_set_panel_type;
383 u8 panel_type;
384 u8 ssc_clk_freq;
385 u16 als_low_trip;
386 u16 als_high_trip;
387 u8 sclalarcoeff_tab_row_num;
388 u8 sclalarcoeff_tab_row_size;
389 u8 coefficient[8];
390 u8 panel_misc_bits_1;
391 u8 panel_misc_bits_2;
392 u8 panel_misc_bits_3;
393 u8 panel_misc_bits_4;
394} __attribute__((packed));
395
Zhao Yakuid112a812012-08-08 13:55:55 +0000396#define BDB_DRIVER_FEATURE_NO_LVDS 0
397#define BDB_DRIVER_FEATURE_INT_LVDS 1
398#define BDB_DRIVER_FEATURE_SDVO_LVDS 2
399#define BDB_DRIVER_FEATURE_EDP 3
400
Alan Cox642c52f2012-04-25 14:36:34 +0100401struct bdb_driver_features {
402 u8 boot_dev_algorithm:1;
403 u8 block_display_switch:1;
404 u8 allow_display_switch:1;
405 u8 hotplug_dvo:1;
406 u8 dual_view_zoom:1;
407 u8 int15h_hook:1;
408 u8 sprite_in_clone:1;
409 u8 primary_lfp_id:1;
410
411 u16 boot_mode_x;
412 u16 boot_mode_y;
413 u8 boot_mode_bpp;
414 u8 boot_mode_refresh;
415
416 u16 enable_lfp_primary:1;
417 u16 selective_mode_pruning:1;
418 u16 dual_frequency:1;
419 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */
420 u16 nt_clone_support:1;
421 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */
422 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */
423 u16 cui_aspect_scaling:1;
424 u16 preserve_aspect_ratio:1;
425 u16 sdvo_device_power_down:1;
426 u16 crt_hotplug:1;
427 u16 lvds_config:2;
428 u16 tv_hotplug:1;
429 u16 hdmi_config:2;
430
431 u8 static_display:1;
432 u8 reserved2:7;
433 u16 legacy_crt_max_x;
434 u16 legacy_crt_max_y;
435 u8 legacy_crt_max_refresh;
436
437 u8 hdmi_termination;
438 u8 custom_vbt_version;
439} __attribute__((packed));
Alan Coxf910b412011-11-03 18:21:42 +0000440
Zhao Yakuid112a812012-08-08 13:55:55 +0000441#define EDP_18BPP 0
442#define EDP_24BPP 1
443#define EDP_30BPP 2
444#define EDP_RATE_1_62 0
445#define EDP_RATE_2_7 1
446#define EDP_LANE_1 0
447#define EDP_LANE_2 1
448#define EDP_LANE_4 3
449#define EDP_PREEMPHASIS_NONE 0
450#define EDP_PREEMPHASIS_3_5dB 1
451#define EDP_PREEMPHASIS_6dB 2
452#define EDP_PREEMPHASIS_9_5dB 3
453#define EDP_VSWING_0_4V 0
454#define EDP_VSWING_0_6V 1
455#define EDP_VSWING_0_8V 2
456#define EDP_VSWING_1_2V 3
457
458struct edp_power_seq {
459 u16 t1_t3;
460 u16 t8;
461 u16 t9;
462 u16 t10;
463 u16 t11_t12;
464} __attribute__ ((packed));
465
466struct edp_link_params {
467 u8 rate:4;
468 u8 lanes:4;
469 u8 preemphasis:4;
470 u8 vswing:4;
471} __attribute__ ((packed));
472
473struct bdb_edp {
474 struct edp_power_seq power_seqs[16];
475 u32 color_depth;
476 u32 sdrrs_msa_timing_delay;
477 struct edp_link_params link_params[16];
478} __attribute__ ((packed));
479
Dan Carpenter0317c6c2012-06-27 12:10:30 +0300480extern int psb_intel_init_bios(struct drm_device *dev);
Alan Coxf910b412011-11-03 18:21:42 +0000481extern void psb_intel_destroy_bios(struct drm_device *dev);
482
483/*
484 * Driver<->VBIOS interaction occurs through scratch bits in
485 * GR18 & SWF*.
486 */
487
488/* GR18 bits are set on display switch and hotkey events */
489#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */
490#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */
491#define GR18_HK_NONE (0x0<<3)
492#define GR18_HK_LFP_STRETCH (0x1<<3)
493#define GR18_HK_TOGGLE_DISP (0x2<<3)
494#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */
495#define GR18_HK_POPUP_DISABLED (0x6<<3)
496#define GR18_HK_POPUP_ENABLED (0x7<<3)
497#define GR18_HK_PFIT (0x8<<3)
498#define GR18_HK_APM_CHANGE (0xa<<3)
499#define GR18_HK_MULTIPLE (0xc<<3)
500#define GR18_USER_INT_EN (1<<2)
501#define GR18_A0000_FLUSH_EN (1<<1)
502#define GR18_SMM_EN (1<<0)
503
504/* Set by driver, cleared by VBIOS */
505#define SWF00_YRES_SHIFT 16
506#define SWF00_XRES_SHIFT 0
507#define SWF00_RES_MASK 0xffff
508
509/* Set by VBIOS at boot time and driver at runtime */
510#define SWF01_TV2_FORMAT_SHIFT 8
511#define SWF01_TV1_FORMAT_SHIFT 0
512#define SWF01_TV_FORMAT_MASK 0xffff
513
514#define SWF10_VBIOS_BLC_I2C_EN (1<<29)
515#define SWF10_GTT_OVERRIDE_EN (1<<28)
516#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */
517#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24)
518#define SWF10_OLD_TOGGLE 0x0
519#define SWF10_TOGGLE_LIST_1 0x1
520#define SWF10_TOGGLE_LIST_2 0x2
521#define SWF10_TOGGLE_LIST_3 0x3
522#define SWF10_TOGGLE_LIST_4 0x4
523#define SWF10_PANNING_EN (1<<23)
524#define SWF10_DRIVER_LOADED (1<<22)
525#define SWF10_EXTENDED_DESKTOP (1<<21)
526#define SWF10_EXCLUSIVE_MODE (1<<20)
527#define SWF10_OVERLAY_EN (1<<19)
528#define SWF10_PLANEB_HOLDOFF (1<<18)
529#define SWF10_PLANEA_HOLDOFF (1<<17)
530#define SWF10_VGA_HOLDOFF (1<<16)
531#define SWF10_ACTIVE_DISP_MASK 0xffff
532#define SWF10_PIPEB_LFP2 (1<<15)
533#define SWF10_PIPEB_EFP2 (1<<14)
534#define SWF10_PIPEB_TV2 (1<<13)
535#define SWF10_PIPEB_CRT2 (1<<12)
536#define SWF10_PIPEB_LFP (1<<11)
537#define SWF10_PIPEB_EFP (1<<10)
538#define SWF10_PIPEB_TV (1<<9)
539#define SWF10_PIPEB_CRT (1<<8)
540#define SWF10_PIPEA_LFP2 (1<<7)
541#define SWF10_PIPEA_EFP2 (1<<6)
542#define SWF10_PIPEA_TV2 (1<<5)
543#define SWF10_PIPEA_CRT2 (1<<4)
544#define SWF10_PIPEA_LFP (1<<3)
545#define SWF10_PIPEA_EFP (1<<2)
546#define SWF10_PIPEA_TV (1<<1)
547#define SWF10_PIPEA_CRT (1<<0)
548
549#define SWF11_MEMORY_SIZE_SHIFT 16
550#define SWF11_SV_TEST_EN (1<<15)
551#define SWF11_IS_AGP (1<<14)
552#define SWF11_DISPLAY_HOLDOFF (1<<13)
553#define SWF11_DPMS_REDUCED (1<<12)
554#define SWF11_IS_VBE_MODE (1<<11)
555#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */
556#define SWF11_DPMS_MASK 0x07
557#define SWF11_DPMS_OFF (1<<2)
558#define SWF11_DPMS_SUSPEND (1<<1)
559#define SWF11_DPMS_STANDBY (1<<0)
560#define SWF11_DPMS_ON 0
561
562#define SWF14_GFX_PFIT_EN (1<<31)
563#define SWF14_TEXT_PFIT_EN (1<<30)
564#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
565#define SWF14_POPUP_EN (1<<28)
566#define SWF14_DISPLAY_HOLDOFF (1<<27)
567#define SWF14_DISP_DETECT_EN (1<<26)
568#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */
569#define SWF14_DRIVER_STATUS (1<<24)
570#define SWF14_OS_TYPE_WIN9X (1<<23)
571#define SWF14_OS_TYPE_WINNT (1<<22)
572/* 21:19 rsvd */
573#define SWF14_PM_TYPE_MASK 0x00070000
574#define SWF14_PM_ACPI_VIDEO (0x4 << 16)
575#define SWF14_PM_ACPI (0x3 << 16)
576#define SWF14_PM_APM_12 (0x2 << 16)
577#define SWF14_PM_APM_11 (0x1 << 16)
578#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */
579 /* if GR18 indicates a display switch */
580#define SWF14_DS_PIPEB_LFP2_EN (1<<15)
581#define SWF14_DS_PIPEB_EFP2_EN (1<<14)
582#define SWF14_DS_PIPEB_TV2_EN (1<<13)
583#define SWF14_DS_PIPEB_CRT2_EN (1<<12)
584#define SWF14_DS_PIPEB_LFP_EN (1<<11)
585#define SWF14_DS_PIPEB_EFP_EN (1<<10)
586#define SWF14_DS_PIPEB_TV_EN (1<<9)
587#define SWF14_DS_PIPEB_CRT_EN (1<<8)
588#define SWF14_DS_PIPEA_LFP2_EN (1<<7)
589#define SWF14_DS_PIPEA_EFP2_EN (1<<6)
590#define SWF14_DS_PIPEA_TV2_EN (1<<5)
591#define SWF14_DS_PIPEA_CRT2_EN (1<<4)
592#define SWF14_DS_PIPEA_LFP_EN (1<<3)
593#define SWF14_DS_PIPEA_EFP_EN (1<<2)
594#define SWF14_DS_PIPEA_TV_EN (1<<1)
595#define SWF14_DS_PIPEA_CRT_EN (1<<0)
596 /* if GR18 indicates a panel fitting request */
597#define SWF14_PFIT_EN (1<<0) /* 0 means disable */
598 /* if GR18 indicates an APM change request */
599#define SWF14_APM_HIBERNATE 0x4
600#define SWF14_APM_SUSPEND 0x3
601#define SWF14_APM_STANDBY 0x1
602#define SWF14_APM_RESTORE 0x0
603
Alan Cox1fb28e92012-04-25 14:37:14 +0100604/* Add the device class for LFP, TV, HDMI */
605#define DEVICE_TYPE_INT_LFP 0x1022
606#define DEVICE_TYPE_INT_TV 0x1009
607#define DEVICE_TYPE_HDMI 0x60D2
608#define DEVICE_TYPE_DP 0x68C6
609#define DEVICE_TYPE_eDP 0x78C6
610
611/* define the DVO port for HDMI output type */
612#define DVO_B 1
613#define DVO_C 2
614#define DVO_D 3
615
616/* define the PORT for DP output type */
617#define PORT_IDPB 7
618#define PORT_IDPC 8
619#define PORT_IDPD 9
620
Patrik Jakobsson9e8e4632013-03-14 12:36:54 +0100621#endif /* _INTEL_BIOS_H_ */