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gerrit-public.fairphone.software / kernel / msm-4.19 / a46ff73d53f011de1dfc1983b05db2c04d193713 / . / include / asm-powerpc / cpm2.h
blob: f1112c15ef96dd2ac29ed1cc91aee2744c3c3412 [file] [log] [blame]
Kumar Gala33d71d22007-08-20 08:50:28 -0500[diff] [blame]1/*
2 * Communication Processor Module v2.
3 *
4 * This file contains structures and information for the communication
5 * processor channels found in the dual port RAM or parameter RAM.
6 * All CPM control and status is available through the CPM2 internal
7 * memory map. See immap_cpm2.h for details.
8 */
9#ifdef __KERNEL__
10#ifndef __CPM2__
11#define __CPM2__
12
13#include <asm/immap_cpm2.h>
Scott Wood15f8c602007-09-28 14:06:16 -0500[diff] [blame]14#include <asm/cpm.h>
Kumar Gala33d71d22007-08-20 08:50:28 -0500[diff] [blame]15
Kumar Gala0bfd5df2007-10-11 09:13:41 -0500[diff] [blame]16#ifdef CONFIG_PPC_85xx
17#define CPM_MAP_ADDR (get_immrbase() + 0x80000)
18#endif
19
Kumar Gala33d71d22007-08-20 08:50:28 -0500[diff] [blame]20/* CPM Command register.
21*/
22#define CPM_CR_RST ((uint)0x80000000)
23#define CPM_CR_PAGE ((uint)0x7c000000)
24#define CPM_CR_SBLOCK ((uint)0x03e00000)
25#define CPM_CR_FLG ((uint)0x00010000)
26#define CPM_CR_MCN ((uint)0x00003fc0)
27#define CPM_CR_OPCODE ((uint)0x0000000f)
28
29/* Device sub-block and page codes.
30*/
31#define CPM_CR_SCC1_SBLOCK (0x04)
32#define CPM_CR_SCC2_SBLOCK (0x05)
33#define CPM_CR_SCC3_SBLOCK (0x06)
34#define CPM_CR_SCC4_SBLOCK (0x07)
35#define CPM_CR_SMC1_SBLOCK (0x08)
36#define CPM_CR_SMC2_SBLOCK (0x09)
37#define CPM_CR_SPI_SBLOCK (0x0a)
38#define CPM_CR_I2C_SBLOCK (0x0b)
39#define CPM_CR_TIMER_SBLOCK (0x0f)
40#define CPM_CR_RAND_SBLOCK (0x0e)
41#define CPM_CR_FCC1_SBLOCK (0x10)
42#define CPM_CR_FCC2_SBLOCK (0x11)
43#define CPM_CR_FCC3_SBLOCK (0x12)
44#define CPM_CR_IDMA1_SBLOCK (0x14)
45#define CPM_CR_IDMA2_SBLOCK (0x15)
46#define CPM_CR_IDMA3_SBLOCK (0x16)
47#define CPM_CR_IDMA4_SBLOCK (0x17)
48#define CPM_CR_MCC1_SBLOCK (0x1c)
49
50#define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
51
52#define CPM_CR_SCC1_PAGE (0x00)
53#define CPM_CR_SCC2_PAGE (0x01)
54#define CPM_CR_SCC3_PAGE (0x02)
55#define CPM_CR_SCC4_PAGE (0x03)
56#define CPM_CR_SMC1_PAGE (0x07)
57#define CPM_CR_SMC2_PAGE (0x08)
58#define CPM_CR_SPI_PAGE (0x09)
59#define CPM_CR_I2C_PAGE (0x0a)
60#define CPM_CR_TIMER_PAGE (0x0a)
61#define CPM_CR_RAND_PAGE (0x0a)
62#define CPM_CR_FCC1_PAGE (0x04)
63#define CPM_CR_FCC2_PAGE (0x05)
64#define CPM_CR_FCC3_PAGE (0x06)
65#define CPM_CR_IDMA1_PAGE (0x07)
66#define CPM_CR_IDMA2_PAGE (0x08)
67#define CPM_CR_IDMA3_PAGE (0x09)
68#define CPM_CR_IDMA4_PAGE (0x0a)
69#define CPM_CR_MCC1_PAGE (0x07)
70#define CPM_CR_MCC2_PAGE (0x08)
71
72#define CPM_CR_FCC_PAGE(x) (x + 0x04)
73
74/* Some opcodes (there are more...later)
75*/
76#define CPM_CR_INIT_TRX ((ushort)0x0000)
77#define CPM_CR_INIT_RX ((ushort)0x0001)
78#define CPM_CR_INIT_TX ((ushort)0x0002)
79#define CPM_CR_HUNT_MODE ((ushort)0x0003)
80#define CPM_CR_STOP_TX ((ushort)0x0004)
81#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
82#define CPM_CR_RESTART_TX ((ushort)0x0006)
83#define CPM_CR_SET_GADDR ((ushort)0x0008)
84#define CPM_CR_START_IDMA ((ushort)0x0009)
85#define CPM_CR_STOP_IDMA ((ushort)0x000b)
86
87#define mk_cr_cmd(PG, SBC, MCN, OP) \
88 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
89
Scott Wood15f8c602007-09-28 14:06:16 -0500[diff] [blame]90#ifndef CONFIG_PPC_CPM_NEW_BINDING
Kumar Gala33d71d22007-08-20 08:50:28 -0500[diff] [blame]91/* Dual Port RAM addresses. The first 16K is available for almost
92 * any CPM use, so we put the BDs there. The first 128 bytes are
93 * used for SMC1 and SMC2 parameter RAM, so we start allocating
94 * BDs above that. All of this must change when we start
95 * downloading RAM microcode.
96 */
97#define CPM_DATAONLY_BASE ((uint)128)
98#define CPM_DP_NOSPACE ((uint)0x7fffffff)
99#if defined(CONFIG_8272) || defined(CONFIG_MPC8555)
100#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
101#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
102#else
103#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
104#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
105#endif
Scott Wood15f8c602007-09-28 14:06:16 -0500[diff] [blame]106#endif
Kumar Gala33d71d22007-08-20 08:50:28 -0500[diff] [blame]107
108/* The number of pages of host memory we allocate for CPM. This is
109 * done early in kernel initialization to get physically contiguous
110 * pages.
111 */
112#define NUM_CPM_HOST_PAGES 2
113
114/* Export the base address of the communication processor registers
115 * and dual port ram.
116 */
Scott Wood449012d2007-09-14 15:30:44 -0500[diff] [blame]117extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
Kumar Gala33d71d22007-08-20 08:50:28 -0500[diff] [blame]118
Scott Wood15f8c602007-09-28 14:06:16 -0500[diff] [blame]119#ifdef CONFIG_PPC_CPM_NEW_BINDING
120#define cpm_dpalloc cpm_muram_alloc
121#define cpm_dpfree cpm_muram_free
122#define cpm_dpram_addr cpm_muram_addr
123#else
Kumar Gala33d71d22007-08-20 08:50:28 -0500[diff] [blame]124extern unsigned long cpm_dpalloc(uint size, uint align);
125extern int cpm_dpfree(unsigned long offset);
126extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
127extern void cpm_dpdump(void);
128extern void *cpm_dpram_addr(unsigned long offset);
Scott Wood15f8c602007-09-28 14:06:16 -0500[diff] [blame]129#endif
130
Kumar Gala33d71d22007-08-20 08:50:28 -0500[diff] [blame]131extern void cpm_setbrg(uint brg, uint rate);
132extern void cpm2_fastbrg(uint brg, uint rate, int div16);
133extern void cpm2_reset(void);
134
135
136/* Buffer descriptors used by many of the CPM protocols.
137*/
138typedef struct cpm_buf_desc {
139 ushort cbd_sc; /* Status and Control */
140 ushort cbd_datlen; /* Data length in buffer */
141 uint cbd_bufaddr; /* Buffer address in host memory */
142} cbd_t;
143
144#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
145#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
146#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
147#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
148#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
149#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
150#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
151#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
152#define BD_SC_BR ((ushort)0x0020) /* Break received */
153#define BD_SC_FR ((ushort)0x0010) /* Framing error */
154#define BD_SC_PR ((ushort)0x0008) /* Parity error */
155#define BD_SC_OV ((ushort)0x0002) /* Overrun */
156#define BD_SC_CD ((ushort)0x0001) /* ?? */
157
158/* Function code bits, usually generic to devices.
159*/
160#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
161#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
162#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
163#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
164#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
165
166/* Parameter RAM offsets from the base.
167*/
168#define PROFF_SCC1 ((uint)0x8000)
169#define PROFF_SCC2 ((uint)0x8100)
170#define PROFF_SCC3 ((uint)0x8200)
171#define PROFF_SCC4 ((uint)0x8300)
172#define PROFF_FCC1 ((uint)0x8400)
173#define PROFF_FCC2 ((uint)0x8500)
174#define PROFF_FCC3 ((uint)0x8600)
175#define PROFF_MCC1 ((uint)0x8700)
176#define PROFF_SMC1_BASE ((uint)0x87fc)
177#define PROFF_IDMA1_BASE ((uint)0x87fe)
178#define PROFF_MCC2 ((uint)0x8800)
179#define PROFF_SMC2_BASE ((uint)0x88fc)
180#define PROFF_IDMA2_BASE ((uint)0x88fe)
181#define PROFF_SPI_BASE ((uint)0x89fc)
182#define PROFF_IDMA3_BASE ((uint)0x89fe)
183#define PROFF_TIMERS ((uint)0x8ae0)
184#define PROFF_REVNUM ((uint)0x8af0)
185#define PROFF_RAND ((uint)0x8af8)
186#define PROFF_I2C_BASE ((uint)0x8afc)
187#define PROFF_IDMA4_BASE ((uint)0x8afe)
188
189#define PROFF_SCC_SIZE ((uint)0x100)
190#define PROFF_FCC_SIZE ((uint)0x100)
191#define PROFF_SMC_SIZE ((uint)64)
192
193/* The SMCs are relocated to any of the first eight DPRAM pages.
194 * We will fix these at the first locations of DPRAM, until we
195 * get some microcode patches :-).
196 * The parameter ram space for the SMCs is fifty-some bytes, and
197 * they are required to start on a 64 byte boundary.
198 */
199#define PROFF_SMC1 (0)
200#define PROFF_SMC2 (64)
201
202
203/* Define enough so I can at least use the serial port as a UART.
204 */
205typedef struct smc_uart {
206 ushort smc_rbase; /* Rx Buffer descriptor base address */
207 ushort smc_tbase; /* Tx Buffer descriptor base address */
208 u_char smc_rfcr; /* Rx function code */
209 u_char smc_tfcr; /* Tx function code */
210 ushort smc_mrblr; /* Max receive buffer length */
211 uint smc_rstate; /* Internal */
212 uint smc_idp; /* Internal */
213 ushort smc_rbptr; /* Internal */
214 ushort smc_ibc; /* Internal */
215 uint smc_rxtmp; /* Internal */
216 uint smc_tstate; /* Internal */
217 uint smc_tdp; /* Internal */
218 ushort smc_tbptr; /* Internal */
219 ushort smc_tbc; /* Internal */
220 uint smc_txtmp; /* Internal */
221 ushort smc_maxidl; /* Maximum idle characters */
222 ushort smc_tmpidl; /* Temporary idle counter */
223 ushort smc_brklen; /* Last received break length */
224 ushort smc_brkec; /* rcv'd break condition counter */
225 ushort smc_brkcr; /* xmt break count register */
226 ushort smc_rmask; /* Temporary bit mask */
227 uint smc_stmp; /* SDMA Temp */
228} smc_uart_t;
229
230/* SMC uart mode register (Internal memory map).
231*/
232#define SMCMR_REN ((ushort)0x0001)
233#define SMCMR_TEN ((ushort)0x0002)
234#define SMCMR_DM ((ushort)0x000c)
235#define SMCMR_SM_GCI ((ushort)0x0000)
236#define SMCMR_SM_UART ((ushort)0x0020)
237#define SMCMR_SM_TRANS ((ushort)0x0030)
238#define SMCMR_SM_MASK ((ushort)0x0030)
239#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
240#define SMCMR_REVD SMCMR_PM_EVEN
241#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
242#define SMCMR_BS SMCMR_PEN
243#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
244#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
245#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
246
247/* SMC Event and Mask register.
248*/
249#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
250#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
251#define SMCM_TXE ((unsigned char)0x10)
252#define SMCM_BSY ((unsigned char)0x04)
253#define SMCM_TX ((unsigned char)0x02)
254#define SMCM_RX ((unsigned char)0x01)
255
256/* Baud rate generators.
257*/
258#define CPM_BRG_RST ((uint)0x00020000)
259#define CPM_BRG_EN ((uint)0x00010000)
260#define CPM_BRG_EXTC_INT ((uint)0x00000000)
261#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
262#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
263#define CPM_BRG_ATB ((uint)0x00002000)
264#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
265#define CPM_BRG_DIV16 ((uint)0x00000001)
266
267/* SCCs.
268*/
269#define SCC_GSMRH_IRP ((uint)0x00040000)
270#define SCC_GSMRH_GDE ((uint)0x00010000)
271#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
272#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
273#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
274#define SCC_GSMRH_REVD ((uint)0x00002000)
275#define SCC_GSMRH_TRX ((uint)0x00001000)
276#define SCC_GSMRH_TTX ((uint)0x00000800)
277#define SCC_GSMRH_CDP ((uint)0x00000400)
278#define SCC_GSMRH_CTSP ((uint)0x00000200)
279#define SCC_GSMRH_CDS ((uint)0x00000100)
280#define SCC_GSMRH_CTSS ((uint)0x00000080)
281#define SCC_GSMRH_TFL ((uint)0x00000040)
282#define SCC_GSMRH_RFW ((uint)0x00000020)
283#define SCC_GSMRH_TXSY ((uint)0x00000010)
284#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
285#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
286#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
287#define SCC_GSMRH_RTSM ((uint)0x00000002)
288#define SCC_GSMRH_RSYN ((uint)0x00000001)
289
290#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
291#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
292#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
293#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
294#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
295#define SCC_GSMRL_TCI ((uint)0x10000000)
296#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
297#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
298#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
299#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
300#define SCC_GSMRL_RINV ((uint)0x02000000)
301#define SCC_GSMRL_TINV ((uint)0x01000000)
302#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
303#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
304#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
305#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
306#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
307#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
308#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
309#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
310#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
311#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
312#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
313#define SCC_GSMRL_TEND ((uint)0x00040000)
314#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
315#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
316#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
317#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
318#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
319#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
320#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
321#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
322#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
323#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
324#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
325#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
326#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
327#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
328#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
329#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
330#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
331#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
332#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
333#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
334#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
335#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
336#define SCC_GSMRL_ENR ((uint)0x00000020)
337#define SCC_GSMRL_ENT ((uint)0x00000010)
338#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
339#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
340#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
341#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
342#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
343#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
344#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
345#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
346#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
347#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
348
349#define SCC_TODR_TOD ((ushort)0x8000)
350
351/* SCC Event and Mask register.
352*/
353#define SCCM_TXE ((unsigned char)0x10)
354#define SCCM_BSY ((unsigned char)0x04)
355#define SCCM_TX ((unsigned char)0x02)
356#define SCCM_RX ((unsigned char)0x01)
357
358typedef struct scc_param {
359 ushort scc_rbase; /* Rx Buffer descriptor base address */
360 ushort scc_tbase; /* Tx Buffer descriptor base address */
361 u_char scc_rfcr; /* Rx function code */
362 u_char scc_tfcr; /* Tx function code */
363 ushort scc_mrblr; /* Max receive buffer length */
364 uint scc_rstate; /* Internal */
365 uint scc_idp; /* Internal */
366 ushort scc_rbptr; /* Internal */
367 ushort scc_ibc; /* Internal */
368 uint scc_rxtmp; /* Internal */
369 uint scc_tstate; /* Internal */
370 uint scc_tdp; /* Internal */
371 ushort scc_tbptr; /* Internal */
372 ushort scc_tbc; /* Internal */
373 uint scc_txtmp; /* Internal */
374 uint scc_rcrc; /* Internal */
375 uint scc_tcrc; /* Internal */
376} sccp_t;
377
378/* CPM Ethernet through SCC1.
379 */
380typedef struct scc_enet {
381 sccp_t sen_genscc;
382 uint sen_cpres; /* Preset CRC */
383 uint sen_cmask; /* Constant mask for CRC */
384 uint sen_crcec; /* CRC Error counter */
385 uint sen_alec; /* alignment error counter */
386 uint sen_disfc; /* discard frame counter */
387 ushort sen_pads; /* Tx short frame pad character */
388 ushort sen_retlim; /* Retry limit threshold */
389 ushort sen_retcnt; /* Retry limit counter */
390 ushort sen_maxflr; /* maximum frame length register */
391 ushort sen_minflr; /* minimum frame length register */
392 ushort sen_maxd1; /* maximum DMA1 length */
393 ushort sen_maxd2; /* maximum DMA2 length */
394 ushort sen_maxd; /* Rx max DMA */
395 ushort sen_dmacnt; /* Rx DMA counter */
396 ushort sen_maxb; /* Max BD byte count */
397 ushort sen_gaddr1; /* Group address filter */
398 ushort sen_gaddr2;
399 ushort sen_gaddr3;
400 ushort sen_gaddr4;
401 uint sen_tbuf0data0; /* Save area 0 - current frame */
402 uint sen_tbuf0data1; /* Save area 1 - current frame */
403 uint sen_tbuf0rba; /* Internal */
404 uint sen_tbuf0crc; /* Internal */
405 ushort sen_tbuf0bcnt; /* Internal */
406 ushort sen_paddrh; /* physical address (MSB) */
407 ushort sen_paddrm;
408 ushort sen_paddrl; /* physical address (LSB) */
409 ushort sen_pper; /* persistence */
410 ushort sen_rfbdptr; /* Rx first BD pointer */
411 ushort sen_tfbdptr; /* Tx first BD pointer */
412 ushort sen_tlbdptr; /* Tx last BD pointer */
413 uint sen_tbuf1data0; /* Save area 0 - current frame */
414 uint sen_tbuf1data1; /* Save area 1 - current frame */
415 uint sen_tbuf1rba; /* Internal */
416 uint sen_tbuf1crc; /* Internal */
417 ushort sen_tbuf1bcnt; /* Internal */
418 ushort sen_txlen; /* Tx Frame length counter */
419 ushort sen_iaddr1; /* Individual address filter */
420 ushort sen_iaddr2;
421 ushort sen_iaddr3;
422 ushort sen_iaddr4;
423 ushort sen_boffcnt; /* Backoff counter */
424
425 /* NOTE: Some versions of the manual have the following items
426 * incorrectly documented. Below is the proper order.
427 */
428 ushort sen_taddrh; /* temp address (MSB) */
429 ushort sen_taddrm;
430 ushort sen_taddrl; /* temp address (LSB) */
431} scc_enet_t;
432
433
434/* SCC Event register as used by Ethernet.
435*/
436#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
437#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
438#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
439#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
440#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
441#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
442
443/* SCC Mode Register (PSMR) as used by Ethernet.
444*/
445#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
446#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
447#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
448#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
449#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
450#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
451#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
452#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
453#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
454#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
455#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
456#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
457#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
458
459/* Buffer descriptor control/status used by Ethernet receive.
460 * Common to SCC and FCC.
461 */
462#define BD_ENET_RX_EMPTY ((ushort)0x8000)
463#define BD_ENET_RX_WRAP ((ushort)0x2000)
464#define BD_ENET_RX_INTR ((ushort)0x1000)
465#define BD_ENET_RX_LAST ((ushort)0x0800)
466#define BD_ENET_RX_FIRST ((ushort)0x0400)
467#define BD_ENET_RX_MISS ((ushort)0x0100)
468#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
469#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
470#define BD_ENET_RX_LG ((ushort)0x0020)
471#define BD_ENET_RX_NO ((ushort)0x0010)
472#define BD_ENET_RX_SH ((ushort)0x0008)
473#define BD_ENET_RX_CR ((ushort)0x0004)
474#define BD_ENET_RX_OV ((ushort)0x0002)
475#define BD_ENET_RX_CL ((ushort)0x0001)
476#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
477
478/* Buffer descriptor control/status used by Ethernet transmit.
479 * Common to SCC and FCC.
480 */
481#define BD_ENET_TX_READY ((ushort)0x8000)
482#define BD_ENET_TX_PAD ((ushort)0x4000)
483#define BD_ENET_TX_WRAP ((ushort)0x2000)
484#define BD_ENET_TX_INTR ((ushort)0x1000)
485#define BD_ENET_TX_LAST ((ushort)0x0800)
486#define BD_ENET_TX_TC ((ushort)0x0400)
487#define BD_ENET_TX_DEF ((ushort)0x0200)
488#define BD_ENET_TX_HB ((ushort)0x0100)
489#define BD_ENET_TX_LC ((ushort)0x0080)
490#define BD_ENET_TX_RL ((ushort)0x0040)
491#define BD_ENET_TX_RCMASK ((ushort)0x003c)
492#define BD_ENET_TX_UN ((ushort)0x0002)
493#define BD_ENET_TX_CSL ((ushort)0x0001)
494#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
495
496/* SCC as UART
497*/
498typedef struct scc_uart {
499 sccp_t scc_genscc;
500 uint scc_res1; /* Reserved */
501 uint scc_res2; /* Reserved */
502 ushort scc_maxidl; /* Maximum idle chars */
503 ushort scc_idlc; /* temp idle counter */
504 ushort scc_brkcr; /* Break count register */
505 ushort scc_parec; /* receive parity error counter */
506 ushort scc_frmec; /* receive framing error counter */
507 ushort scc_nosec; /* receive noise counter */
508 ushort scc_brkec; /* receive break condition counter */
509 ushort scc_brkln; /* last received break length */
510 ushort scc_uaddr1; /* UART address character 1 */
511 ushort scc_uaddr2; /* UART address character 2 */
512 ushort scc_rtemp; /* Temp storage */
513 ushort scc_toseq; /* Transmit out of sequence char */
514 ushort scc_char1; /* control character 1 */
515 ushort scc_char2; /* control character 2 */
516 ushort scc_char3; /* control character 3 */
517 ushort scc_char4; /* control character 4 */
518 ushort scc_char5; /* control character 5 */
519 ushort scc_char6; /* control character 6 */
520 ushort scc_char7; /* control character 7 */
521 ushort scc_char8; /* control character 8 */
522 ushort scc_rccm; /* receive control character mask */
523 ushort scc_rccr; /* receive control character register */
524 ushort scc_rlbc; /* receive last break character */
525} scc_uart_t;
526
527/* SCC Event and Mask registers when it is used as a UART.
528*/
529#define UART_SCCM_GLR ((ushort)0x1000)
530#define UART_SCCM_GLT ((ushort)0x0800)
531#define UART_SCCM_AB ((ushort)0x0200)
532#define UART_SCCM_IDL ((ushort)0x0100)
533#define UART_SCCM_GRA ((ushort)0x0080)
534#define UART_SCCM_BRKE ((ushort)0x0040)
535#define UART_SCCM_BRKS ((ushort)0x0020)
536#define UART_SCCM_CCR ((ushort)0x0008)
537#define UART_SCCM_BSY ((ushort)0x0004)
538#define UART_SCCM_TX ((ushort)0x0002)
539#define UART_SCCM_RX ((ushort)0x0001)
540
541/* The SCC PSMR when used as a UART.
542*/
543#define SCU_PSMR_FLC ((ushort)0x8000)
544#define SCU_PSMR_SL ((ushort)0x4000)
545#define SCU_PSMR_CL ((ushort)0x3000)
546#define SCU_PSMR_UM ((ushort)0x0c00)
547#define SCU_PSMR_FRZ ((ushort)0x0200)
548#define SCU_PSMR_RZS ((ushort)0x0100)
549#define SCU_PSMR_SYN ((ushort)0x0080)
550#define SCU_PSMR_DRT ((ushort)0x0040)
551#define SCU_PSMR_PEN ((ushort)0x0010)
552#define SCU_PSMR_RPM ((ushort)0x000c)
553#define SCU_PSMR_REVP ((ushort)0x0008)
554#define SCU_PSMR_TPM ((ushort)0x0003)
555#define SCU_PSMR_TEVP ((ushort)0x0002)
556
557/* CPM Transparent mode SCC.
558 */
559typedef struct scc_trans {
560 sccp_t st_genscc;
561 uint st_cpres; /* Preset CRC */
562 uint st_cmask; /* Constant mask for CRC */
563} scc_trans_t;
564
565#define BD_SCC_TX_LAST ((ushort)0x0800)
566
567/* How about some FCCs.....
568*/
569#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
570#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
571#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
572#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
573#define FCC_GFMR_TCI ((uint)0x20000000)
574#define FCC_GFMR_TRX ((uint)0x10000000)
575#define FCC_GFMR_TTX ((uint)0x08000000)
576#define FCC_GFMR_TTX ((uint)0x08000000)
577#define FCC_GFMR_CDP ((uint)0x04000000)
578#define FCC_GFMR_CTSP ((uint)0x02000000)
579#define FCC_GFMR_CDS ((uint)0x01000000)
580#define FCC_GFMR_CTSS ((uint)0x00800000)
581#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
582#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
583#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
584#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
585#define FCC_GFMR_RTSM ((uint)0x00002000)
586#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
587#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
588#define FCC_GFMR_REVD ((uint)0x00000400)
589#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
590#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
591#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
592#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
593#define FCC_GFMR_ENR ((uint)0x00000020)
594#define FCC_GFMR_ENT ((uint)0x00000010)
595#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
596#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
597#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
598
599/* Generic FCC parameter ram.
600*/
601typedef struct fcc_param {
602 ushort fcc_riptr; /* Rx Internal temp pointer */
603 ushort fcc_tiptr; /* Tx Internal temp pointer */
604 ushort fcc_res1;
605 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
606 uint fcc_rstate; /* Upper byte is Func code, must be set */
607 uint fcc_rbase; /* Receive BD base */
608 ushort fcc_rbdstat; /* RxBD status */
609 ushort fcc_rbdlen; /* RxBD down counter */
610 uint fcc_rdptr; /* RxBD internal data pointer */
611 uint fcc_tstate; /* Upper byte is Func code, must be set */
612 uint fcc_tbase; /* Transmit BD base */
613 ushort fcc_tbdstat; /* TxBD status */
614 ushort fcc_tbdlen; /* TxBD down counter */
615 uint fcc_tdptr; /* TxBD internal data pointer */
616 uint fcc_rbptr; /* Rx BD Internal buf pointer */
617 uint fcc_tbptr; /* Tx BD Internal buf pointer */
618 uint fcc_rcrc; /* Rx temp CRC */
619 uint fcc_res2;
620 uint fcc_tcrc; /* Tx temp CRC */
621} fccp_t;
622
623
624/* Ethernet controller through FCC.
625*/
626typedef struct fcc_enet {
627 fccp_t fen_genfcc;
628 uint fen_statbuf; /* Internal status buffer */
629 uint fen_camptr; /* CAM address */
630 uint fen_cmask; /* Constant mask for CRC */
631 uint fen_cpres; /* Preset CRC */
632 uint fen_crcec; /* CRC Error counter */
633 uint fen_alec; /* alignment error counter */
634 uint fen_disfc; /* discard frame counter */
635 ushort fen_retlim; /* Retry limit */
636 ushort fen_retcnt; /* Retry counter */
637 ushort fen_pper; /* Persistence */
638 ushort fen_boffcnt; /* backoff counter */
639 uint fen_gaddrh; /* Group address filter, high 32-bits */
640 uint fen_gaddrl; /* Group address filter, low 32-bits */
641 ushort fen_tfcstat; /* out of sequence TxBD */
642 ushort fen_tfclen;
643 uint fen_tfcptr;
644 ushort fen_mflr; /* Maximum frame length (1518) */
645 ushort fen_paddrh; /* MAC address */
646 ushort fen_paddrm;
647 ushort fen_paddrl;
648 ushort fen_ibdcount; /* Internal BD counter */
649 ushort fen_ibdstart; /* Internal BD start pointer */
650 ushort fen_ibdend; /* Internal BD end pointer */
651 ushort fen_txlen; /* Internal Tx frame length counter */
652 uint fen_ibdbase[8]; /* Internal use */
653 uint fen_iaddrh; /* Individual address filter */
654 uint fen_iaddrl;
655 ushort fen_minflr; /* Minimum frame length (64) */
656 ushort fen_taddrh; /* Filter transfer MAC address */
657 ushort fen_taddrm;
658 ushort fen_taddrl;
659 ushort fen_padptr; /* Pointer to pad byte buffer */
660 ushort fen_cftype; /* control frame type */
661 ushort fen_cfrange; /* control frame range */
662 ushort fen_maxb; /* maximum BD count */
663 ushort fen_maxd1; /* Max DMA1 length (1520) */
664 ushort fen_maxd2; /* Max DMA2 length (1520) */
665 ushort fen_maxd; /* internal max DMA count */
666 ushort fen_dmacnt; /* internal DMA counter */
667 uint fen_octc; /* Total octect counter */
668 uint fen_colc; /* Total collision counter */
669 uint fen_broc; /* Total broadcast packet counter */
670 uint fen_mulc; /* Total multicast packet count */
671 uint fen_uspc; /* Total packets < 64 bytes */
672 uint fen_frgc; /* Total packets < 64 bytes with errors */
673 uint fen_ospc; /* Total packets > 1518 */
674 uint fen_jbrc; /* Total packets > 1518 with errors */
675 uint fen_p64c; /* Total packets == 64 bytes */
676 uint fen_p65c; /* Total packets 64 < bytes <= 127 */
677 uint fen_p128c; /* Total packets 127 < bytes <= 255 */
678 uint fen_p256c; /* Total packets 256 < bytes <= 511 */
679 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
680 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
681 uint fen_cambuf; /* Internal CAM buffer poiner */
682 ushort fen_rfthr; /* Received frames threshold */
683 ushort fen_rfcnt; /* Received frames count */
684} fcc_enet_t;
685
686/* FCC Event/Mask register as used by Ethernet.
687*/
688#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
689#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
690#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
691#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
692#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
693#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
694#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
695#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
696
697/* FCC Mode Register (FPSMR) as used by Ethernet.
698*/
699#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
700#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
701#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
702#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
703#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
704#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
705#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
706#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
707#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
708#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
709#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
710#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
711#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
712
713/* IIC parameter RAM.
714*/
715typedef struct iic {
716 ushort iic_rbase; /* Rx Buffer descriptor base address */
717 ushort iic_tbase; /* Tx Buffer descriptor base address */
718 u_char iic_rfcr; /* Rx function code */
719 u_char iic_tfcr; /* Tx function code */
720 ushort iic_mrblr; /* Max receive buffer length */
721 uint iic_rstate; /* Internal */
722 uint iic_rdp; /* Internal */
723 ushort iic_rbptr; /* Internal */
724 ushort iic_rbc; /* Internal */
725 uint iic_rxtmp; /* Internal */
726 uint iic_tstate; /* Internal */
727 uint iic_tdp; /* Internal */
728 ushort iic_tbptr; /* Internal */
729 ushort iic_tbc; /* Internal */
730 uint iic_txtmp; /* Internal */
731} iic_t;
732
733/* SPI parameter RAM.
734*/
735typedef struct spi {
736 ushort spi_rbase; /* Rx Buffer descriptor base address */
737 ushort spi_tbase; /* Tx Buffer descriptor base address */
738 u_char spi_rfcr; /* Rx function code */
739 u_char spi_tfcr; /* Tx function code */
740 ushort spi_mrblr; /* Max receive buffer length */
741 uint spi_rstate; /* Internal */
742 uint spi_rdp; /* Internal */
743 ushort spi_rbptr; /* Internal */
744 ushort spi_rbc; /* Internal */
745 uint spi_rxtmp; /* Internal */
746 uint spi_tstate; /* Internal */
747 uint spi_tdp; /* Internal */
748 ushort spi_tbptr; /* Internal */
749 ushort spi_tbc; /* Internal */
750 uint spi_txtmp; /* Internal */
751 uint spi_res; /* Tx temp. */
752 uint spi_res1[4]; /* SDMA temp. */
753} spi_t;
754
755/* SPI Mode register.
756*/
757#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
758#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
759#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
760#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
761#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
762#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
763#define SPMODE_EN ((ushort)0x0100) /* Enable */
764#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
765#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
766
767#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
768#define SPMODE_PM(x) ((x) &0xF)
769
770#define SPI_EB ((u_char)0x10) /* big endian byte order */
771
772#define BD_IIC_START ((ushort)0x0400)
773
774/* IDMA parameter RAM
775*/
776typedef struct idma {
777 ushort ibase; /* IDMA buffer descriptor table base address */
778 ushort dcm; /* DMA channel mode */
779 ushort ibdptr; /* IDMA current buffer descriptor pointer */
780 ushort dpr_buf; /* IDMA transfer buffer base address */
781 ushort buf_inv; /* internal buffer inventory */
782 ushort ss_max; /* steady-state maximum transfer size */
783 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
784 ushort sts; /* source transfer size */
785 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
786 ushort seob; /* source end of burst */
787 ushort deob; /* destination end of burst */
788 ushort dts; /* destination transfer size */
789 ushort ret_add; /* return address when working in ERM=1 mode */
790 ushort res0; /* reserved */
791 uint bd_cnt; /* internal byte count */
792 uint s_ptr; /* source internal data pointer */
793 uint d_ptr; /* destination internal data pointer */
794 uint istate; /* internal state */
795 u_char res1[20]; /* pad to 64-byte length */
796} idma_t;
797
798/* DMA channel mode bit fields
799*/
800#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
801#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
802#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
803#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
804#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
805#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
806#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
807#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
808#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
809#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
810#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
811#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
812#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
813#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
814#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
815#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
816#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
817#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
818
819/* IDMA Buffer Descriptors
820*/
821typedef struct idma_bd {
822 uint flags;
823 uint len; /* data length */
824 uint src; /* source data buffer pointer */
825 uint dst; /* destination data buffer pointer */
826} idma_bd_t;
827
828/* IDMA buffer descriptor flag bit fields
829*/
830#define IDMA_BD_V ((uint)0x80000000) /* valid */
831#define IDMA_BD_W ((uint)0x20000000) /* wrap */
832#define IDMA_BD_I ((uint)0x10000000) /* interrupt */
833#define IDMA_BD_L ((uint)0x08000000) /* last */
834#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
835#define IDMA_BD_SDN ((uint)0x00400000) /* source done */
836#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
837#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
838#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
839#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
840#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
841#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
842#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
843#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
844#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
845
846/* per-channel IDMA registers
847*/
848typedef struct im_idma {
849 u_char idsr; /* IDMAn event status register */
850 u_char res0[3];
851 u_char idmr; /* IDMAn event mask register */
852 u_char res1[3];
853} im_idma_t;
854
855/* IDMA event register bit fields
856*/
857#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */
858#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */
859#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */
860#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */
861
862/* RISC Controller Configuration Register (RCCR) bit fields
863*/
864#define RCCR_TIME ((uint)0x80000000) /* timer enable */
865#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
866#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
867#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
868#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
869#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
870#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
871#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
872#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
873#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
874#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
875#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
876#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
877#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
878#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
879#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
880#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
881#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
882#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
883#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
884#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
885#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
886#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
887#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
888#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
889#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
890#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
891#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
892#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
893#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
894#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
895#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
896#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
897#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
898#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
899#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
900#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
901#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
902
903/*-----------------------------------------------------------------------
904 * CMXFCR - CMX FCC Clock Route Register
905 */
906#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
907#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
908#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
909#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
910#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
911#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
912#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
913#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
914#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
915
916#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
917#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
918#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
919#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
920#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
921#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
922#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
923#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
924
925#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
926#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
927#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
928#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
929#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
930#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
931#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
932#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
933
934#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
935#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
936#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
937#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
938#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
939#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
940#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
941#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
942
943#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
944#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
945#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
946#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
947#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
948#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
949#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
950#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
951
952#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
953#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
954#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
955#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
956#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
957#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
958#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
959#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
960
961#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
962#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
963#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
964#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
965#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
966#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
967#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
968#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
969
970/*-----------------------------------------------------------------------
971 * CMXSCR - CMX SCC Clock Route Register
972 */
973#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
974#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
975#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
976#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
977#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
978#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
979#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
980#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
981#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
982#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
983#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
984#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
985#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
986#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
987#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
988#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
989
990#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
991#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
992#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
993#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
994#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
995#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
996#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
997#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
998
999#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
1000#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
1001#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
1002#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
1003#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
1004#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
1005#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
1006#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
1007
1008#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
1009#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
1010#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
1011#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
1012#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
1013#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
1014#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
1015#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
1016
1017#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
1018#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
1019#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
1020#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
1021#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
1022#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
1023#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
1024#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
1025
1026#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
1027#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
1028#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
1029#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
1030#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
1031#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
1032#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
1033#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
1034
1035#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
1036#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
1037#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
1038#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
1039#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
1040#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
1041#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
1042#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
1043
1044#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
1045#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
1046#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
1047#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
1048#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
1049#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
1050#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
1051#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
1052
1053#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
1054#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
1055#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
1056#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
1057#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
1058#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
1059#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
1060#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
1061
1062/*-----------------------------------------------------------------------
1063 * SIUMCR - SIU Module Configuration Register 4-31
1064 */
1065#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
1066#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
1067#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
1068#define SIUMCR_CDIS 0x10000000 /* Core Disable */
1069#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
1070#define SIUMCR_DPPC01 0x04000000 /* - " - */
1071#define SIUMCR_DPPC10 0x08000000 /* - " - */
1072#define SIUMCR_DPPC11 0x0c000000 /* - " - */
1073#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
1074#define SIUMCR_L2CPC01 0x01000000 /* - " - */
1075#define SIUMCR_L2CPC10 0x02000000 /* - " - */
1076#define SIUMCR_L2CPC11 0x03000000 /* - " - */
1077#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
1078#define SIUMCR_LBPC01 0x00400000 /* - " - */
1079#define SIUMCR_LBPC10 0x00800000 /* - " - */
1080#define SIUMCR_LBPC11 0x00c00000 /* - " - */
1081#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
1082#define SIUMCR_APPC01 0x00100000 /* - " - */
1083#define SIUMCR_APPC10 0x00200000 /* - " - */
1084#define SIUMCR_APPC11 0x00300000 /* - " - */
1085#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
1086#define SIUMCR_CS10PC01 0x00040000 /* - " - */
1087#define SIUMCR_CS10PC10 0x00080000 /* - " - */
1088#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
1089#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
1090#define SIUMCR_BCTLC01 0x00010000 /* - " - */
1091#define SIUMCR_BCTLC10 0x00020000 /* - " - */
1092#define SIUMCR_BCTLC11 0x00030000 /* - " - */
1093#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
1094#define SIUMCR_MMR01 0x00004000 /* - " - */
1095#define SIUMCR_MMR10 0x00008000 /* - " - */
1096#define SIUMCR_MMR11 0x0000c000 /* - " - */
1097#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
1098
1099/*-----------------------------------------------------------------------
1100 * SCCR - System Clock Control Register 9-8
1101*/
1102#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
1103#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
1104#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
1105#define SCCR_PCIDF_SHIFT 3
1106
1107#ifndef CPM_IMMR_OFFSET
1108#define CPM_IMMR_OFFSET 0x101a8
1109#endif
1110
1111#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
1112
1113/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
1114 * in order to use clock-computing stuff below for the FCC x
1115 */
1116
1117/* Automatically generates register configurations */
1118#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
1119
1120#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
1121#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
1122#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
1123#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
1124#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
1125#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1126
1127#define PC_F1RXCLK PC_CLK(F1_RXCLK)
1128#define PC_F1TXCLK PC_CLK(F1_TXCLK)
1129#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1130#define CMX1_CLK_MASK ((uint)0xff000000)
1131
1132#define PC_F2RXCLK PC_CLK(F2_RXCLK)
1133#define PC_F2TXCLK PC_CLK(F2_TXCLK)
1134#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1135#define CMX2_CLK_MASK ((uint)0x00ff0000)
1136
1137#define PC_F3RXCLK PC_CLK(F3_RXCLK)
1138#define PC_F3TXCLK PC_CLK(F3_TXCLK)
1139#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1140#define CMX3_CLK_MASK ((uint)0x0000ff00)
1141
1142#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1143#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1144
1145#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1146
1147/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
1148 * but there is little variation among the choices.
1149 */
1150#define PA1_COL 0x00000001U
1151#define PA1_CRS 0x00000002U
1152#define PA1_TXER 0x00000004U
1153#define PA1_TXEN 0x00000008U
1154#define PA1_RXDV 0x00000010U
1155#define PA1_RXER 0x00000020U
1156#define PA1_TXDAT 0x00003c00U
1157#define PA1_RXDAT 0x0003c000U
1158#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
1159#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1160 PA1_RXDV | PA1_RXER)
1161#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1162#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
1163
1164
1165/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
1166 * but there is little variation among the choices.
1167 */
1168#define PB2_TXER 0x00000001U
1169#define PB2_RXDV 0x00000002U
1170#define PB2_TXEN 0x00000004U
1171#define PB2_RXER 0x00000008U
1172#define PB2_COL 0x00000010U
1173#define PB2_CRS 0x00000020U
1174#define PB2_TXDAT 0x000003c0U
1175#define PB2_RXDAT 0x00003c00U
1176#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1177 PB2_RXER | PB2_RXDV | PB2_TXER)
1178#define PB2_PSORB1 (PB2_TXEN)
1179#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1180#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
1181
1182
1183/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
1184 * but there is little variation among the choices.
1185 */
1186#define PB3_RXDV 0x00004000U
1187#define PB3_RXER 0x00008000U
1188#define PB3_TXER 0x00010000U
1189#define PB3_TXEN 0x00020000U
1190#define PB3_COL 0x00040000U
1191#define PB3_CRS 0x00080000U
1192#define PB3_TXDAT 0x0f000000U
1193#define PC3_TXDAT 0x00000010U
1194#define PB3_RXDAT 0x00f00000U
1195#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1196 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1197#define PB3_PSORB1 0
1198#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1199#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
1200#define PC3_DIRC1 (PC3_TXDAT)
1201
1202/* Handy macro to specify mem for FCCs*/
1203#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1204#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1205#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1206#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
1207
1208/* Clocks and GRG's */
1209
1210enum cpm_clk_dir {
1211 CPM_CLK_RX,
1212 CPM_CLK_TX,
1213 CPM_CLK_RTX
1214};
1215
1216enum cpm_clk_target {
1217 CPM_CLK_SCC1,
1218 CPM_CLK_SCC2,
1219 CPM_CLK_SCC3,
1220 CPM_CLK_SCC4,
1221 CPM_CLK_FCC1,
1222 CPM_CLK_FCC2,
Scott Wood2652d4e2007-07-16 13:26:35 -0500[diff] [blame]1223 CPM_CLK_FCC3,
1224 CPM_CLK_SMC1,
1225 CPM_CLK_SMC2,
Kumar Gala33d71d22007-08-20 08:50:28 -0500[diff] [blame]1226};
1227
1228enum cpm_clk {
1229 CPM_CLK_NONE = 0,
1230 CPM_BRG1, /* Baud Rate Generator 1 */
1231 CPM_BRG2, /* Baud Rate Generator 2 */
1232 CPM_BRG3, /* Baud Rate Generator 3 */
1233 CPM_BRG4, /* Baud Rate Generator 4 */
1234 CPM_BRG5, /* Baud Rate Generator 5 */
1235 CPM_BRG6, /* Baud Rate Generator 6 */
1236 CPM_BRG7, /* Baud Rate Generator 7 */
1237 CPM_BRG8, /* Baud Rate Generator 8 */
1238 CPM_CLK1, /* Clock 1 */
1239 CPM_CLK2, /* Clock 2 */
1240 CPM_CLK3, /* Clock 3 */
1241 CPM_CLK4, /* Clock 4 */
1242 CPM_CLK5, /* Clock 5 */
1243 CPM_CLK6, /* Clock 6 */
1244 CPM_CLK7, /* Clock 7 */
1245 CPM_CLK8, /* Clock 8 */
1246 CPM_CLK9, /* Clock 9 */
1247 CPM_CLK10, /* Clock 10 */
1248 CPM_CLK11, /* Clock 11 */
1249 CPM_CLK12, /* Clock 12 */
1250 CPM_CLK13, /* Clock 13 */
1251 CPM_CLK14, /* Clock 14 */
1252 CPM_CLK15, /* Clock 15 */
1253 CPM_CLK16, /* Clock 16 */
1254 CPM_CLK17, /* Clock 17 */
1255 CPM_CLK18, /* Clock 18 */
1256 CPM_CLK19, /* Clock 19 */
1257 CPM_CLK20, /* Clock 20 */
1258 CPM_CLK_DUMMY
1259};
1260
1261extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
Scott Wood2652d4e2007-07-16 13:26:35 -0500[diff] [blame]1262extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
Kumar Gala33d71d22007-08-20 08:50:28 -0500[diff] [blame]1263
Scott Wood7f21f522007-07-16 13:32:24 -0500[diff] [blame]1264#define CPM_PIN_INPUT 0
1265#define CPM_PIN_OUTPUT 1
1266#define CPM_PIN_PRIMARY 0
1267#define CPM_PIN_SECONDARY 2
1268#define CPM_PIN_GPIO 4
1269#define CPM_PIN_OPENDRAIN 8
1270
1271void cpm2_set_pin(int port, int pin, int flags);
1272
Kumar Gala33d71d22007-08-20 08:50:28 -0500[diff] [blame]1273#endif /* __CPM2__ */
1274#endif /* __KERNEL__ */