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gerrit-public.fairphone.software / kernel / msm-4.19 / a68bd1267b7286b1687905651b404e765046de25 / . / arch / powerpc / platforms / powernv / pci.h
blob: 0020937fc694c3c9ed4491048cf45a15ca78ab14 [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]2#ifndef __POWERNV_PCI_H
3#define __POWERNV_PCI_H
4
Ian Munsief4568342016-07-14 07:17:00 +1000[diff] [blame]5#include <linux/iommu.h>
6#include <asm/iommu.h>
7#include <asm/msi_bitmap.h>
8
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]9struct pci_dn;
10
Alistair Popple1ab66d12017-04-03 19:51:44 +1000[diff] [blame]11/* Maximum possible number of ATSD MMIO registers per NPU */
12#define NV_NMMU_ATSD_REGS 8
13
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]14enum pnv_phb_type {
Frederic Barrat7f2c39e2018-01-23 12:31:36 +0100[diff] [blame]15 PNV_PHB_IODA1 = 0,
16 PNV_PHB_IODA2 = 1,
17 PNV_PHB_NPU_NVLINK = 2,
18 PNV_PHB_NPU_OCAPI = 3,
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]19};
20
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]21/* Precise PHB model for error management */
22enum pnv_phb_model {
23 PNV_PHB_MODEL_UNKNOWN,
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]24 PNV_PHB_MODEL_P7IOC,
Gavin Shanaa0c0332013-04-25 19:20:57 +0000[diff] [blame]25 PNV_PHB_MODEL_PHB3,
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]26 PNV_PHB_MODEL_NPU,
Alistair Popple616badd2017-01-10 15:41:44 +1100[diff] [blame]27 PNV_PHB_MODEL_NPU2,
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]28};
29
Gavin Shan5c9d6d72013-09-06 09:00:03 +0800[diff] [blame]30#define PNV_PCI_DIAG_BUF_SIZE 8192
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]31#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
32#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
33#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]34#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
35#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
Wei Yang781a8682015-03-25 16:23:57 +0800[diff] [blame]36#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]37
Russell Currey31bbd452017-06-14 14:19:58 +1000[diff] [blame]38/* Indicates operations are frozen for a PE: MMIO in PESTA & DMA in PESTB. */
39#define PNV_IODA_STOPPED_STATE 0x8000000000000000
40
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]41/* Data associated with a PE, including IOMMU tracking etc.. */
Gavin Shan4cce9552013-04-25 19:21:00 +0000[diff] [blame]42struct pnv_phb;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]43struct pnv_ioda_pe {
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]44 unsigned long flags;
Gavin Shan4cce9552013-04-25 19:21:00 +0000[diff] [blame]45 struct pnv_phb *phb;
Gavin Shanc5f77002016-05-20 16:41:35 +1000[diff] [blame]46 int device_count;
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]47
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]48 /* A PE can be associated with a single device or an
49 * entire bus (& children). In the former case, pdev
50 * is populated, in the later case, pbus is.
51 */
Wei Yang781a8682015-03-25 16:23:57 +0800[diff] [blame]52#ifdef CONFIG_PCI_IOV
53 struct pci_dev *parent_dev;
54#endif
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]55 struct pci_dev *pdev;
56 struct pci_bus *pbus;
57
58 /* Effective RID (device RID for a device PE and base bus
59 * RID with devfn 0 for a bus PE)
60 */
61 unsigned int rid;
62
63 /* PE number */
64 unsigned int pe_number;
65
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]66 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
Alexey Kardashevskiyb348aa62015-06-05 16:35:08 +1000[diff] [blame]67 struct iommu_table_group table_group;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]68
Benjamin Herrenschmidtcd15b042014-02-11 11:32:38 +1100[diff] [blame]69 /* 64-bit TCE bypass region */
70 bool tce_bypass_enabled;
71 uint64_t tce_bypass_base;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]72
73 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
74 * and -1 if not supported. (It's actually identical to the
75 * PE number)
76 */
77 int mve_number;
78
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]79 /* PEs in compound case */
80 struct pnv_ioda_pe *master;
81 struct list_head slaves;
82
Frederic Barrat25529102017-08-04 11:55:14 +0200[diff] [blame]83 /* PCI peer-to-peer*/
84 int p2p_initiator_count;
85
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]86 /* Link in list of PE#s */
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]87 struct list_head list;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]88};
89
Gavin Shanf5bc6b72014-04-24 18:00:09 +1000[diff] [blame]90#define PNV_PHB_FLAG_EEH (1 << 0)
Ian Munsie4361b032016-07-14 07:17:06 +1000[diff] [blame]91#define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */
Gavin Shanf5bc6b72014-04-24 18:00:09 +1000[diff] [blame]92
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]93struct pnv_phb {
94 struct pci_controller *hose;
95 enum pnv_phb_type type;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]96 enum pnv_phb_model model;
Gavin Shan8747f362013-06-20 13:21:06 +0800[diff] [blame]97 u64 hub_id;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]98 u64 opal_id;
Gavin Shanf5bc6b72014-04-24 18:00:09 +1000[diff] [blame]99 int flags;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]100 void __iomem *regs;
Benjamin Herrenschmidtfd141d1a2016-07-08 16:37:14 +1000[diff] [blame]101 u64 regs_phys;
Gavin Shandb1266c2012-08-20 03:49:18 +0000[diff] [blame]102 int initialized;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]103 spinlock_t lock;
104
Gavin Shan37c367f2013-06-20 18:13:25 +0800[diff] [blame]105#ifdef CONFIG_DEBUG_FS
Gavin Shan7f52a5262014-04-24 18:00:18 +1000[diff] [blame]106 int has_dbgfs;
Gavin Shan37c367f2013-06-20 18:13:25 +0800[diff] [blame]107 struct dentry *dbgfs;
108#endif
109
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]110#ifdef CONFIG_PCI_MSI
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]111 unsigned int msi_base;
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]112 unsigned int msi32_support;
Gavin Shanfb1b55d2013-03-05 21:12:37 +0000[diff] [blame]113 struct msi_bitmap msi_bmp;
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]114#endif
115 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
Gavin Shan137436c2013-04-25 19:20:59 +0000[diff] [blame]116 unsigned int hwirq, unsigned int virq,
117 unsigned int is_64, struct msi_msg *msg);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]118 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
119 void (*fixup_phb)(struct pci_controller *hose);
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]120 int (*init_m64)(struct pnv_phb *phb);
Gavin Shan96a2f922015-06-19 12:26:17 +1000[diff] [blame]121 void (*reserve_m64_pe)(struct pci_bus *bus,
122 unsigned long *pe_bitmap, bool all);
Gavin Shan1e916772016-05-03 15:41:36 +1000[diff] [blame]123 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
Gavin Shan49dec922014-07-21 14:42:33 +1000[diff] [blame]124 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
125 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
126 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]127
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]128 struct {
129 /* Global bridge info */
Gavin Shan92b8f132016-05-03 15:41:24 +1000[diff] [blame]130 unsigned int total_pe_num;
131 unsigned int reserved_pe_idx;
Gavin Shan63803c32016-05-20 16:41:32 +1000[diff] [blame]132 unsigned int root_pe_idx;
133 bool root_pe_populated;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]134
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]135 /* 32-bit MMIO window */
136 unsigned int m32_size;
137 unsigned int m32_segsize;
138 unsigned int m32_pci_base;
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]139
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]140 /* 64-bit MMIO window */
141 unsigned int m64_bar_idx;
142 unsigned long m64_size;
143 unsigned long m64_segsize;
144 unsigned long m64_base;
145 unsigned long m64_bar_alloc;
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]146
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]147 /* IO ports */
148 unsigned int io_size;
149 unsigned int io_segsize;
150 unsigned int io_pci_base;
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]151
Gavin Shan13ce7592016-05-03 15:41:23 +1000[diff] [blame]152 /* PE allocation */
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]153 struct mutex pe_alloc_mutex;
Gavin Shan13ce7592016-05-03 15:41:23 +1000[diff] [blame]154 unsigned long *pe_alloc;
155 struct pnv_ioda_pe *pe_array;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]156
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]157 /* M32 & IO segment maps */
Gavin Shan93289d82016-05-03 15:41:29 +1000[diff] [blame]158 unsigned int *m64_segmap;
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]159 unsigned int *m32_segmap;
160 unsigned int *io_segmap;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]161
Gavin Shan2b923ed2016-05-05 12:04:16 +1000[diff] [blame]162 /* DMA32 segment maps - IODA1 only */
163 unsigned int dma32_count;
164 unsigned int *dma32_segmap;
165
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]166 /* IRQ chip */
167 int irq_chip_init;
168 struct irq_chip irq_chip;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]169
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]170 /* Sorted list of used PE's based
171 * on the sequence of creation
172 */
173 struct list_head pe_list;
174 struct mutex pe_list_mutex;
Gavin Shan137436c2013-04-25 19:20:59 +0000[diff] [blame]175
Gavin Shanc1275622016-05-20 16:41:29 +1000[diff] [blame]176 /* Reverse map of PEs, indexed by {bus, devfn} */
177 unsigned int pe_rmap[0x10000];
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]178 } ioda;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]179
Russell Currey5cb1f8f2017-06-14 14:19:59 +1000[diff] [blame]180 /* PHB and hub diagnostics */
181 unsigned int diag_data_size;
182 u8 *diag_data;
Brian W Hartca1de5d2013-12-20 13:06:01 -0600[diff] [blame]183
Alistair Popple1ab66d12017-04-03 19:51:44 +1000[diff] [blame]184 /* Nvlink2 data */
185 struct npu {
186 int index;
187 __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
188 unsigned int mmio_atsd_count;
189
190 /* Bitmask for MMIO register usage */
191 unsigned long mmio_atsd_usage;
Alistair Popple1b2c2b12017-09-06 11:49:00 +1000[diff] [blame]192
193 /* Do we need to explicitly flush the nest mmu? */
194 bool nmmu_flush;
Alistair Popple1ab66d12017-04-03 19:51:44 +1000[diff] [blame]195 } npu;
196
Ian Munsie4361b032016-07-14 07:17:06 +1000[diff] [blame]197#ifdef CONFIG_CXL_BASE
198 struct cxl_afu *cxl_afu;
199#endif
Frederic Barrat25529102017-08-04 11:55:14 +0200[diff] [blame]200 int p2p_target_count;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]201};
202
203extern struct pci_ops pnv_pci_ops;
204
Gavin Shan93aef2a2013-11-22 16:28:45 +0800[diff] [blame]205void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
206 unsigned char *log_buff);
Gavin Shan3532a7412015-03-17 16:15:03 +1100[diff] [blame]207int pnv_pci_cfg_read(struct pci_dn *pdn,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800[diff] [blame]208 int where, int size, u32 *val);
Gavin Shan3532a7412015-03-17 16:15:03 +1100[diff] [blame]209int pnv_pci_cfg_write(struct pci_dn *pdn,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800[diff] [blame]210 int where, int size, u32 val);
Alexey Kardashevskiy0eaf4de2015-06-05 16:35:09 +1000[diff] [blame]211extern struct iommu_table *pnv_pci_table_alloc(int nid);
212
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]213extern void pnv_pci_init_ioda_hub(struct device_node *np);
Gavin Shanaa0c0332013-04-25 19:20:57 +0000[diff] [blame]214extern void pnv_pci_init_ioda2_phb(struct device_node *np);
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]215extern void pnv_pci_init_npu_phb(struct device_node *np);
Frederic Barrat7f2c39e2018-01-23 12:31:36 +0100[diff] [blame]216extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
Gavin Shand92a2082014-04-24 18:00:24 +1000[diff] [blame]217extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
Gavin Shancadf3642015-02-16 14:45:47 +1100[diff] [blame]218extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
Benjamin Herrenschmidt73ed1482013-05-10 16:59:18 +1000[diff] [blame]219
Daniel Axtens92ae0352015-04-28 15:12:05 +1000[diff] [blame]220extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
Gavin Shan1bc74f12016-02-09 15:50:22 +1100[diff] [blame]221extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
Daniel Axtens92ae0352015-04-28 15:12:05 +1000[diff] [blame]222extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
223extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
Ian Munsief4568342016-07-14 07:17:00 +1000[diff] [blame]224extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
225extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
Ian Munsie4361b032016-07-14 07:17:06 +1000[diff] [blame]226extern bool pnv_pci_enable_device_hook(struct pci_dev *dev);
Frederic Barrat25529102017-08-04 11:55:14 +0200[diff] [blame]227extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
Benjamin Herrenschmidtb9fde582017-09-07 16:35:44 +1000[diff] [blame]228extern int pnv_eeh_post_init(void);
Daniel Axtens92ae0352015-04-28 15:12:05 +1000[diff] [blame]229
Alexey Kardashevskiy7d623e42016-04-29 18:55:21 +1000[diff] [blame]230extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
231 const char *fmt, ...);
232#define pe_err(pe, fmt, ...) \
233 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
234#define pe_warn(pe, fmt, ...) \
235 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
236#define pe_info(pe, fmt, ...) \
237 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
238
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]239/* Nvlink functions */
Alexey Kardashevskiyf9f83452016-04-29 18:55:20 +1000[diff] [blame]240extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
Alistair Popple6b3d12a2017-05-03 13:24:08 +1000[diff] [blame]241extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
Alexey Kardashevskiyb5cb9ab2016-04-29 18:55:24 +1000[diff] [blame]242extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
243extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
244 struct iommu_table *tbl);
245extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
246extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
247extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
Alistair Popple1ab66d12017-04-03 19:51:44 +1000[diff] [blame]248extern int pnv_npu2_init(struct pnv_phb *phb);
Ian Munsie4361b032016-07-14 07:17:06 +1000[diff] [blame]249
250/* cxl functions */
251extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);
252extern void pnv_cxl_disable_device(struct pci_dev *dev);
Ian Munsiea2f67d52016-07-14 07:17:10 +1000[diff] [blame]253extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
254extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
Ian Munsie4361b032016-07-14 07:17:06 +1000[diff] [blame]255
256
257/* phb ops (cxl switches these when enabling the kernel api on the phb) */
258extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops;
259
Alexey Kardashevskiy191c2282018-07-04 16:13:45 +1000[diff] [blame]260/* pci-ioda-tce.c */
261#define POWERNV_IOMMU_DEFAULT_LEVELS 1
262#define POWERNV_IOMMU_MAX_LEVELS 5
263
264extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
265 unsigned long uaddr, enum dma_data_direction direction,
266 unsigned long attrs);
267extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
268extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
Alexey Kardashevskiya68bd122018-07-04 16:13:49 +1000[diff] [blame^]269 unsigned long *hpa, enum dma_data_direction *direction,
270 bool alloc);
271extern __be64 *pnv_tce_useraddrptr(struct iommu_table *tbl, long index,
272 bool alloc);
Alexey Kardashevskiy191c2282018-07-04 16:13:45 +1000[diff] [blame]273extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
274
275extern long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
276 __u32 page_shift, __u64 window_size, __u32 levels,
Alexey Kardashevskiy090bad32018-07-04 16:13:47 +1000[diff] [blame]277 bool alloc_userspace_copy, struct iommu_table *tbl);
Alexey Kardashevskiy191c2282018-07-04 16:13:45 +1000[diff] [blame]278extern void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl);
279
280extern long pnv_pci_link_table_and_group(int node, int num,
281 struct iommu_table *tbl,
282 struct iommu_table_group *table_group);
283extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
284 struct iommu_table_group *table_group);
285extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
286 void *tce_mem, u64 tce_size,
287 u64 dma_offset, unsigned int page_shift);
288
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]289#endif /* __POWERNV_PCI_H */