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Linus Torvalds1da177e2005-04-16 15:20:36 -07001if ARCH_IXP4XX
2
3config ARCH_SUPPORTS_BIG_ENDIAN
4 bool
5 default y
6
7menu "Intel IXP4xx Implementation Options"
8
9comment "IXP4xx Platforms"
10
Alessandro Zummoa7918f32005-11-10 14:05:04 +000011# This entry is placed on top because otherwise it would have
12# been shown as a submenu.
13config MACH_NSLU2
14 bool
15 prompt "NSLU2" if !(MACH_IXDP465 || MACH_IXDPG425 || ARCH_IXDP425 || ARCH_ADI_COYOTE || ARCH_AVILA || ARCH_IXCDP1100 || ARCH_PRPMC1100 || MACH_GTWX5715)
16 help
17 Say 'Y' here if you want your kernel to support Linksys's
18 NSLU2 NAS device. For more information on this platform,
19 see http://www.nslu2-linux.org
20
Linus Torvalds1da177e2005-04-16 15:20:36 -070021config ARCH_AVILA
22 bool "Avila"
23 help
24 Say 'Y' here if you want your kernel to support the Gateworks
25 Avila Network Platform. For more information on this platform,
26 see <file:Documentation/arm/IXP4xx>.
27
28config ARCH_ADI_COYOTE
29 bool "Coyote"
30 help
31 Say 'Y' here if you want your kernel to support the ADI
32 Engineering Coyote Gateway Reference Platform. For more
33 information on this platform, see <file:Documentation/arm/IXP4xx>.
34
35config ARCH_IXDP425
36 bool "IXDP425"
37 help
38 Say 'Y' here if you want your kernel to support Intel's
39 IXDP425 Development Platform (Also known as Richfield).
40 For more information on this platform, see <file:Documentation/arm/IXP4xx>.
41
42config MACH_IXDPG425
43 bool "IXDPG425"
44 help
45 Say 'Y' here if you want your kernel to support Intel's
46 IXDPG425 Development Platform (Also known as Montajade).
47 For more information on this platform, see <file:Documentation/arm/IXP4xx>.
48
49config MACH_IXDP465
50 bool "IXDP465"
51 help
52 Say 'Y' here if you want your kernel to support Intel's
53 IXDP465 Development Platform (Also known as BMP).
akpm@osdl.org7aa52f52005-04-16 15:23:56 -070054 For more information on this platform, see <file:Documentation/arm/IXP4xx>.
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
56
57#
58# IXCDP1100 is the exact same HW as IXDP425, but with a different machine
59# number from the bootloader due to marketing monkeys, so we just enable it
60# by default if IXDP425 is enabled.
61#
62config ARCH_IXCDP1100
63 bool
64 depends on ARCH_IXDP425
65 default y
66
67config ARCH_PRPMC1100
68 bool "PrPMC1100"
69 help
70 Say 'Y' here if you want your kernel to support the Motorola
71 PrPCM1100 Processor Mezanine Module. For more information on
72 this platform, see <file:Documentation/arm/IXP4xx>.
73
74#
75# Avila and IXDP share the same source for now. Will change in future
76#
77config ARCH_IXDP4XX
78 bool
79 depends on ARCH_IXDP425 || ARCH_AVILA || MACH_IXDP465
80 default y
81
82#
83# Certain registers and IRQs are only enabled if supporting IXP465 CPUs
84#
85config CPU_IXP46X
86 bool
87 depends on MACH_IXDP465
88 default y
89
90config MACH_GTWX5715
91 bool "Gemtek WX5715 (Linksys WRV54G)"
92 depends on ARCH_IXP4XX
93 help
94 This board is currently inside the Linksys WRV54G Gateways.
95
96 IXP425 - 266mhz
97 32mb SDRAM
98 8mb Flash
99 miniPCI slot 0 does not have a card connector soldered to the board
100 miniPCI slot 1 has an ISL3880 802.11g card (Prism54)
101 npe0 is connected to a Kendin KS8995M Switch (4 ports)
102 npe1 is the "wan" port
103 "Console" UART is available on J11 as console
104 "High Speed" UART is n/c (as far as I can tell)
105 20 Pin ARM/Xscale JTAG interface on J2
106
107
108comment "IXP4xx Options"
109
110config IXP4XX_INDIRECT_PCI
111 bool "Use indirect PCI memory access"
112 help
113 IXP4xx provides two methods of accessing PCI memory space:
114
115 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
116 To access PCI via this space, we simply ioremap() the BAR
117 into the kernel and we can use the standard read[bwl]/write[bwl]
118 macros. This is the preferred method due to speed but it
119 limits the system to just 64MB of PCI memory. This can be
120 problamatic if using video cards and other memory-heavy devices.
121
122 2) If > 64MB of memory space is required, the IXP4xx can be
123 configured to use indirect registers to access PCI This allows
124 for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
125 The disadvantadge of this is that every PCI access requires
126 three local register accesses plus a spinlock, but in some
127 cases the performance hit is acceptable. In addition, you cannot
128 mmap() PCI devices in this case due to the indirect nature
129 of the PCI window.
130
131 By default, the direct method is used. Choose this option if you
132 need to use the indirect method instead. If you don't know
133 what you need, leave this option unselected.
134
135endmenu
136
137endif