arch/arm64/boot/dts/qcom/kona.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

#include "skeleton64.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
	model = "Qualcomm Technologies, Inc. kona";
	compatible = "qcom,kona";
	qcom,msm-id = <356 0x10000>;
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "spin-table";
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_0>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
				      compatible = "arm,arch-cache";
				      cache-size = <0x400000>;
				      cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "spin-table";
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_1>;
			L2_1: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			enable-method = "spin-table";
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_2>;
			L2_2: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x300>;
			enable-method = "spin-table";
			cache-size = <0x8000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_3>;
			L2_3: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x400>;
			enable-method = "spin-table";
			cache-size = <0x10000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_4>;
			L2_4: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x500>;
			enable-method = "spin-table";
			cache-size = <0x10000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_5>;
			L2_5: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x600>;
			enable-method = "spin-table";
			cache-size = <0x10000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_6>;
			L2_6: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x20000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x700>;
			enable-method = "spin-table";
			cache-size = <0x10000>;
			cpu-release-addr = <0x0 0x90000000>;
			next-level-cache = <&L2_7>;
			L2_7: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x80000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};

				core3 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	soc: soc { };

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_mem: hyp_region@80000000 {
			no-map;
			reg = <0x0 0x80000000 0x0 0x600000>;
		};

		xbl_aop_mem: xbl_aop_region@80700000 {
			no-map;
			reg = <0x0 0x80700000 0x0 0x140000>;
		};

		smem_mem: smem_region@80900000 {
			no-map;
			reg = <0x0 0x80900000 0x0 0x200000>;
		};

		removed_mem: removed_region@80b00000 {
			no-map;
			reg = <0x0 0x80b00000 0x0 0xc00000>;
		};

		qtee_apps_mem: qtee_apps_region@81e00000 {
			no-map;
			reg = <0x0 0x81e00000 0x0 0x2600000>;
		};

		pil_camera_mem: pil_camera_region@86000000 {
			no-map;
			reg = <0x0 0x86000000 0x0 0x500000>;
		};

		pil_wlan_fw_mem: pil_wlan_fw_region@86500000 {
			no-map;
			reg = <0x0 0x86500000 0x0 0x100000>;
		};

		pil_ipa_fw_mem: pil_ipa_fw_region@86600000 {
			no-map;
			reg = <0x0 0x86600000 0x0 0x10000>;
		};

		pil_ipa_gsi_mem: pil_ipa_gsi_region@86610000 {
			no-map;
			reg = <0x0 0x86610000 0x0 0x5000>;
		};

		pil_gpu_mem: pil_gpu_region@86615000 {
			no-map;
			reg = <0x0 0x86615000 0x0 0x2000>;
		};

		pil_npu_mem: pil_npu_region@86680000 {
			no-map;
			reg = <0x0 0x86680000 0x0 0x80000>;
		};

		pil_video_mem: pil_video_region@86700000 {
			no-map;
			reg = <0x0 0x86700000 0x0 0x500000>;
		};

		pil_cvp_mem: pil_cvp_region@86c00000 {
			no-map;
			reg = <0x0 0x86c00000 0x0 0x500000>;
		};

		pil_cdsp_mem: pil_cdsp_region@87100000 {
			no-map;
			reg = <0x0 0x87100000 0x0 0x800000>;
		};

		pil_slpi_mem: pil_slpi_region@87900000 {
			no-map;
			reg = <0x0 0x87900000 0x0 0x1400000>;
		};

		pil_adsp_mem: pil_adsp_region@88d00000 {
			no-map;
			reg = <0x0 0x88d00000 0x0 0x1a00000>;
		};

		pil_spss_mem: pil_spss_region@8a700000 {
			no-map;
			reg = <0x0 0x8a700000 0x0 0x100000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x2000000>;
			linux,cma-default;
		};
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17a00000 0x10000>,     /* GICD */
		      <0x17a60000 0x100000>;    /* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	timer@0x17c00000{
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17c00000 0x1000>;
		clock-frequency = <19200000>;

		frame@0x17c10000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17c10000 0x1000>,
			      <0x17c20000 0x1000>;
		};

		frame@17c30000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 8 0x4>;
			reg = <0x17c30000 0x1000>;
			status = "disabled";
		};

		frame@17c40000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 9 0x4>;
			reg = <0x17c40000 0x1000>;
			status = "disabled";
		};

		frame@17c60000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 10 0x4>;
			reg = <0x17c60000 0x1000>;
			status = "disabled";
		};

		frame@17c70000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 11 0x4>;
			reg = <0x17c70000 0x1000>;
			status = "disabled";
		};

		frame@17c800000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 12 0x4>;
			reg = <0x17c80000 0x1000>;
			status = "disabled";
		};

		frame@17c90000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 13 0x4>;
			reg = <0x17c90000 0x1000>;
			status = "disabled";
		};
	};
};