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gerrit-public.fairphone.software / kernel / msm-4.19 / a9efad8b24bd22616f6c749a6c029957dc76542b / . / drivers / pinctrl / meson / pinctrl-meson8b.c
blob: 874f2edf8be39236aad367be3edb9f6aa7796bf0 [file] [log] [blame]
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]1/*
2 * Pin controller and GPIO driver for Amlogic Meson8b.
3 *
4 * Copyright (C) 2015 Endless Mobile, Inc.
5 * Author: Carlo Caione <carlo@endlessm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program. If not, see <http://www.gnu.org/licenses/>.
13 */
14
15#include <dt-bindings/gpio/meson8b-gpio.h>
16#include "pinctrl-meson.h"
17
18#define AO_OFF 130
19
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]20static const struct pinctrl_pin_desc meson8b_cbus_pins[] = {
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]21 MESON_PIN(GPIOX_0, 0),
22 MESON_PIN(GPIOX_1, 0),
23 MESON_PIN(GPIOX_2, 0),
24 MESON_PIN(GPIOX_3, 0),
25 MESON_PIN(GPIOX_4, 0),
26 MESON_PIN(GPIOX_5, 0),
27 MESON_PIN(GPIOX_6, 0),
28 MESON_PIN(GPIOX_7, 0),
29 MESON_PIN(GPIOX_8, 0),
30 MESON_PIN(GPIOX_9, 0),
31 MESON_PIN(GPIOX_10, 0),
32 MESON_PIN(GPIOX_11, 0),
33 MESON_PIN(GPIOX_16, 0),
34 MESON_PIN(GPIOX_17, 0),
35 MESON_PIN(GPIOX_18, 0),
36 MESON_PIN(GPIOX_19, 0),
37 MESON_PIN(GPIOX_20, 0),
38 MESON_PIN(GPIOX_21, 0),
39
40 MESON_PIN(GPIOY_0, 0),
41 MESON_PIN(GPIOY_1, 0),
42 MESON_PIN(GPIOY_3, 0),
43 MESON_PIN(GPIOY_6, 0),
44 MESON_PIN(GPIOY_7, 0),
45 MESON_PIN(GPIOY_8, 0),
46 MESON_PIN(GPIOY_9, 0),
47 MESON_PIN(GPIOY_10, 0),
48 MESON_PIN(GPIOY_11, 0),
49 MESON_PIN(GPIOY_12, 0),
50 MESON_PIN(GPIOY_13, 0),
51 MESON_PIN(GPIOY_14, 0),
52
53 MESON_PIN(GPIODV_9, 0),
54 MESON_PIN(GPIODV_24, 0),
55 MESON_PIN(GPIODV_25, 0),
56 MESON_PIN(GPIODV_26, 0),
57 MESON_PIN(GPIODV_27, 0),
58 MESON_PIN(GPIODV_28, 0),
59 MESON_PIN(GPIODV_29, 0),
60
61 MESON_PIN(GPIOH_0, 0),
62 MESON_PIN(GPIOH_1, 0),
63 MESON_PIN(GPIOH_2, 0),
64 MESON_PIN(GPIOH_3, 0),
65 MESON_PIN(GPIOH_4, 0),
66 MESON_PIN(GPIOH_5, 0),
67 MESON_PIN(GPIOH_6, 0),
68 MESON_PIN(GPIOH_7, 0),
69 MESON_PIN(GPIOH_8, 0),
70 MESON_PIN(GPIOH_9, 0),
71
72 MESON_PIN(CARD_0, 0),
73 MESON_PIN(CARD_1, 0),
74 MESON_PIN(CARD_2, 0),
75 MESON_PIN(CARD_3, 0),
76 MESON_PIN(CARD_4, 0),
77 MESON_PIN(CARD_5, 0),
78 MESON_PIN(CARD_6, 0),
79
80 MESON_PIN(BOOT_0, 0),
81 MESON_PIN(BOOT_1, 0),
82 MESON_PIN(BOOT_2, 0),
83 MESON_PIN(BOOT_3, 0),
84 MESON_PIN(BOOT_4, 0),
85 MESON_PIN(BOOT_5, 0),
86 MESON_PIN(BOOT_6, 0),
87 MESON_PIN(BOOT_7, 0),
88 MESON_PIN(BOOT_8, 0),
89 MESON_PIN(BOOT_9, 0),
90 MESON_PIN(BOOT_10, 0),
91 MESON_PIN(BOOT_11, 0),
92 MESON_PIN(BOOT_12, 0),
93 MESON_PIN(BOOT_13, 0),
94 MESON_PIN(BOOT_14, 0),
95 MESON_PIN(BOOT_15, 0),
96 MESON_PIN(BOOT_16, 0),
97 MESON_PIN(BOOT_17, 0),
98 MESON_PIN(BOOT_18, 0),
99
100 MESON_PIN(DIF_0_P, 0),
101 MESON_PIN(DIF_0_N, 0),
102 MESON_PIN(DIF_1_P, 0),
103 MESON_PIN(DIF_1_N, 0),
104 MESON_PIN(DIF_2_P, 0),
105 MESON_PIN(DIF_2_N, 0),
106 MESON_PIN(DIF_3_P, 0),
107 MESON_PIN(DIF_3_N, 0),
108 MESON_PIN(DIF_4_P, 0),
109 MESON_PIN(DIF_4_N, 0),
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]110};
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]111
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]112static const struct pinctrl_pin_desc meson8b_aobus_pins[] = {
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]113 MESON_PIN(GPIOAO_0, AO_OFF),
114 MESON_PIN(GPIOAO_1, AO_OFF),
115 MESON_PIN(GPIOAO_2, AO_OFF),
116 MESON_PIN(GPIOAO_3, AO_OFF),
117 MESON_PIN(GPIOAO_4, AO_OFF),
118 MESON_PIN(GPIOAO_5, AO_OFF),
119 MESON_PIN(GPIOAO_6, AO_OFF),
120 MESON_PIN(GPIOAO_7, AO_OFF),
121 MESON_PIN(GPIOAO_8, AO_OFF),
122 MESON_PIN(GPIOAO_9, AO_OFF),
123 MESON_PIN(GPIOAO_10, AO_OFF),
124 MESON_PIN(GPIOAO_11, AO_OFF),
125 MESON_PIN(GPIOAO_12, AO_OFF),
126 MESON_PIN(GPIOAO_13, AO_OFF),
127 MESON_PIN(GPIO_BSD_EN, AO_OFF),
128 MESON_PIN(GPIO_TEST_N, AO_OFF),
129};
130
131/* bank X */
132static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) };
133static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) };
134static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) };
135static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) };
136static const unsigned int sdxc_d0_0_a_pins[] = { PIN(GPIOX_4, 0) };
137static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0),
138 PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) };
139static const unsigned int sdxc_d13_0_a_pins[] = { PIN(GPIOX_5, 0), PIN(GPIOX_6, 0),
140 PIN(GPIOX_7, 0) };
141static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) };
142static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
143static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) };
144static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) };
145static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) };
146static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) };
147static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) };
148static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) };
149
150static const unsigned int sdxc_d0_1_a_pins[] = { PIN(GPIOX_0, 0) };
151static const unsigned int sdxc_d13_1_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0),
152 PIN(GPIOX_3, 0) };
153static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) };
154static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) };
155static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) };
156static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) };
157static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) };
158static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
159static const unsigned int pwm_vs_0_pins[] = { PIN(GPIOX_10, 0) };
160static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) };
161static const unsigned int pwm_vs_1_pins[] = { PIN(GPIOX_11, 0) };
162
163static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_4, 0) };
164static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_5, 0) };
165static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_6, 0) };
166static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_7, 0) };
167static const unsigned int uart_tx_b1_pins[] = { PIN(GPIOX_8, 0) };
168static const unsigned int uart_rx_b1_pins[] = { PIN(GPIOX_9, 0) };
169static const unsigned int uart_cts_b1_pins[] = { PIN(GPIOX_10, 0) };
170static const unsigned int uart_rts_b1_pins[] = { PIN(GPIOX_20, 0) };
171
172static const unsigned int iso7816_0_clk_pins[] = { PIN(GPIOX_6, 0) };
173static const unsigned int iso7816_0_data_pins[] = { PIN(GPIOX_7, 0) };
174static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOX_8, 0) };
175static const unsigned int spi_miso_0_pins[] = { PIN(GPIOX_9, 0) };
176static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOX_10, 0) };
177static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) };
178static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) };
179static const unsigned int iso7816_1_clk_pins[] = { PIN(GPIOX_18, 0) };
180static const unsigned int iso7816_1_data_pins[] = { PIN(GPIOX_19, 0) };
181static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOX_20, 0) };
182
183static const unsigned int tsin_clk_b_pins[] = { PIN(GPIOX_8, 0) };
184static const unsigned int tsin_sop_b_pins[] = { PIN(GPIOX_9, 0) };
185static const unsigned int tsin_d0_b_pins[] = { PIN(GPIOX_10, 0) };
186static const unsigned int pwm_b_pins[] = { PIN(GPIOX_11, 0) };
187static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) };
188static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) };
189static const unsigned int tsin_d_valid_b_pins[] = { PIN(GPIOX_20, 0) };
190
191/* bank Y */
192static const unsigned int tsin_d_valid_a_pins[] = { PIN(GPIOY_0, 0) };
193static const unsigned int tsin_sop_a_pins[] = { PIN(GPIOY_1, 0) };
194static const unsigned int tsin_d17_a_pins[] = { PIN(GPIOY_6, 0), PIN(GPIOY_7, 0),
195 PIN(GPIOY_10, 0), PIN(GPIOY_11, 0),
196 PIN(GPIOY_12, 0), PIN(GPIOY_13, 0),
197 PIN(GPIOY_14, 0) };
198static const unsigned int tsin_clk_a_pins[] = { PIN(GPIOY_8, 0) };
199static const unsigned int tsin_d0_a_pins[] = { PIN(GPIOY_9, 0) };
200
201static const unsigned int spdif_out_0_pins[] = { PIN(GPIOY_3, 0) };
202
203static const unsigned int xtal_24m_pins[] = { PIN(GPIOY_3, 0) };
204static const unsigned int iso7816_2_clk_pins[] = { PIN(GPIOY_13, 0) };
205static const unsigned int iso7816_2_data_pins[] = { PIN(GPIOY_14, 0) };
206
207/* bank DV */
208static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) };
209static const unsigned int pwm_c0_pins[] = { PIN(GPIODV_29, 0) };
210
211static const unsigned int pwm_vs_2_pins[] = { PIN(GPIODV_9, 0) };
212static const unsigned int pwm_vs_3_pins[] = { PIN(GPIODV_28, 0) };
213static const unsigned int pwm_vs_4_pins[] = { PIN(GPIODV_29, 0) };
214
215static const unsigned int xtal24_out_pins[] = { PIN(GPIODV_29, 0) };
216
217static const unsigned int uart_tx_c_pins[] = { PIN(GPIODV_24, 0) };
218static const unsigned int uart_rx_c_pins[] = { PIN(GPIODV_25, 0) };
219static const unsigned int uart_cts_c_pins[] = { PIN(GPIODV_26, 0) };
220static const unsigned int uart_rts_c_pins[] = { PIN(GPIODV_27, 0) };
221
222static const unsigned int pwm_c1_pins[] = { PIN(GPIODV_9, 0) };
223
224static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, 0) };
225static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, 0) };
226static const unsigned int i2c_sda_b0_pins[] = { PIN(GPIODV_26, 0) };
227static const unsigned int i2c_sck_b0_pins[] = { PIN(GPIODV_27, 0) };
228static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIODV_28, 0) };
229static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIODV_29, 0) };
230
231/* bank H */
232static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) };
233static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) };
234static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) };
235static const unsigned int hdmi_cec_0_pins[] = { PIN(GPIOH_3, 0) };
236static const unsigned int eth_txd1_0_pins[] = { PIN(GPIOH_5, 0) };
237static const unsigned int eth_txd0_0_pins[] = { PIN(GPIOH_6, 0) };
238static const unsigned int clk_24m_out_pins[] = { PIN(GPIOH_9, 0) };
239
240static const unsigned int spi_ss1_pins[] = { PIN(GPIOH_0, 0) };
241static const unsigned int spi_ss2_pins[] = { PIN(GPIOH_1, 0) };
242static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOH_3, 0) };
243static const unsigned int spi_miso_1_pins[] = { PIN(GPIOH_4, 0) };
244static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOH_5, 0) };
245static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOH_6, 0) };
246
247static const unsigned int eth_txd3_pins[] = { PIN(GPIOH_7, 0) };
248static const unsigned int eth_txd2_pins[] = { PIN(GPIOH_8, 0) };
249static const unsigned int eth_tx_clk_pins[] = { PIN(GPIOH_9, 0) };
250
251static const unsigned int i2c_sda_b1_pins[] = { PIN(GPIOH_3, 0) };
252static const unsigned int i2c_sck_b1_pins[] = { PIN(GPIOH_4, 0) };
253static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOH_5, 0) };
254static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOH_6, 0) };
255static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) };
256static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) };
257
258/* bank BOOT */
259static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0),
260 PIN(BOOT_2, 0), PIN(BOOT_3, 0),
261 PIN(BOOT_4, 0), PIN(BOOT_5, 0),
262 PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
263static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) };
264static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) };
265static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) };
266static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) };
267static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) };
268static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) };
269static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) };
270static const unsigned int nand_dqs_0_pins[] = { PIN(BOOT_15, 0) };
271static const unsigned int nand_dqs_1_pins[] = { PIN(BOOT_18, 0) };
272
273static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)};
274static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0),
275 PIN(BOOT_3, 0) };
276static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0),
277 PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
278static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_8, 0) };
279static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_10, 0) };
280static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) };
281static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) };
282static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) };
283static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) };
284
285static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) };
286static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) };
287static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) };
288static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) };
289static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_8, 0) };
290static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_10, 0) };
291
292/* bank CARD */
293static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) };
294static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) };
295static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) };
296static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) };
297static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) };
298static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) };
299
300static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0),
301 PIN(CARD_5, 0) };
302static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) };
303static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) };
304static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) };
305
306/* bank AO */
307static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) };
308static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) };
309static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) };
310static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) };
311static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
312static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
313static const unsigned int clk_32k_in_out_pins[] = { PIN(GPIOAO_6, AO_OFF) };
314static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) };
315static const unsigned int hdmi_cec_1_pins[] = { PIN(GPIOAO_12, AO_OFF) };
316static const unsigned int ir_blaster_pins[] = { PIN(GPIOAO_13, AO_OFF) };
317
318static const unsigned int pwm_c2_pins[] = { PIN(GPIOAO_3, AO_OFF) };
319static const unsigned int i2c_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
320static const unsigned int i2c_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
321static const unsigned int ir_remote_out_pins[] = { PIN(GPIOAO_7, AO_OFF) };
322static const unsigned int i2s_am_clk_out_pins[] = { PIN(GPIOAO_8, AO_OFF) };
323static const unsigned int i2s_ao_clk_out_pins[] = { PIN(GPIOAO_9, AO_OFF) };
324static const unsigned int i2s_lr_clk_out_pins[] = { PIN(GPIOAO_10, AO_OFF) };
325static const unsigned int i2s_out_01_pins[] = { PIN(GPIOAO_11, AO_OFF) };
326
327static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) };
328static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) };
329static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, AO_OFF) };
330static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, AO_OFF) };
331static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) };
332static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) };
333static const unsigned int spdif_out_1_pins[] = { PIN(GPIOAO_6, AO_OFF) };
334
335static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOAO_6, AO_OFF) };
336static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOAO_9, AO_OFF) };
337static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOAO_10, AO_OFF) };
338
339/* bank DIF */
340static const unsigned int eth_rxd1_pins[] = { PIN(DIF_0_P, 0) };
341static const unsigned int eth_rxd0_pins[] = { PIN(DIF_0_N, 0) };
342static const unsigned int eth_rx_dv_pins[] = { PIN(DIF_1_P, 0) };
343static const unsigned int eth_rx_clk_pins[] = { PIN(DIF_1_N, 0) };
344static const unsigned int eth_txd0_1_pins[] = { PIN(DIF_2_P, 0) };
345static const unsigned int eth_txd1_1_pins[] = { PIN(DIF_2_N, 0) };
346static const unsigned int eth_tx_en_pins[] = { PIN(DIF_3_P, 0) };
347static const unsigned int eth_ref_clk_pins[] = { PIN(DIF_3_N, 0) };
348static const unsigned int eth_mdc_pins[] = { PIN(DIF_4_P, 0) };
349static const unsigned int eth_mdio_en_pins[] = { PIN(DIF_4_N, 0) };
350
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]351static struct meson_pmx_group meson8b_cbus_groups[] = {
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]352 GPIO_GROUP(GPIOX_0, 0),
353 GPIO_GROUP(GPIOX_1, 0),
354 GPIO_GROUP(GPIOX_2, 0),
355 GPIO_GROUP(GPIOX_3, 0),
356 GPIO_GROUP(GPIOX_4, 0),
357 GPIO_GROUP(GPIOX_5, 0),
358 GPIO_GROUP(GPIOX_6, 0),
359 GPIO_GROUP(GPIOX_7, 0),
360 GPIO_GROUP(GPIOX_8, 0),
361 GPIO_GROUP(GPIOX_9, 0),
362 GPIO_GROUP(GPIOX_10, 0),
363 GPIO_GROUP(GPIOX_11, 0),
364 GPIO_GROUP(GPIOX_16, 0),
365 GPIO_GROUP(GPIOX_17, 0),
366 GPIO_GROUP(GPIOX_18, 0),
367 GPIO_GROUP(GPIOX_19, 0),
368 GPIO_GROUP(GPIOX_20, 0),
369 GPIO_GROUP(GPIOX_21, 0),
370
371 GPIO_GROUP(GPIOY_0, 0),
372 GPIO_GROUP(GPIOY_1, 0),
373 GPIO_GROUP(GPIOY_3, 0),
374 GPIO_GROUP(GPIOY_6, 0),
375 GPIO_GROUP(GPIOY_7, 0),
376 GPIO_GROUP(GPIOY_8, 0),
377 GPIO_GROUP(GPIOY_9, 0),
378 GPIO_GROUP(GPIOY_10, 0),
379 GPIO_GROUP(GPIOY_11, 0),
380 GPIO_GROUP(GPIOY_12, 0),
381 GPIO_GROUP(GPIOY_13, 0),
382 GPIO_GROUP(GPIOY_14, 0),
383
384 GPIO_GROUP(GPIODV_9, 0),
385 GPIO_GROUP(GPIODV_24, 0),
386 GPIO_GROUP(GPIODV_25, 0),
387 GPIO_GROUP(GPIODV_26, 0),
388 GPIO_GROUP(GPIODV_27, 0),
389 GPIO_GROUP(GPIODV_28, 0),
390 GPIO_GROUP(GPIODV_29, 0),
391
392 GPIO_GROUP(GPIOH_0, 0),
393 GPIO_GROUP(GPIOH_1, 0),
394 GPIO_GROUP(GPIOH_2, 0),
395 GPIO_GROUP(GPIOH_3, 0),
396 GPIO_GROUP(GPIOH_4, 0),
397 GPIO_GROUP(GPIOH_5, 0),
398 GPIO_GROUP(GPIOH_6, 0),
399 GPIO_GROUP(GPIOH_7, 0),
400 GPIO_GROUP(GPIOH_8, 0),
401 GPIO_GROUP(GPIOH_9, 0),
402
403 GPIO_GROUP(DIF_0_P, 0),
404 GPIO_GROUP(DIF_0_N, 0),
405 GPIO_GROUP(DIF_1_P, 0),
406 GPIO_GROUP(DIF_1_N, 0),
407 GPIO_GROUP(DIF_2_P, 0),
408 GPIO_GROUP(DIF_2_N, 0),
409 GPIO_GROUP(DIF_3_P, 0),
410 GPIO_GROUP(DIF_3_N, 0),
411 GPIO_GROUP(DIF_4_P, 0),
412 GPIO_GROUP(DIF_4_N, 0),
413
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]414 /* bank X */
415 GROUP(sd_d0_a, 8, 5),
416 GROUP(sd_d1_a, 8, 4),
417 GROUP(sd_d2_a, 8, 3),
418 GROUP(sd_d3_a, 8, 2),
419 GROUP(sdxc_d0_0_a, 5, 29),
420 GROUP(sdxc_d47_a, 5, 12),
421 GROUP(sdxc_d13_0_a, 5, 28),
422 GROUP(sd_clk_a, 8, 1),
423 GROUP(sd_cmd_a, 8, 0),
424 GROUP(xtal_32k_out, 3, 22),
425 GROUP(xtal_24m_out, 3, 20),
426 GROUP(uart_tx_b0, 4, 9),
427 GROUP(uart_rx_b0, 4, 8),
428 GROUP(uart_cts_b0, 4, 7),
429 GROUP(uart_rts_b0, 4, 6),
430 GROUP(sdxc_d0_1_a, 5, 14),
431 GROUP(sdxc_d13_1_a, 5, 13),
432 GROUP(pcm_out_a, 3, 30),
433 GROUP(pcm_in_a, 3, 29),
434 GROUP(pcm_fs_a, 3, 28),
435 GROUP(pcm_clk_a, 3, 27),
436 GROUP(sdxc_clk_a, 5, 11),
437 GROUP(sdxc_cmd_a, 5, 10),
438 GROUP(pwm_vs_0, 7, 31),
439 GROUP(pwm_e, 9, 19),
440 GROUP(pwm_vs_1, 7, 30),
441 GROUP(uart_tx_a, 4, 17),
442 GROUP(uart_rx_a, 4, 16),
443 GROUP(uart_cts_a, 4, 15),
444 GROUP(uart_rts_a, 4, 14),
445 GROUP(uart_tx_b1, 6, 19),
446 GROUP(uart_rx_b1, 6, 18),
447 GROUP(uart_cts_b1, 6, 17),
448 GROUP(uart_rts_b1, 6, 16),
449 GROUP(iso7816_0_clk, 5, 9),
450 GROUP(iso7816_0_data, 5, 8),
451 GROUP(spi_sclk_0, 4, 22),
452 GROUP(spi_miso_0, 4, 24),
453 GROUP(spi_mosi_0, 4, 23),
454 GROUP(iso7816_det, 4, 21),
455 GROUP(iso7816_reset, 4, 20),
456 GROUP(iso7816_1_clk, 4, 19),
457 GROUP(iso7816_1_data, 4, 18),
458 GROUP(spi_ss0_0, 4, 25),
459 GROUP(tsin_clk_b, 3, 6),
460 GROUP(tsin_sop_b, 3, 7),
461 GROUP(tsin_d0_b, 3, 8),
462 GROUP(pwm_b, 2, 3),
463 GROUP(i2c_sda_d0, 4, 5),
464 GROUP(i2c_sck_d0, 4, 4),
465 GROUP(tsin_d_valid_b, 3, 9),
466
467 /* bank Y */
468 GROUP(tsin_d_valid_a, 3, 2),
469 GROUP(tsin_sop_a, 3, 1),
470 GROUP(tsin_d17_a, 3, 5),
471 GROUP(tsin_clk_a, 3, 0),
472 GROUP(tsin_d0_a, 3, 4),
473 GROUP(spdif_out_0, 1, 7),
474 GROUP(xtal_24m, 3, 18),
475 GROUP(iso7816_2_clk, 5, 7),
476 GROUP(iso7816_2_data, 5, 6),
477
478 /* bank DV */
479 GROUP(pwm_d, 3, 26),
480 GROUP(pwm_c0, 3, 25),
481 GROUP(pwm_vs_2, 7, 28),
482 GROUP(pwm_vs_3, 7, 27),
483 GROUP(pwm_vs_4, 7, 26),
484 GROUP(xtal24_out, 7, 25),
485 GROUP(uart_tx_c, 6, 23),
486 GROUP(uart_rx_c, 6, 22),
487 GROUP(uart_cts_c, 6, 21),
488 GROUP(uart_rts_c, 6, 20),
489 GROUP(pwm_c1, 3, 24),
490 GROUP(i2c_sda_a, 9, 31),
491 GROUP(i2c_sck_a, 9, 30),
492 GROUP(i2c_sda_b0, 9, 29),
493 GROUP(i2c_sck_b0, 9, 28),
494 GROUP(i2c_sda_c0, 9, 27),
495 GROUP(i2c_sck_c0, 9, 26),
496
497 /* bank H */
498 GROUP(hdmi_hpd, 1, 26),
499 GROUP(hdmi_sda, 1, 25),
500 GROUP(hdmi_scl, 1, 24),
501 GROUP(hdmi_cec_0, 1, 23),
502 GROUP(eth_txd1_0, 7, 21),
503 GROUP(eth_txd0_0, 7, 20),
504 GROUP(clk_24m_out, 4, 1),
505 GROUP(spi_ss1, 8, 11),
506 GROUP(spi_ss2, 8, 12),
507 GROUP(spi_ss0_1, 9, 13),
508 GROUP(spi_miso_1, 9, 12),
509 GROUP(spi_mosi_1, 9, 11),
510 GROUP(spi_sclk_1, 9, 10),
511 GROUP(eth_txd3, 6, 13),
512 GROUP(eth_txd2, 6, 12),
513 GROUP(eth_tx_clk, 6, 11),
514 GROUP(i2c_sda_b1, 5, 27),
515 GROUP(i2c_sck_b1, 5, 26),
516 GROUP(i2c_sda_c1, 5, 25),
517 GROUP(i2c_sck_c1, 5, 24),
518 GROUP(i2c_sda_d1, 4, 3),
519 GROUP(i2c_sck_d1, 4, 2),
520
521 /* bank BOOT */
522 GROUP(nand_io, 2, 26),
523 GROUP(nand_io_ce0, 2, 25),
524 GROUP(nand_io_ce1, 2, 24),
525 GROUP(nand_io_rb0, 2, 17),
526 GROUP(nand_ale, 2, 21),
527 GROUP(nand_cle, 2, 20),
528 GROUP(nand_wen_clk, 2, 19),
529 GROUP(nand_ren_clk, 2, 18),
530 GROUP(nand_dqs_0, 2, 27),
531 GROUP(nand_dqs_1, 2, 28),
532 GROUP(sdxc_d0_c, 4, 30),
533 GROUP(sdxc_d13_c, 4, 29),
534 GROUP(sdxc_d47_c, 4, 28),
535 GROUP(sdxc_clk_c, 7, 19),
536 GROUP(sdxc_cmd_c, 7, 18),
537 GROUP(nor_d, 5, 1),
538 GROUP(nor_q, 5, 3),
539 GROUP(nor_c, 5, 2),
540 GROUP(nor_cs, 5, 0),
541 GROUP(sd_d0_c, 6, 29),
542 GROUP(sd_d1_c, 6, 28),
543 GROUP(sd_d2_c, 6, 27),
544 GROUP(sd_d3_c, 6, 26),
545 GROUP(sd_cmd_c, 6, 30),
546 GROUP(sd_clk_c, 6, 31),
547
548 /* bank CARD */
549 GROUP(sd_d1_b, 2, 14),
550 GROUP(sd_d0_b, 2, 15),
551 GROUP(sd_clk_b, 2, 11),
552 GROUP(sd_cmd_b, 2, 10),
553 GROUP(sd_d3_b, 2, 12),
554 GROUP(sd_d2_b, 2, 13),
555 GROUP(sdxc_d13_b, 2, 6),
556 GROUP(sdxc_d0_b, 2, 7),
557 GROUP(sdxc_clk_b, 2, 5),
558 GROUP(sdxc_cmd_b, 2, 4),
559
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]560 /* bank DIF */
561 GROUP(eth_rxd1, 6, 0),
562 GROUP(eth_rxd0, 6, 1),
563 GROUP(eth_rx_dv, 6, 2),
564 GROUP(eth_rx_clk, 6, 3),
565 GROUP(eth_txd0_1, 6, 4),
566 GROUP(eth_txd1_1, 6, 5),
Alexander Müllerd6d5c122016-05-08 19:59:49 +0200[diff] [blame]567 GROUP(eth_tx_en, 6, 6),
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]568 GROUP(eth_ref_clk, 6, 8),
569 GROUP(eth_mdc, 6, 9),
570 GROUP(eth_mdio_en, 6, 10),
571};
572
573static struct meson_pmx_group meson8b_aobus_groups[] = {
574 GPIO_GROUP(GPIOAO_0, AO_OFF),
575 GPIO_GROUP(GPIOAO_1, AO_OFF),
576 GPIO_GROUP(GPIOAO_2, AO_OFF),
577 GPIO_GROUP(GPIOAO_3, AO_OFF),
578 GPIO_GROUP(GPIOAO_4, AO_OFF),
579 GPIO_GROUP(GPIOAO_5, AO_OFF),
580 GPIO_GROUP(GPIOAO_6, AO_OFF),
581 GPIO_GROUP(GPIOAO_7, AO_OFF),
582 GPIO_GROUP(GPIOAO_8, AO_OFF),
583 GPIO_GROUP(GPIOAO_9, AO_OFF),
584 GPIO_GROUP(GPIOAO_10, AO_OFF),
585 GPIO_GROUP(GPIOAO_11, AO_OFF),
586 GPIO_GROUP(GPIOAO_12, AO_OFF),
587 GPIO_GROUP(GPIOAO_13, AO_OFF),
588 GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
589 GPIO_GROUP(GPIO_TEST_N, AO_OFF),
590
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]591 /* bank AO */
592 GROUP(uart_tx_ao_a, 0, 12),
593 GROUP(uart_rx_ao_a, 0, 11),
594 GROUP(uart_cts_ao_a, 0, 10),
595 GROUP(uart_rts_ao_a, 0, 9),
596 GROUP(i2c_mst_sck_ao, 0, 6),
597 GROUP(i2c_mst_sda_ao, 0, 5),
598 GROUP(clk_32k_in_out, 0, 18),
599 GROUP(remote_input, 0, 0),
600 GROUP(hdmi_cec_1, 0, 17),
601 GROUP(ir_blaster, 0, 31),
602 GROUP(pwm_c2, 0, 22),
603 GROUP(i2c_sck_ao, 0, 2),
604 GROUP(i2c_sda_ao, 0, 1),
605 GROUP(ir_remote_out, 0, 21),
606 GROUP(i2s_am_clk_out, 0, 30),
607 GROUP(i2s_ao_clk_out, 0, 29),
608 GROUP(i2s_lr_clk_out, 0, 28),
609 GROUP(i2s_out_01, 0, 27),
610 GROUP(uart_tx_ao_b0, 0, 26),
611 GROUP(uart_rx_ao_b0, 0, 25),
612 GROUP(uart_cts_ao_b, 0, 8),
613 GROUP(uart_rts_ao_b, 0, 7),
614 GROUP(uart_tx_ao_b1, 0, 24),
615 GROUP(uart_rx_ao_b1, 0, 23),
616 GROUP(spdif_out_1, 0, 16),
617 GROUP(i2s_in_ch01, 0, 13),
618 GROUP(i2s_ao_clk_in, 0, 15),
619 GROUP(i2s_lr_clk_in, 0, 14),
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]620};
621
622static const char * const gpio_groups[] = {
623 "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
624 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
625 "GPIOX_10", "GPIOX_11", "GPIOX_16", "GPIOX_17", "GPIOX_18",
626 "GPIOX_19", "GPIOX_20", "GPIOX_21",
627
628 "GPIOY_0", "GPIOY_1", "GPIOY_3", "GPIOY_6", "GPIOY_7",
629 "GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11", "GPIOY_12",
630 "GPIOY_13", "GPIOY_14",
631
632 "GPIODV_9", "GPIODV_24", "GPIODV_25", "GPIODV_26",
633 "GPIODV_27", "GPIODV_28", "GPIODV_29",
634
635 "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
636 "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
637
638 "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
639 "CARD_5", "CARD_6",
640
641 "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
642 "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
643 "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
644 "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
645
646 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
647 "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
648 "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
649 "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N",
650
651 "DIF_0_P", "DIF_0_N", "DIF_1_P", "DIF_1_N",
652 "DIF_2_P", "DIF_2_N", "DIF_3_P", "DIF_3_N",
653 "DIF_4_P", "DIF_4_N"
654};
655
656static const char * const sd_a_groups[] = {
657 "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a",
658 "sd_cmd_a"
659};
660
661static const char * const sdxc_a_groups[] = {
662 "sdxc_d0_0_a", "sdxc_d13_0_a", "sdxc_d47_a", "sdxc_clk_a",
663 "sdxc_cmd_a", "sdxc_d0_1_a", "sdxc_d0_13_1_a"
664};
665
666static const char * const pcm_a_groups[] = {
667 "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
668};
669
670static const char * const uart_a_groups[] = {
671 "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a"
672};
673
674static const char * const uart_b_groups[] = {
675 "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
676 "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
677};
678
679static const char * const iso7816_groups[] = {
680 "iso7816_det", "iso7816_reset", "iso7816_0_clk", "iso7816_0_data",
681 "iso7816_1_clk", "iso7816_1_data", "iso7816_2_clk", "iso7816_2_data"
682};
683
684static const char * const i2c_d_groups[] = {
685 "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
686};
687
688static const char * const xtal_groups[] = {
689 "xtal_32k_out", "xtal_24m_out", "xtal_24m", "xtal24_out"
690};
691
692static const char * const uart_c_groups[] = {
693 "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
694};
695
696static const char * const i2c_c_groups[] = {
697 "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
698};
699
700static const char * const hdmi_groups[] = {
Carlo Caioneac1afc42016-03-01 23:04:33 +0100[diff] [blame]701 "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0"
702};
703
704static const char * const hdmi_cec_groups[] = {
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]705 "hdmi_cec_1"
706};
707
708static const char * const spi_groups[] = {
709 "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
710 "spi_ss0_1", "spi_ss1", "spi_sclk_1", "spi_mosi_1",
711 "spi_miso_1", "spi_ss2"
712};
713
714static const char * const ethernet_groups[] = {
715 "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1",
716 "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv",
717 "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk",
718 "eth_txd2", "eth_txd3"
719};
720
721static const char * const i2c_a_groups[] = {
722 "i2c_sda_a", "i2c_sck_a",
723};
724
725static const char * const i2c_b_groups[] = {
726 "i2c_sda_b0", "i2c_sck_b0", "i2c_sda_b1", "i2c_sck_b1"
727};
728
729static const char * const sd_c_groups[] = {
730 "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
731 "sd_cmd_c", "sd_clk_c"
732};
733
734static const char * const sdxc_c_groups[] = {
735 "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
736 "sdxc_clk_c"
737};
738
739static const char * const nand_groups[] = {
740 "nand_io", "nand_io_ce0", "nand_io_ce1",
741 "nand_io_rb0", "nand_ale", "nand_cle",
742 "nand_wen_clk", "nand_ren_clk", "nand_dqs0",
743 "nand_dqs1"
744};
745
746static const char * const nor_groups[] = {
747 "nor_d", "nor_q", "nor_c", "nor_cs"
748};
749
750static const char * const sd_b_groups[] = {
751 "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
752 "sd_d3_b", "sd_d2_b"
753};
754
755static const char * const sdxc_b_groups[] = {
756 "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
757};
758
759static const char * const uart_ao_groups[] = {
760 "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
761};
762
763static const char * const remote_groups[] = {
764 "remote_input", "ir_blaster", "ir_remote_out"
765};
766
767static const char * const i2c_slave_ao_groups[] = {
768 "i2c_sck_ao", "i2c_sda_ao"
769};
770
771static const char * const uart_ao_b_groups[] = {
772 "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1",
773 "uart_cts_ao_b", "uart_rts_ao_b"
774};
775
776static const char * const i2c_mst_ao_groups[] = {
777 "i2c_mst_sck_ao", "i2c_mst_sda_ao"
778};
779
Carlo Caioneac1afc42016-03-01 23:04:33 +0100[diff] [blame]780static const char * const clk_24m_groups[] = {
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]781 "clk_24m_out"
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]782};
783
Carlo Caioneac1afc42016-03-01 23:04:33 +0100[diff] [blame]784static const char * const clk_32k_groups[] = {
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]785 "clk_32k_in_out"
Carlo Caioneac1afc42016-03-01 23:04:33 +0100[diff] [blame]786};
787
788static const char * const spdif_0_groups[] = {
789 "spdif_out_0"
790};
791
792static const char * const spdif_1_groups[] = {
793 "spdif_out_1"
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]794};
795
796static const char * const i2s_groups[] = {
797 "i2s_am_clk_out", "i2s_ao_clk_out", "i2s_lr_clk_out",
798 "i2s_out_01", "i2s_in_ch01", "i2s_ao_clk_in",
799 "i2s_lr_clk_in"
800};
801
802static const char * const pwm_b_groups[] = {
803 "pwm_b"
804};
805
806static const char * const pwm_c_groups[] = {
Carlo Caioneac1afc42016-03-01 23:04:33 +0100[diff] [blame]807 "pwm_c0", "pwm_c1"
808};
809
810static const char * const pwm_c_ao_groups[] = {
811 "pwm_c2"
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]812};
813
814static const char * const pwm_d_groups[] = {
815 "pwm_d"
816};
817
818static const char * const pwm_e_groups[] = {
819 "pwm_e"
820};
821
822static const char * const pwm_vs_groups[] = {
823 "pwm_vs_0", "pwm_vs_1", "pwm_vs_2",
824 "pwm_vs_3", "pwm_vs_4"
825};
826
827static const char * const tsin_a_groups[] = {
828 "tsin_d0_a", "tsin_d17_a", "tsin_clk_a", "tsin_sop_a",
829 "tsin_d_valid_a"
830};
831
832static const char * const tsin_b_groups[] = {
833 "tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b"
834};
835
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]836static struct meson_pmx_func meson8b_cbus_functions[] = {
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]837 FUNCTION(gpio),
838 FUNCTION(sd_a),
839 FUNCTION(sdxc_a),
840 FUNCTION(pcm_a),
841 FUNCTION(uart_a),
842 FUNCTION(uart_b),
843 FUNCTION(iso7816),
844 FUNCTION(i2c_d),
845 FUNCTION(xtal),
846 FUNCTION(uart_c),
847 FUNCTION(i2c_c),
848 FUNCTION(hdmi),
849 FUNCTION(spi),
850 FUNCTION(ethernet),
851 FUNCTION(i2c_a),
852 FUNCTION(i2c_b),
853 FUNCTION(sd_c),
854 FUNCTION(sdxc_c),
855 FUNCTION(nand),
856 FUNCTION(nor),
857 FUNCTION(sd_b),
858 FUNCTION(sdxc_b),
Carlo Caioneac1afc42016-03-01 23:04:33 +0100[diff] [blame]859 FUNCTION(spdif_0),
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]860 FUNCTION(pwm_b),
861 FUNCTION(pwm_c),
862 FUNCTION(pwm_d),
863 FUNCTION(pwm_e),
864 FUNCTION(pwm_vs),
865 FUNCTION(tsin_a),
866 FUNCTION(tsin_b),
Carlo Caioneac1afc42016-03-01 23:04:33 +0100[diff] [blame]867 FUNCTION(clk_24m),
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]868};
869
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]870static struct meson_pmx_func meson8b_aobus_functions[] = {
871 FUNCTION(uart_ao),
872 FUNCTION(uart_ao_b),
873 FUNCTION(i2c_slave_ao),
874 FUNCTION(i2c_mst_ao),
875 FUNCTION(i2s),
876 FUNCTION(remote),
877 FUNCTION(clk_32k),
878 FUNCTION(pwm_c_ao),
879 FUNCTION(spdif_1),
880 FUNCTION(hdmi_cec),
881};
882
883static struct meson_bank meson8b_cbus_banks[] = {
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]884 /* name first last pullen pull dir out in */
885 BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
886 BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_14, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
887 BANK("DV", PIN(GPIODV_9, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
888 BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
889 BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
890 BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
891 BANK("DIF", PIN(DIF_0_P, 0), PIN(DIF_4_N, 0), 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
892};
893
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]894static struct meson_bank meson8b_aobus_banks[] = {
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]895 /* name first last pullen pull dir out in */
896 BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
897};
898
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]899static struct meson_domain_data meson8b_cbus_domain_data = {
900 .name = "cbus-banks",
901 .banks = meson8b_cbus_banks,
902 .num_banks = ARRAY_SIZE(meson8b_cbus_banks),
903 .pin_base = 0,
904 .num_pins = 130,
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]905};
906
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]907static struct meson_domain_data meson8b_aobus_domain_data = {
908 .name = "aobus-banks",
909 .banks = meson8b_aobus_banks,
910 .num_banks = ARRAY_SIZE(meson8b_aobus_banks),
911 .pin_base = 130,
912 .num_pins = 16,
913};
914
915struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
916 .pins = meson8b_cbus_pins,
917 .groups = meson8b_cbus_groups,
918 .funcs = meson8b_cbus_functions,
919 .domain_data = &meson8b_cbus_domain_data,
920 .num_pins = ARRAY_SIZE(meson8b_cbus_pins),
921 .num_groups = ARRAY_SIZE(meson8b_cbus_groups),
922 .num_funcs = ARRAY_SIZE(meson8b_cbus_functions),
923};
924
925struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
926 .pins = meson8b_aobus_pins,
927 .groups = meson8b_aobus_groups,
928 .funcs = meson8b_aobus_functions,
929 .domain_data = &meson8b_aobus_domain_data,
930 .num_pins = ARRAY_SIZE(meson8b_aobus_pins),
931 .num_groups = ARRAY_SIZE(meson8b_aobus_groups),
932 .num_funcs = ARRAY_SIZE(meson8b_aobus_functions),
Carlo Caione0fefcb62015-03-29 12:56:42 +0200[diff] [blame]933};