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gerrit-public.fairphone.software / kernel / msm-4.19 / aa96a18d22dc7ad4dbc98cb0f4b2967a9fc979ca / . / arch / arm / mach-imx / clk-imx6q.c
blob: cab02d0a15d60d1c1bfe6e16157b386c0fb6b062 [file] [log] [blame]
Shawn Guo2acd1b62012-04-04 20:53:22 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/types.h>
15#include <linux/clk.h>
16#include <linux/clkdev.h>
17#include <linux/err.h>
18#include <linux/io.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22#include <mach/common.h>
23#include "clk.h"
24
25#define CCGR0 0x68
26#define CCGR1 0x6c
27#define CCGR2 0x70
28#define CCGR3 0x74
29#define CCGR4 0x78
30#define CCGR5 0x7c
31#define CCGR6 0x80
32#define CCGR7 0x84
33
34#define CLPCR 0x54
35#define BP_CLPCR_LPM 0
36#define BM_CLPCR_LPM (0x3 << 0)
37#define BM_CLPCR_BYPASS_PMIC_READY (0x1 << 2)
38#define BM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5)
39#define BM_CLPCR_SBYOS (0x1 << 6)
40#define BM_CLPCR_DIS_REF_OSC (0x1 << 7)
41#define BM_CLPCR_VSTBY (0x1 << 8)
42#define BP_CLPCR_STBY_COUNT 9
43#define BM_CLPCR_STBY_COUNT (0x3 << 9)
44#define BM_CLPCR_COSC_PWRDOWN (0x1 << 11)
45#define BM_CLPCR_WB_PER_AT_LPM (0x1 << 16)
46#define BM_CLPCR_WB_CORE_AT_LPM (0x1 << 17)
47#define BM_CLPCR_BYP_MMDC_CH0_LPM_HS (0x1 << 19)
48#define BM_CLPCR_BYP_MMDC_CH1_LPM_HS (0x1 << 21)
49#define BM_CLPCR_MASK_CORE0_WFI (0x1 << 22)
50#define BM_CLPCR_MASK_CORE1_WFI (0x1 << 23)
51#define BM_CLPCR_MASK_CORE2_WFI (0x1 << 24)
52#define BM_CLPCR_MASK_CORE3_WFI (0x1 << 25)
53#define BM_CLPCR_MASK_SCU_IDLE (0x1 << 26)
54#define BM_CLPCR_MASK_L2CC_IDLE (0x1 << 27)
55
56static void __iomem *ccm_base;
57
58void __init imx6q_clock_map_io(void) { }
59
60int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
61{
62 u32 val = readl_relaxed(ccm_base + CLPCR);
63
64 val &= ~BM_CLPCR_LPM;
65 switch (mode) {
66 case WAIT_CLOCKED:
67 break;
68 case WAIT_UNCLOCKED:
69 val |= 0x1 << BP_CLPCR_LPM;
70 break;
71 case STOP_POWER_ON:
72 val |= 0x2 << BP_CLPCR_LPM;
73 break;
74 case WAIT_UNCLOCKED_POWER_OFF:
75 val |= 0x1 << BP_CLPCR_LPM;
76 val &= ~BM_CLPCR_VSTBY;
77 val &= ~BM_CLPCR_SBYOS;
78 break;
79 case STOP_POWER_OFF:
80 val |= 0x2 << BP_CLPCR_LPM;
81 val |= 0x3 << BP_CLPCR_STBY_COUNT;
82 val |= BM_CLPCR_VSTBY;
83 val |= BM_CLPCR_SBYOS;
84 break;
85 default:
86 return -EINVAL;
87 }
88
89 writel_relaxed(val, ccm_base + CLPCR);
90
91 return 0;
92}
93
94static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
95static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
96static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
97static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", };
98static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
99static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
100static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "pll3_pfd1_540m", };
101static const char *audio_sels[] = { "pll4_audio", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
102static const char *gpu_axi_sels[] = { "axi", "ahb", };
103static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
104static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
105static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd9_720m", };
106static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
107static const char *ldb_di_sels[] = { "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
108static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
109static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
110static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
111static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
112static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
113static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", };
114static const char *pcie_axi_sels[] = { "axi", "ahb", };
115static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio", };
116static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
117static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
118static const char *emi_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
119static const char *vdo_axi_sels[] = { "axi", "ahb", };
120static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
121static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video",
122 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
123 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio", };
124
125static const char * const clks_init_on[] __initconst = {
126 "mmdc_ch0_axi", "mmdc_ch1_axi", "usboh3",
127};
128
129enum mx6q_clks {
130 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
131 pll3_pfd0_720m, pll3_pfd1_540m, pll3_pfd2_508m, pll3_pfd3_454m,
132 pll2_198m, pll3_120m, pll3_80m, pll3_60m, twd, step, pll1_sw,
133 periph_pre, periph2_pre, periph_clk2_sel, periph2_clk2_sel, axi_sel,
134 esai_sel, asrc_sel, spdif_sel, gpu2d_axi, gpu3d_axi, gpu2d_core_sel,
135 gpu3d_core_sel, gpu3d_shader_sel, ipu1_sel, ipu2_sel, ldb_di0_sel,
136 ldb_di1_sel, ipu1_di0_pre_sel, ipu1_di1_pre_sel, ipu2_di0_pre_sel,
137 ipu2_di1_pre_sel, ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel,
138 ipu2_di1_sel, hsi_tx_sel, pcie_axi_sel, ssi1_sel, ssi2_sel, ssi3_sel,
139 usdhc1_sel, usdhc2_sel, usdhc3_sel, usdhc4_sel, enfc_sel, emi_sel,
140 emi_slow_sel, vdo_axi_sel, vpu_axi_sel, cko1_sel, periph, periph2,
141 periph_clk2, periph2_clk2, ipg, ipg_per, esai_pred, esai_podf,
142 asrc_pred, asrc_podf, spdif_pred, spdif_podf, can_root, ecspi_root,
143 gpu2d_core_podf, gpu3d_core_podf, gpu3d_shader, ipu1_podf, ipu2_podf,
144 ldb_di0_podf, ldb_di1_podf, ipu1_di0_pre, ipu1_di1_pre, ipu2_di0_pre,
145 ipu2_di1_pre, hsi_tx_podf, ssi1_pred, ssi1_podf, ssi2_pred, ssi2_podf,
146 ssi3_pred, ssi3_podf, uart_serial_podf, usdhc1_podf, usdhc2_podf,
147 usdhc3_podf, usdhc4_podf, enfc_pred, enfc_podf, emi_podf,
148 emi_slow_podf, vpu_axi_podf, cko1_podf, axi, mmdc_ch0_axi_podf,
149 mmdc_ch1_axi_podf, arm, ahb, apbh_dma, asrc, can1_ipg, can1_serial,
150 can2_ipg, can2_serial, ecspi1, ecspi2, ecspi3, ecspi4, ecspi5, enet,
151 esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
152 hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
153 ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
154 mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4,
155 gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
156 ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
157 usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
Richard Zhao0987b592012-04-23 15:42:16 +0800[diff] [blame]158 pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
159 ssi2_ipg, ssi3_ipg, clk_max
Shawn Guo2acd1b62012-04-04 20:53:22 +0800[diff] [blame]160};
161
162static struct clk *clk[clk_max];
163
164int __init mx6q_clocks_init(void)
165{
166 struct device_node *np;
167 void __iomem *base;
168 struct clk *c;
169 int i, irq;
170
171 clk[dummy] = imx_clk_fixed("dummy", 0);
172
173 /* retrieve the freqency of fixed clocks from device tree */
174 for_each_compatible_node(np, NULL, "fixed-clock") {
175 u32 rate;
176 if (of_property_read_u32(np, "clock-frequency", &rate))
177 continue;
178
179 if (of_device_is_compatible(np, "fsl,imx-ckil"))
180 clk[ckil] = imx_clk_fixed("ckil", rate);
181 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
182 clk[ckih] = imx_clk_fixed("ckih", rate);
183 else if (of_device_is_compatible(np, "fsl,imx-osc"))
184 clk[osc] = imx_clk_fixed("osc", rate);
185 }
186
187 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
188 base = of_iomap(np, 0);
189 WARN_ON(!base);
190
191 /* type name parent_name base gate_mask div_mask */
192 clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x2000, 0x7f);
193 clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x2000, 0x1);
194 clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x2000, 0x3);
195 clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x2000, 0x7f);
196 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x2000, 0x7f);
197 clk[pll6_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll6_mlb", "osc", base + 0xd0, 0x2000, 0x0);
198 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3);
199 clk[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3);
200
201 /* name parent_name reg idx */
202 clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
203 clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
204 clk[pll2_pfd2_396m] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
205 clk[pll3_pfd0_720m] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
206 clk[pll3_pfd1_540m] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
207 clk[pll3_pfd2_508m] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
208 clk[pll3_pfd3_454m] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
209
210 /* name parent_name mult div */
211 clk[pll2_198m] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
212 clk[pll3_120m] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
213 clk[pll3_80m] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
214 clk[pll3_60m] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
215 clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
216
217 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
218 base = of_iomap(np, 0);
219 WARN_ON(!base);
220 ccm_base = base;
221
222 /* name reg shift width parent_names num_parents */
223 clk[step] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
224 clk[pll1_sw] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
225 clk[periph_pre] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
226 clk[periph2_pre] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
227 clk[periph_clk2_sel] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
228 clk[periph2_clk2_sel] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
229 clk[axi_sel] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
230 clk[esai_sel] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
231 clk[asrc_sel] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
232 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
233 clk[gpu2d_axi] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
234 clk[gpu3d_axi] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
235 clk[gpu2d_core_sel] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
236 clk[gpu3d_core_sel] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
237 clk[gpu3d_shader_sel] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
238 clk[ipu1_sel] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
239 clk[ipu2_sel] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
240 clk[ldb_di0_sel] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
241 clk[ldb_di1_sel] = imx_clk_mux("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
242 clk[ipu1_di0_pre_sel] = imx_clk_mux("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
243 clk[ipu1_di1_pre_sel] = imx_clk_mux("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
244 clk[ipu2_di0_pre_sel] = imx_clk_mux("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
245 clk[ipu2_di1_pre_sel] = imx_clk_mux("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels));
246 clk[ipu1_di0_sel] = imx_clk_mux("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels));
247 clk[ipu1_di1_sel] = imx_clk_mux("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels));
248 clk[ipu2_di0_sel] = imx_clk_mux("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels));
249 clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
250 clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
251 clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
252 clk[ssi1_sel] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
253 clk[ssi2_sel] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
254 clk[ssi3_sel] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
255 clk[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
256 clk[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
257 clk[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
258 clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
259 clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
260 clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels));
261 clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_sels, ARRAY_SIZE(emi_sels));
262 clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
263 clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
264 clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
265
266 /* name reg shift width busy: reg, shift parent_names num_parents */
267 clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
268 clk[periph2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
269
270 /* name parent_name reg shift width */
271 clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
272 clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
273 clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
274 clk[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6);
275 clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
276 clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
277 clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
278 clk[asrc_podf] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
279 clk[spdif_pred] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
280 clk[spdif_podf] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
281 clk[can_root] = imx_clk_divider("can_root", "pll3_usb_otg", base + 0x20, 2, 6);
282 clk[ecspi_root] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
283 clk[gpu2d_core_podf] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
284 clk[gpu3d_core_podf] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
285 clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
286 clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
287 clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
288 clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_sel", base + 0x20, 10, 1);
289 clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_sel", base + 0x20, 11, 1);
290 clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
291 clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
292 clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
293 clk[ipu2_di1_pre] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
294 clk[hsi_tx_podf] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
295 clk[ssi1_pred] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
296 clk[ssi1_podf] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
297 clk[ssi2_pred] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
298 clk[ssi2_podf] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
299 clk[ssi3_pred] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
300 clk[ssi3_podf] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
301 clk[uart_serial_podf] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
302 clk[usdhc1_podf] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
303 clk[usdhc2_podf] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
304 clk[usdhc3_podf] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
305 clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
306 clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
307 clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
308 clk[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3);
309 clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3);
310 clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
311 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
312
313 /* name parent_name reg shift width busy: reg, shift */
314 clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
315 clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
316 clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
317 clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
318 clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
319
320 /* name parent_name reg shift */
321 clk[apbh_dma] = imx_clk_gate2("apbh_dma", "ahb", base + 0x68, 4);
322 clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
323 clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
324 clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
325 clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
326 clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
327 clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
328 clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
329 clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
330 clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
331 clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
332 clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
333 clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
334 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
335 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
336 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
337 clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
338 clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
339 clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
340 clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
341 clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
342 clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
343 clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
344 clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
345 clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
346 clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
347 clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
348 clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
349 clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
350 clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
351 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
352 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
353 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
354 clk[mlb] = imx_clk_gate2("mlb", "pll6_mlb", base + 0x74, 18);
355 clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
356 clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
357 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
358 clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
359 clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
360 clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
361 clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
362 clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
363 clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
364 clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
365 clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
366 clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
367 clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
368 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
369 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
370 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
Richard Zhao0987b592012-04-23 15:42:16 +0800[diff] [blame]371 clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
372 clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
373 clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
Shawn Guo2acd1b62012-04-04 20:53:22 +0800[diff] [blame]374 clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
375 clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
376 clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
377 clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
378 clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
379 clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
380 clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
381 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
382 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
383 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
384
385 for (i = 0; i < ARRAY_SIZE(clk); i++)
386 if (IS_ERR(clk[i]))
387 pr_err("i.MX6q clk %d: register failed with %ld\n",
388 i, PTR_ERR(clk[i]));
389
390 clk_register_clkdev(clk[mmdc_ch0_axi], NULL, "mmdc_ch0_axi");
391 clk_register_clkdev(clk[mmdc_ch1_axi], NULL, "mmdc_ch1_axi");
392 clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
393 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
394 clk_register_clkdev(clk[twd], NULL, "smp_twd");
395 clk_register_clkdev(clk[usboh3], NULL, "usboh3");
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]396 clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
397 clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
398 clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
399 clk_register_clkdev(clk[uart_ipg], "ipg", "21e8000.serial");
400 clk_register_clkdev(clk[uart_serial], "per", "21ec000.serial");
401 clk_register_clkdev(clk[uart_ipg], "ipg", "21ec000.serial");
402 clk_register_clkdev(clk[uart_serial], "per", "21f0000.serial");
403 clk_register_clkdev(clk[uart_ipg], "ipg", "21f0000.serial");
404 clk_register_clkdev(clk[uart_serial], "per", "21f4000.serial");
405 clk_register_clkdev(clk[uart_ipg], "ipg", "21f4000.serial");
406 clk_register_clkdev(clk[enet], NULL, "2188000.ethernet");
Shawn Guo2acd1b62012-04-04 20:53:22 +0800[diff] [blame]407 clk_register_clkdev(clk[usdhc1], NULL, "2190000.usdhc");
408 clk_register_clkdev(clk[usdhc2], NULL, "2194000.usdhc");
409 clk_register_clkdev(clk[usdhc3], NULL, "2198000.usdhc");
410 clk_register_clkdev(clk[usdhc4], NULL, "219c000.usdhc");
411 clk_register_clkdev(clk[i2c1], NULL, "21a0000.i2c");
412 clk_register_clkdev(clk[i2c2], NULL, "21a4000.i2c");
413 clk_register_clkdev(clk[i2c3], NULL, "21a8000.i2c");
414 clk_register_clkdev(clk[ecspi1], NULL, "2008000.ecspi");
415 clk_register_clkdev(clk[ecspi2], NULL, "200c000.ecspi");
416 clk_register_clkdev(clk[ecspi3], NULL, "2010000.ecspi");
417 clk_register_clkdev(clk[ecspi4], NULL, "2014000.ecspi");
418 clk_register_clkdev(clk[ecspi5], NULL, "2018000.ecspi");
419 clk_register_clkdev(clk[sdma], NULL, "20ec000.sdma");
420 clk_register_clkdev(clk[dummy], NULL, "20bc000.wdog");
421 clk_register_clkdev(clk[dummy], NULL, "20c0000.wdog");
Richard Zhao0987b592012-04-23 15:42:16 +0800[diff] [blame]422 clk_register_clkdev(clk[ssi1_ipg], NULL, "2028000.ssi");
Richard Zhaoa2585612012-04-24 14:19:13 +0800[diff] [blame]423 clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
424 clk_register_clkdev(clk[ahb], "ahb", NULL);
425 clk_register_clkdev(clk[cko1], "cko1", NULL);
Shawn Guo2acd1b62012-04-04 20:53:22 +0800[diff] [blame]426
427 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) {
428 c = clk_get_sys(clks_init_on[i], NULL);
429 if (IS_ERR(c)) {
430 pr_err("%s: failed to get clk %s", __func__,
431 clks_init_on[i]);
432 return PTR_ERR(c);
433 }
434 clk_prepare_enable(c);
435 }
436
437 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
438 base = of_iomap(np, 0);
439 WARN_ON(!base);
440 irq = irq_of_parse_and_map(np, 0);
441 mxc_timer_init(NULL, base, irq);
442
443 return 0;
444}