Viresh Kumar | 07658d9 | 2012-04-16 23:57:51 +0530 | [diff] [blame] | 1 | /* |
| 2 | * DTS file for all SPEAr13xx SoCs |
| 3 | * |
| 4 | * Copyright 2012 Viresh Kumar <viresh.kumar@st.com> |
| 5 | * |
| 6 | * The code contained herein is licensed under the GNU General Public |
| 7 | * License. You may obtain a copy of the GNU General Public License |
| 8 | * Version 2 or later at the following locations: |
| 9 | * |
| 10 | * http://www.opensource.org/licenses/gpl-license.html |
| 11 | * http://www.gnu.org/copyleft/gpl.html |
| 12 | */ |
| 13 | |
| 14 | /include/ "skeleton.dtsi" |
| 15 | |
| 16 | / { |
| 17 | interrupt-parent = <&gic>; |
| 18 | |
| 19 | cpus { |
| 20 | #address-cells = <1>; |
| 21 | #size-cells = <0>; |
| 22 | |
| 23 | cpu@0 { |
| 24 | compatible = "arm,cortex-a9"; |
| 25 | reg = <0>; |
| 26 | next-level-cache = <&L2>; |
| 27 | }; |
| 28 | |
| 29 | cpu@1 { |
| 30 | compatible = "arm,cortex-a9"; |
| 31 | reg = <1>; |
| 32 | next-level-cache = <&L2>; |
| 33 | }; |
| 34 | }; |
| 35 | |
| 36 | gic: interrupt-controller@ec801000 { |
| 37 | compatible = "arm,cortex-a9-gic"; |
| 38 | interrupt-controller; |
| 39 | #interrupt-cells = <3>; |
| 40 | reg = < 0xec801000 0x1000 >, |
| 41 | < 0xec800100 0x0100 >; |
| 42 | }; |
| 43 | |
| 44 | pmu { |
| 45 | compatible = "arm,cortex-a9-pmu"; |
| 46 | interrupts = <0 8 0x04 |
| 47 | 0 9 0x04>; |
| 48 | }; |
| 49 | |
| 50 | L2: l2-cache { |
| 51 | compatible = "arm,pl310-cache"; |
| 52 | reg = <0xed000000 0x1000>; |
| 53 | cache-unified; |
| 54 | cache-level = <2>; |
| 55 | }; |
| 56 | |
| 57 | memory { |
| 58 | name = "memory"; |
| 59 | device_type = "memory"; |
| 60 | reg = <0 0x40000000>; |
| 61 | }; |
| 62 | |
| 63 | chosen { |
| 64 | bootargs = "console=ttyAMA0,115200"; |
| 65 | }; |
| 66 | |
| 67 | ahb { |
| 68 | #address-cells = <1>; |
| 69 | #size-cells = <1>; |
| 70 | compatible = "simple-bus"; |
| 71 | ranges = <0x50000000 0x50000000 0x10000000 |
| 72 | 0xb0000000 0xb0000000 0x10000000 |
| 73 | 0xe0000000 0xe0000000 0x10000000>; |
| 74 | |
| 75 | sdhci@b3000000 { |
| 76 | compatible = "st,sdhci-spear"; |
| 77 | reg = <0xb3000000 0x100>; |
| 78 | interrupts = <0 28 0x4>; |
| 79 | status = "disabled"; |
| 80 | }; |
| 81 | |
| 82 | cf@b2800000 { |
| 83 | compatible = "arasan,cf-spear1340"; |
| 84 | reg = <0xb2800000 0x100>; |
| 85 | interrupts = <0 29 0x4>; |
| 86 | status = "disabled"; |
| 87 | }; |
| 88 | |
| 89 | dma@ea800000 { |
| 90 | compatible = "snps,dma-spear1340"; |
| 91 | reg = <0xea800000 0x1000>; |
| 92 | interrupts = <0 19 0x4>; |
| 93 | status = "disabled"; |
| 94 | }; |
| 95 | |
| 96 | dma@eb000000 { |
| 97 | compatible = "snps,dma-spear1340"; |
| 98 | reg = <0xeb000000 0x1000>; |
| 99 | interrupts = <0 59 0x4>; |
| 100 | status = "disabled"; |
| 101 | }; |
| 102 | |
| 103 | fsmc: flash@b0000000 { |
| 104 | compatible = "st,spear600-fsmc-nand"; |
| 105 | #address-cells = <1>; |
| 106 | #size-cells = <1>; |
| 107 | reg = <0xb0000000 0x1000 /* FSMC Register */ |
| 108 | 0xb0800000 0x0010>; /* NAND Base */ |
| 109 | reg-names = "fsmc_regs", "nand_data"; |
| 110 | interrupts = <0 20 0x4 |
| 111 | 0 21 0x4 |
| 112 | 0 22 0x4 |
| 113 | 0 23 0x4>; |
| 114 | st,ale-off = <0x20000>; |
| 115 | st,cle-off = <0x10000>; |
| 116 | status = "disabled"; |
| 117 | }; |
| 118 | |
| 119 | gmac0: eth@e2000000 { |
| 120 | compatible = "st,spear600-gmac"; |
| 121 | reg = <0xe2000000 0x8000>; |
| 122 | interrupts = <0 23 0x4 |
| 123 | 0 24 0x4>; |
| 124 | interrupt-names = "macirq", "eth_wake_irq"; |
| 125 | status = "disabled"; |
| 126 | }; |
| 127 | |
| 128 | smi: flash@ea000000 { |
| 129 | compatible = "st,spear600-smi"; |
| 130 | #address-cells = <1>; |
| 131 | #size-cells = <1>; |
| 132 | reg = <0xea000000 0x1000>; |
| 133 | interrupts = <0 30 0x4>; |
| 134 | status = "disabled"; |
| 135 | }; |
| 136 | |
| 137 | spi0: spi@e0100000 { |
| 138 | compatible = "arm,pl022", "arm,primecell"; |
| 139 | reg = <0xe0100000 0x1000>; |
| 140 | interrupts = <0 31 0x4>; |
| 141 | status = "disabled"; |
| 142 | }; |
| 143 | |
| 144 | ehci@e4800000 { |
| 145 | compatible = "st,spear600-ehci", "usb-ehci"; |
| 146 | reg = <0xe4800000 0x1000>; |
| 147 | interrupts = <0 64 0x4>; |
| 148 | status = "disabled"; |
| 149 | }; |
| 150 | |
| 151 | ehci@e5800000 { |
| 152 | compatible = "st,spear600-ehci", "usb-ehci"; |
| 153 | reg = <0xe5800000 0x1000>; |
| 154 | interrupts = <0 66 0x4>; |
| 155 | status = "disabled"; |
| 156 | }; |
| 157 | |
| 158 | ohci@e4000000 { |
| 159 | compatible = "st,spear600-ohci", "usb-ohci"; |
| 160 | reg = <0xe4000000 0x1000>; |
| 161 | interrupts = <0 65 0x4>; |
| 162 | status = "disabled"; |
| 163 | }; |
| 164 | |
| 165 | ohci@e5000000 { |
| 166 | compatible = "st,spear600-ohci", "usb-ohci"; |
| 167 | reg = <0xe5000000 0x1000>; |
| 168 | interrupts = <0 67 0x4>; |
| 169 | status = "disabled"; |
| 170 | }; |
| 171 | |
| 172 | apb { |
| 173 | #address-cells = <1>; |
| 174 | #size-cells = <1>; |
| 175 | compatible = "simple-bus"; |
| 176 | ranges = <0x50000000 0x50000000 0x10000000 |
| 177 | 0xb0000000 0xb0000000 0x10000000 |
| 178 | 0xe0000000 0xe0000000 0x10000000>; |
| 179 | |
| 180 | gpio0: gpio@e0600000 { |
| 181 | compatible = "arm,pl061", "arm,primecell"; |
| 182 | reg = <0xe0600000 0x1000>; |
| 183 | interrupts = <0 24 0x4>; |
| 184 | gpio-controller; |
| 185 | #gpio-cells = <2>; |
| 186 | interrupt-controller; |
| 187 | #interrupt-cells = <2>; |
| 188 | status = "disabled"; |
| 189 | }; |
| 190 | |
| 191 | gpio1: gpio@e0680000 { |
| 192 | compatible = "arm,pl061", "arm,primecell"; |
| 193 | reg = <0xe0680000 0x1000>; |
| 194 | interrupts = <0 25 0x4>; |
| 195 | gpio-controller; |
| 196 | #gpio-cells = <2>; |
| 197 | interrupt-controller; |
| 198 | #interrupt-cells = <2>; |
| 199 | status = "disabled"; |
| 200 | }; |
| 201 | |
| 202 | kbd@e0300000 { |
| 203 | compatible = "st,spear300-kbd"; |
| 204 | reg = <0xe0300000 0x1000>; |
| 205 | status = "disabled"; |
| 206 | }; |
| 207 | |
| 208 | i2c0: i2c@e0280000 { |
| 209 | #address-cells = <1>; |
| 210 | #size-cells = <0>; |
| 211 | compatible = "snps,designware-i2c"; |
| 212 | reg = <0xe0280000 0x1000>; |
| 213 | interrupts = <0 41 0x4>; |
| 214 | status = "disabled"; |
| 215 | }; |
| 216 | |
| 217 | rtc@e0580000 { |
| 218 | compatible = "st,spear-rtc"; |
| 219 | reg = <0xe0580000 0x1000>; |
| 220 | interrupts = <0 36 0x4>; |
| 221 | status = "disabled"; |
| 222 | }; |
| 223 | |
| 224 | serial@e0000000 { |
| 225 | compatible = "arm,pl011", "arm,primecell"; |
| 226 | reg = <0xe0000000 0x1000>; |
| 227 | interrupts = <0 36 0x4>; |
| 228 | status = "disabled"; |
| 229 | }; |
| 230 | |
| 231 | adc@e0080000 { |
| 232 | compatible = "st,spear600-adc"; |
| 233 | reg = <0xe0080000 0x1000>; |
| 234 | interrupts = <0 44 0x4>; |
| 235 | status = "disabled"; |
| 236 | }; |
| 237 | |
| 238 | timer@e0380000 { |
| 239 | compatible = "st,spear-timer"; |
| 240 | reg = <0xe0380000 0x400>; |
| 241 | interrupts = <0 37 0x4>; |
| 242 | }; |
| 243 | |
| 244 | timer@ec800600 { |
| 245 | compatible = "arm,cortex-a9-twd-timer"; |
| 246 | reg = <0xec800600 0x20>; |
| 247 | interrupts = <1 13 0x301>; |
| 248 | }; |
| 249 | |
| 250 | wdt@ec800620 { |
| 251 | compatible = "arm,cortex-a9-twd-wdt"; |
| 252 | reg = <0xec800620 0x20>; |
| 253 | status = "disabled"; |
| 254 | }; |
| 255 | |
| 256 | thermal@e07008c4 { |
| 257 | compatible = "st,thermal-spear1340"; |
| 258 | reg = <0xe07008c4 0x4>; |
| 259 | }; |
| 260 | }; |
| 261 | }; |
| 262 | }; |