blob: 1c317de2617623438bd169d9ba7cb89623139794 [file] [log] [blame]
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +08001/*
2 * sgtl5000.h - SGTL5000 audio codec interface
3 *
4 * Copyright 2010-2011 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef _SGTL5000_H
12#define _SGTL5000_H
13
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +080014/*
Fabio Estevam271f1932013-05-03 18:04:24 -030015 * Registers addresses
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +080016 */
17#define SGTL5000_CHIP_ID 0x0000
18#define SGTL5000_CHIP_DIG_POWER 0x0002
19#define SGTL5000_CHIP_CLK_CTRL 0x0004
20#define SGTL5000_CHIP_I2S_CTRL 0x0006
21#define SGTL5000_CHIP_SSS_CTRL 0x000a
22#define SGTL5000_CHIP_ADCDAC_CTRL 0x000e
23#define SGTL5000_CHIP_DAC_VOL 0x0010
24#define SGTL5000_CHIP_PAD_STRENGTH 0x0014
25#define SGTL5000_CHIP_ANA_ADC_CTRL 0x0020
26#define SGTL5000_CHIP_ANA_HP_CTRL 0x0022
27#define SGTL5000_CHIP_ANA_CTRL 0x0024
28#define SGTL5000_CHIP_LINREG_CTRL 0x0026
29#define SGTL5000_CHIP_REF_CTRL 0x0028
30#define SGTL5000_CHIP_MIC_CTRL 0x002a
31#define SGTL5000_CHIP_LINE_OUT_CTRL 0x002c
32#define SGTL5000_CHIP_LINE_OUT_VOL 0x002e
33#define SGTL5000_CHIP_ANA_POWER 0x0030
34#define SGTL5000_CHIP_PLL_CTRL 0x0032
35#define SGTL5000_CHIP_CLK_TOP_CTRL 0x0034
36#define SGTL5000_CHIP_ANA_STATUS 0x0036
37#define SGTL5000_CHIP_SHORT_CTRL 0x003c
38#define SGTL5000_CHIP_ANA_TEST2 0x003a
39#define SGTL5000_DAP_CTRL 0x0100
40#define SGTL5000_DAP_PEQ 0x0102
41#define SGTL5000_DAP_BASS_ENHANCE 0x0104
42#define SGTL5000_DAP_BASS_ENHANCE_CTRL 0x0106
43#define SGTL5000_DAP_AUDIO_EQ 0x0108
44#define SGTL5000_DAP_SURROUND 0x010a
45#define SGTL5000_DAP_FLT_COEF_ACCESS 0x010c
46#define SGTL5000_DAP_COEF_WR_B0_MSB 0x010e
47#define SGTL5000_DAP_COEF_WR_B0_LSB 0x0110
48#define SGTL5000_DAP_EQ_BASS_BAND0 0x0116
49#define SGTL5000_DAP_EQ_BASS_BAND1 0x0118
50#define SGTL5000_DAP_EQ_BASS_BAND2 0x011a
51#define SGTL5000_DAP_EQ_BASS_BAND3 0x011c
52#define SGTL5000_DAP_EQ_BASS_BAND4 0x011e
53#define SGTL5000_DAP_MAIN_CHAN 0x0120
54#define SGTL5000_DAP_MIX_CHAN 0x0122
55#define SGTL5000_DAP_AVC_CTRL 0x0124
56#define SGTL5000_DAP_AVC_THRESHOLD 0x0126
57#define SGTL5000_DAP_AVC_ATTACK 0x0128
58#define SGTL5000_DAP_AVC_DECAY 0x012a
59#define SGTL5000_DAP_COEF_WR_B1_MSB 0x012c
60#define SGTL5000_DAP_COEF_WR_B1_LSB 0x012e
61#define SGTL5000_DAP_COEF_WR_B2_MSB 0x0130
62#define SGTL5000_DAP_COEF_WR_B2_LSB 0x0132
63#define SGTL5000_DAP_COEF_WR_A1_MSB 0x0134
64#define SGTL5000_DAP_COEF_WR_A1_LSB 0x0136
65#define SGTL5000_DAP_COEF_WR_A2_MSB 0x0138
66#define SGTL5000_DAP_COEF_WR_A2_LSB 0x013a
67
68/*
69 * Field Definitions.
70 */
71
72/*
73 * SGTL5000_CHIP_ID
74 */
75#define SGTL5000_PARTID_MASK 0xff00
76#define SGTL5000_PARTID_SHIFT 8
77#define SGTL5000_PARTID_WIDTH 8
78#define SGTL5000_PARTID_PART_ID 0xa0
79#define SGTL5000_REVID_MASK 0x00ff
80#define SGTL5000_REVID_SHIFT 0
81#define SGTL5000_REVID_WIDTH 8
82
83/*
84 * SGTL5000_CHIP_DIG_POWER
85 */
86#define SGTL5000_ADC_EN 0x0040
87#define SGTL5000_DAC_EN 0x0020
88#define SGTL5000_DAP_POWERUP 0x0010
89#define SGTL5000_I2S_OUT_POWERUP 0x0002
90#define SGTL5000_I2S_IN_POWERUP 0x0001
91
92/*
93 * SGTL5000_CHIP_CLK_CTRL
94 */
95#define SGTL5000_RATE_MODE_MASK 0x0030
96#define SGTL5000_RATE_MODE_SHIFT 4
97#define SGTL5000_RATE_MODE_WIDTH 2
98#define SGTL5000_RATE_MODE_DIV_1 0
99#define SGTL5000_RATE_MODE_DIV_2 1
100#define SGTL5000_RATE_MODE_DIV_4 2
101#define SGTL5000_RATE_MODE_DIV_6 3
102#define SGTL5000_SYS_FS_MASK 0x000c
103#define SGTL5000_SYS_FS_SHIFT 2
104#define SGTL5000_SYS_FS_WIDTH 2
105#define SGTL5000_SYS_FS_32k 0x0
106#define SGTL5000_SYS_FS_44_1k 0x1
107#define SGTL5000_SYS_FS_48k 0x2
108#define SGTL5000_SYS_FS_96k 0x3
109#define SGTL5000_MCLK_FREQ_MASK 0x0003
110#define SGTL5000_MCLK_FREQ_SHIFT 0
111#define SGTL5000_MCLK_FREQ_WIDTH 2
112#define SGTL5000_MCLK_FREQ_256FS 0x0
113#define SGTL5000_MCLK_FREQ_384FS 0x1
114#define SGTL5000_MCLK_FREQ_512FS 0x2
115#define SGTL5000_MCLK_FREQ_PLL 0x3
116
117/*
118 * SGTL5000_CHIP_I2S_CTRL
119 */
120#define SGTL5000_I2S_SCLKFREQ_MASK 0x0100
121#define SGTL5000_I2S_SCLKFREQ_SHIFT 8
122#define SGTL5000_I2S_SCLKFREQ_WIDTH 1
123#define SGTL5000_I2S_SCLKFREQ_64FS 0x0
124#define SGTL5000_I2S_SCLKFREQ_32FS 0x1 /* Not for RJ mode */
125#define SGTL5000_I2S_MASTER 0x0080
126#define SGTL5000_I2S_SCLK_INV 0x0040
127#define SGTL5000_I2S_DLEN_MASK 0x0030
128#define SGTL5000_I2S_DLEN_SHIFT 4
129#define SGTL5000_I2S_DLEN_WIDTH 2
130#define SGTL5000_I2S_DLEN_32 0x0
131#define SGTL5000_I2S_DLEN_24 0x1
132#define SGTL5000_I2S_DLEN_20 0x2
133#define SGTL5000_I2S_DLEN_16 0x3
134#define SGTL5000_I2S_MODE_MASK 0x000c
135#define SGTL5000_I2S_MODE_SHIFT 2
136#define SGTL5000_I2S_MODE_WIDTH 2
137#define SGTL5000_I2S_MODE_I2S_LJ 0x0
138#define SGTL5000_I2S_MODE_RJ 0x1
139#define SGTL5000_I2S_MODE_PCM 0x2
140#define SGTL5000_I2S_LRALIGN 0x0002
141#define SGTL5000_I2S_LRPOL 0x0001 /* set for which mode */
142
143/*
144 * SGTL5000_CHIP_SSS_CTRL
145 */
146#define SGTL5000_DAP_MIX_LRSWAP 0x4000
147#define SGTL5000_DAP_LRSWAP 0x2000
148#define SGTL5000_DAC_LRSWAP 0x1000
149#define SGTL5000_I2S_OUT_LRSWAP 0x0400
150#define SGTL5000_DAP_MIX_SEL_MASK 0x0300
151#define SGTL5000_DAP_MIX_SEL_SHIFT 8
152#define SGTL5000_DAP_MIX_SEL_WIDTH 2
153#define SGTL5000_DAP_MIX_SEL_ADC 0x0
154#define SGTL5000_DAP_MIX_SEL_I2S_IN 0x1
155#define SGTL5000_DAP_SEL_MASK 0x00c0
156#define SGTL5000_DAP_SEL_SHIFT 6
157#define SGTL5000_DAP_SEL_WIDTH 2
158#define SGTL5000_DAP_SEL_ADC 0x0
159#define SGTL5000_DAP_SEL_I2S_IN 0x1
160#define SGTL5000_DAC_SEL_MASK 0x0030
161#define SGTL5000_DAC_SEL_SHIFT 4
162#define SGTL5000_DAC_SEL_WIDTH 2
163#define SGTL5000_DAC_SEL_ADC 0x0
164#define SGTL5000_DAC_SEL_I2S_IN 0x1
165#define SGTL5000_DAC_SEL_DAP 0x3
166#define SGTL5000_I2S_OUT_SEL_MASK 0x0003
167#define SGTL5000_I2S_OUT_SEL_SHIFT 0
168#define SGTL5000_I2S_OUT_SEL_WIDTH 2
169#define SGTL5000_I2S_OUT_SEL_ADC 0x0
170#define SGTL5000_I2S_OUT_SEL_I2S_IN 0x1
171#define SGTL5000_I2S_OUT_SEL_DAP 0x3
172
173/*
174 * SGTL5000_CHIP_ADCDAC_CTRL
175 */
176#define SGTL5000_VOL_BUSY_DAC_RIGHT 0x2000
177#define SGTL5000_VOL_BUSY_DAC_LEFT 0x1000
178#define SGTL5000_DAC_VOL_RAMP_EN 0x0200
179#define SGTL5000_DAC_VOL_RAMP_EXPO 0x0100
180#define SGTL5000_DAC_MUTE_RIGHT 0x0008
181#define SGTL5000_DAC_MUTE_LEFT 0x0004
182#define SGTL5000_ADC_HPF_FREEZE 0x0002
183#define SGTL5000_ADC_HPF_BYPASS 0x0001
184
185/*
186 * SGTL5000_CHIP_DAC_VOL
187 */
188#define SGTL5000_DAC_VOL_RIGHT_MASK 0xff00
189#define SGTL5000_DAC_VOL_RIGHT_SHIFT 8
190#define SGTL5000_DAC_VOL_RIGHT_WIDTH 8
191#define SGTL5000_DAC_VOL_LEFT_MASK 0x00ff
192#define SGTL5000_DAC_VOL_LEFT_SHIFT 0
193#define SGTL5000_DAC_VOL_LEFT_WIDTH 8
194
195/*
196 * SGTL5000_CHIP_PAD_STRENGTH
197 */
198#define SGTL5000_PAD_I2S_LRCLK_MASK 0x0300
199#define SGTL5000_PAD_I2S_LRCLK_SHIFT 8
200#define SGTL5000_PAD_I2S_LRCLK_WIDTH 2
201#define SGTL5000_PAD_I2S_SCLK_MASK 0x00c0
202#define SGTL5000_PAD_I2S_SCLK_SHIFT 6
203#define SGTL5000_PAD_I2S_SCLK_WIDTH 2
204#define SGTL5000_PAD_I2S_DOUT_MASK 0x0030
205#define SGTL5000_PAD_I2S_DOUT_SHIFT 4
206#define SGTL5000_PAD_I2S_DOUT_WIDTH 2
207#define SGTL5000_PAD_I2C_SDA_MASK 0x000c
208#define SGTL5000_PAD_I2C_SDA_SHIFT 2
209#define SGTL5000_PAD_I2C_SDA_WIDTH 2
210#define SGTL5000_PAD_I2C_SCL_MASK 0x0003
211#define SGTL5000_PAD_I2C_SCL_SHIFT 0
212#define SGTL5000_PAD_I2C_SCL_WIDTH 2
213
214/*
215 * SGTL5000_CHIP_ANA_ADC_CTRL
216 */
217#define SGTL5000_ADC_VOL_M6DB 0x0100
218#define SGTL5000_ADC_VOL_RIGHT_MASK 0x00f0
219#define SGTL5000_ADC_VOL_RIGHT_SHIFT 4
220#define SGTL5000_ADC_VOL_RIGHT_WIDTH 4
221#define SGTL5000_ADC_VOL_LEFT_MASK 0x000f
222#define SGTL5000_ADC_VOL_LEFT_SHIFT 0
223#define SGTL5000_ADC_VOL_LEFT_WIDTH 4
224
225/*
226 * SGTL5000_CHIP_ANA_HP_CTRL
227 */
228#define SGTL5000_HP_VOL_RIGHT_MASK 0x7f00
229#define SGTL5000_HP_VOL_RIGHT_SHIFT 8
230#define SGTL5000_HP_VOL_RIGHT_WIDTH 7
231#define SGTL5000_HP_VOL_LEFT_MASK 0x007f
232#define SGTL5000_HP_VOL_LEFT_SHIFT 0
233#define SGTL5000_HP_VOL_LEFT_WIDTH 7
234
235/*
236 * SGTL5000_CHIP_ANA_CTRL
237 */
238#define SGTL5000_LINE_OUT_MUTE 0x0100
239#define SGTL5000_HP_SEL_MASK 0x0040
240#define SGTL5000_HP_SEL_SHIFT 6
241#define SGTL5000_HP_SEL_WIDTH 1
242#define SGTL5000_HP_SEL_DAC 0x0
243#define SGTL5000_HP_SEL_LINE_IN 0x1
244#define SGTL5000_HP_ZCD_EN 0x0020
245#define SGTL5000_HP_MUTE 0x0010
246#define SGTL5000_ADC_SEL_MASK 0x0004
247#define SGTL5000_ADC_SEL_SHIFT 2
248#define SGTL5000_ADC_SEL_WIDTH 1
249#define SGTL5000_ADC_SEL_MIC 0x0
250#define SGTL5000_ADC_SEL_LINE_IN 0x1
251#define SGTL5000_ADC_ZCD_EN 0x0002
252#define SGTL5000_ADC_MUTE 0x0001
253
254/*
255 * SGTL5000_CHIP_LINREG_CTRL
256 */
257#define SGTL5000_VDDC_MAN_ASSN_MASK 0x0040
258#define SGTL5000_VDDC_MAN_ASSN_SHIFT 6
259#define SGTL5000_VDDC_MAN_ASSN_WIDTH 1
260#define SGTL5000_VDDC_MAN_ASSN_VDDA 0x0
261#define SGTL5000_VDDC_MAN_ASSN_VDDIO 0x1
262#define SGTL5000_VDDC_ASSN_OVRD 0x0020
263#define SGTL5000_LINREG_VDDD_MASK 0x000f
264#define SGTL5000_LINREG_VDDD_SHIFT 0
265#define SGTL5000_LINREG_VDDD_WIDTH 4
266
267/*
268 * SGTL5000_CHIP_REF_CTRL
269 */
270#define SGTL5000_ANA_GND_MASK 0x01f0
271#define SGTL5000_ANA_GND_SHIFT 4
272#define SGTL5000_ANA_GND_WIDTH 5
273#define SGTL5000_ANA_GND_BASE 800 /* mv */
274#define SGTL5000_ANA_GND_STP 25 /*mv */
275#define SGTL5000_BIAS_CTRL_MASK 0x000e
276#define SGTL5000_BIAS_CTRL_SHIFT 1
277#define SGTL5000_BIAS_CTRL_WIDTH 3
Axel Linb101acf2015-07-22 11:27:45 +0800278#define SGTL5000_SMALL_POP 1
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800279
280/*
281 * SGTL5000_CHIP_MIC_CTRL
282 */
Axel Lin56c09aa2011-10-19 10:54:56 +0800283#define SGTL5000_BIAS_R_MASK 0x0300
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800284#define SGTL5000_BIAS_R_SHIFT 8
285#define SGTL5000_BIAS_R_WIDTH 2
286#define SGTL5000_BIAS_R_off 0x0
287#define SGTL5000_BIAS_R_2K 0x1
288#define SGTL5000_BIAS_R_4k 0x2
289#define SGTL5000_BIAS_R_8k 0x3
290#define SGTL5000_BIAS_VOLT_MASK 0x0070
291#define SGTL5000_BIAS_VOLT_SHIFT 4
292#define SGTL5000_BIAS_VOLT_WIDTH 3
293#define SGTL5000_MIC_GAIN_MASK 0x0003
294#define SGTL5000_MIC_GAIN_SHIFT 0
295#define SGTL5000_MIC_GAIN_WIDTH 2
296
297/*
298 * SGTL5000_CHIP_LINE_OUT_CTRL
299 */
300#define SGTL5000_LINE_OUT_CURRENT_MASK 0x0f00
301#define SGTL5000_LINE_OUT_CURRENT_SHIFT 8
302#define SGTL5000_LINE_OUT_CURRENT_WIDTH 4
303#define SGTL5000_LINE_OUT_CURRENT_180u 0x0
304#define SGTL5000_LINE_OUT_CURRENT_270u 0x1
305#define SGTL5000_LINE_OUT_CURRENT_360u 0x3
306#define SGTL5000_LINE_OUT_CURRENT_450u 0x7
307#define SGTL5000_LINE_OUT_CURRENT_540u 0xf
308#define SGTL5000_LINE_OUT_GND_MASK 0x003f
309#define SGTL5000_LINE_OUT_GND_SHIFT 0
310#define SGTL5000_LINE_OUT_GND_WIDTH 6
311#define SGTL5000_LINE_OUT_GND_BASE 800 /* mv */
312#define SGTL5000_LINE_OUT_GND_STP 25
313#define SGTL5000_LINE_OUT_GND_MAX 0x23
314
315/*
316 * SGTL5000_CHIP_LINE_OUT_VOL
317 */
318#define SGTL5000_LINE_OUT_VOL_RIGHT_MASK 0x1f00
319#define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT 8
320#define SGTL5000_LINE_OUT_VOL_RIGHT_WIDTH 5
321#define SGTL5000_LINE_OUT_VOL_LEFT_MASK 0x001f
322#define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT 0
323#define SGTL5000_LINE_OUT_VOL_LEFT_WIDTH 5
324
325/*
326 * SGTL5000_CHIP_ANA_POWER
327 */
328#define SGTL5000_DAC_STEREO 0x4000
329#define SGTL5000_LINREG_SIMPLE_POWERUP 0x2000
330#define SGTL5000_STARTUP_POWERUP 0x1000
331#define SGTL5000_VDDC_CHRGPMP_POWERUP 0x0800
332#define SGTL5000_PLL_POWERUP 0x0400
333#define SGTL5000_LINEREG_D_POWERUP 0x0200
334#define SGTL5000_VCOAMP_POWERUP 0x0100
335#define SGTL5000_VAG_POWERUP 0x0080
336#define SGTL5000_ADC_STEREO 0x0040
337#define SGTL5000_REFTOP_POWERUP 0x0020
338#define SGTL5000_HP_POWERUP 0x0010
339#define SGTL5000_DAC_POWERUP 0x0008
340#define SGTL5000_CAPLESS_HP_POWERUP 0x0004
341#define SGTL5000_ADC_POWERUP 0x0002
342#define SGTL5000_LINE_OUT_POWERUP 0x0001
343
344/*
345 * SGTL5000_CHIP_PLL_CTRL
346 */
347#define SGTL5000_PLL_INT_DIV_MASK 0xf800
348#define SGTL5000_PLL_INT_DIV_SHIFT 11
349#define SGTL5000_PLL_INT_DIV_WIDTH 5
Fabio Estevam5c78dfe2013-07-04 20:01:03 -0300350#define SGTL5000_PLL_FRAC_DIV_MASK 0x07ff
Zeng Zhaoming9b34e6c2011-02-24 02:08:21 +0800351#define SGTL5000_PLL_FRAC_DIV_SHIFT 0
352#define SGTL5000_PLL_FRAC_DIV_WIDTH 11
353
354/*
355 * SGTL5000_CHIP_CLK_TOP_CTRL
356 */
357#define SGTL5000_INT_OSC_EN 0x0800
358#define SGTL5000_INPUT_FREQ_DIV2 0x0008
359
360/*
361 * SGTL5000_CHIP_ANA_STATUS
362 */
363#define SGTL5000_HP_LRSHORT 0x0200
364#define SGTL5000_CAPLESS_SHORT 0x0100
365#define SGTL5000_PLL_LOCKED 0x0010
366
367/*
368 * SGTL5000_CHIP_SHORT_CTRL
369 */
370#define SGTL5000_LVLADJR_MASK 0x7000
371#define SGTL5000_LVLADJR_SHIFT 12
372#define SGTL5000_LVLADJR_WIDTH 3
373#define SGTL5000_LVLADJL_MASK 0x0700
374#define SGTL5000_LVLADJL_SHIFT 8
375#define SGTL5000_LVLADJL_WIDTH 3
376#define SGTL5000_LVLADJC_MASK 0x0070
377#define SGTL5000_LVLADJC_SHIFT 4
378#define SGTL5000_LVLADJC_WIDTH 3
379#define SGTL5000_LR_SHORT_MOD_MASK 0x000c
380#define SGTL5000_LR_SHORT_MOD_SHIFT 2
381#define SGTL5000_LR_SHORT_MOD_WIDTH 2
382#define SGTL5000_CM_SHORT_MOD_MASK 0x0003
383#define SGTL5000_CM_SHORT_MOD_SHIFT 0
384#define SGTL5000_CM_SHORT_MOD_WIDTH 2
385
386/*
387 *SGTL5000_CHIP_ANA_TEST2
388 */
389#define SGTL5000_MONO_DAC 0x1000
390
391/*
392 * SGTL5000_DAP_CTRL
393 */
394#define SGTL5000_DAP_MIX_EN 0x0010
395#define SGTL5000_DAP_EN 0x0001
396
397#define SGTL5000_SYSCLK 0x00
398#define SGTL5000_LRCLK 0x01
399
400#endif